1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32#ifndef __CONFIG_H
33#define __CONFIG_H
34
35
36
37
38
39
40
41
42#define MPC85xx_ATUM_CLKOCR 0x80000002
43
44
45#define CONFIG_BOOKE 1
46#define CONFIG_E500 1
47#define CONFIG_MPC85xx 1
48#define CONFIG_MPC8548 1
49
50#define CONFIG_PCI 1
51#define CONFIG_PCI1 1
52#define CONFIG_PCIE1 1
53#define CONFIG_PCI2 1
54#define CONFIG_FSL_PCI_INIT 1
55
56#define CONFIG_TSEC_ENET 1
57#define CONFIG_ENV_OVERWRITE
58
59#define CONFIG_INTERRUPTS
60
61#define CONFIG_FSL_LAW 1
62
63#define CONFIG_SYS_CLK_FREQ 33000000
64
65
66
67
68#define CONFIG_L2_CACHE
69#define CONFIG_BTB
70#define CONFIG_CLEAR_LAW0
71
72
73
74
75#define CONFIG_ENABLE_36BIT_PHYS 1
76
77#define CONFIG_BOARD_EARLY_INIT_F 1
78
79#define CONFIG_CMD_SDRAM 1
80#define CONFIG_ENABLE_36BIT_PHYS 1
81#undef CONFIG_SYS_DRAM_TEST
82#define CONFIG_SYS_MEMTEST_START 0x00200000
83#define CONFIG_SYS_MEMTEST_END 0x00400000
84
85
86
87
88
89#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
90#define CONFIG_SYS_CCSRBAR 0xe0000000
91#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
92#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
93
94#define PCI_SPEED 33333000
95#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
96#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
97#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
98
99
100#define CONFIG_FSL_DDR2
101#undef CONFIG_FSL_DDR_INTERACTIVE
102#define CONFIG_DDR_ECC
103#define CONFIG_SPD_EEPROM
104#define CONFIG_DDR_SPD
105
106#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
107#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
108
109#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
110#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
111#define CONFIG_VERY_BIG_RAM
112
113#define CONFIG_NUM_DDR_CONTROLLERS 1
114#define CONFIG_DIMM_SLOTS_PER_CTLR 1
115#define CONFIG_CHIP_SELECTS_PER_CTRL 2
116
117
118#define SPD_EEPROM_ADDRESS 0x51
119
120
121#define CONFIG_SYS_SDRAM_SIZE 1024
122#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
123#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000102
124#define CONFIG_SYS_DDR_TIMING_0 0x00260802
125#define CONFIG_SYS_DDR_TIMING_1 0x38355322
126#define CONFIG_SYS_DDR_TIMING_2 0x039048c7
127#define CONFIG_SYS_DDR_CONTROL 0xc2000000
128#define CONFIG_SYS_DDR_MODE 0x00000432
129#define CONFIG_SYS_DDR_INTERVAL 0x05150100
130#define DDR_SDRAM_CFG 0x43000000
131
132#undef CONFIG_CLOCKS_IN_MHZ
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166#define CONFIG_SYS_BOOT_BLOCK 0xf8000000
167#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK
168
169#define CONFIG_SYS_BR0_PRELIM 0xf8001001
170
171#define CONFIG_SYS_OR0_PRELIM 0xf8000E65
172
173#define CONFIG_SYS_MAX_FLASH_BANKS 1
174#define CONFIG_SYS_MAX_FLASH_SECT 1024
175#undef CONFIG_SYS_FLASH_CHECKSUM
176#define CONFIG_SYS_FLASH_ERASE_TOUT 512000
177#define CONFIG_SYS_FLASH_WRITE_TOUT 8000
178
179
180#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
181
182#define CONFIG_FLASH_CFI_DRIVER 1
183#define CONFIG_SYS_FLASH_CFI 1
184#define CONFIG_SYS_FLASH_EMPTY_INFO
185
186
187
188
189#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000
190
191
192#define CONFIG_SYS_INIT_RAM_LOCK 1
193#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
194#define CONFIG_SYS_INIT_RAM_END 0x4000
195
196#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
197
198#define CONFIG_SYS_GBL_DATA_SIZE 128
199#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
200#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
201
202#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
203#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
204
205
206#define CONFIG_CONS_INDEX 1
207#undef CONFIG_SERIAL_SOFTWARE_FIFO
208#define CONFIG_SYS_NS16550
209#define CONFIG_SYS_NS16550_SERIAL
210#define CONFIG_SYS_NS16550_REG_SIZE 1
211#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
212
213#define CONFIG_SYS_BAUDRATE_TABLE \
214 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
215
216#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
217#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
218
219
220#define CONFIG_SYS_HUSH_PARSER
221#ifdef CONFIG_SYS_HUSH_PARSER
222#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
223#endif
224
225
226#define CONFIG_OF_LIBFDT 1
227#define CONFIG_OF_BOARD_SETUP 1
228
229
230
231
232#define CONFIG_FSL_I2C
233#define CONFIG_HARD_I2C
234#undef CONFIG_SOFT_I2C
235#define CONFIG_SYS_I2C_SPEED 400000
236#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
237#define CONFIG_SYS_I2C_SLAVE 0x7F
238#define CONFIG_SYS_I2C_NOPROBES {0x69}
239#define CONFIG_SYS_I2C_OFFSET 0x3000
240
241
242
243
244
245#define CONFIG_SYS_PCI_PHYS 0x80000000
246
247#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
248#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
249#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
250#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
251#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
252#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
253
254#ifdef CONFIG_PCI2
255#define CONFIG_SYS_PCI2_MEM_BASE 0xC0000000
256#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
257#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000
258#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
259#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
260#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000
261#endif
262
263#ifdef CONFIG_PCIE1
264#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000
265#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE
266#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000
267#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
268#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
269#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000
270#endif
271
272
273#if !defined(CONFIG_PCI_PNP)
274 #define PCI_ENET0_IOADDR 0xe0000000
275 #define PCI_ENET0_MEMADDR 0xe0000000
276 #define PCI_IDSEL_NUMBER 0x0c
277#endif
278
279#if defined(CONFIG_PCI)
280
281#define CONFIG_NET_MULTI
282#define CONFIG_PCI_PNP
283
284#undef CONFIG_EEPRO100
285#undef CONFIG_TULIP
286
287#undef CONFIG_PCI_SCAN_SHOW
288
289#endif
290
291#if defined(CONFIG_TSEC_ENET)
292
293#ifndef CONFIG_NET_MULTI
294#define CONFIG_NET_MULTI 1
295#endif
296
297#define CONFIG_MII 1
298#define CONFIG_TSEC1 1
299#define CONFIG_TSEC1_NAME "eTSEC0"
300#define CONFIG_TSEC2 1
301#define CONFIG_TSEC2_NAME "eTSEC1"
302#define CONFIG_TSEC3 1
303#define CONFIG_TSEC3_NAME "eTSEC2"
304#define CONFIG_TSEC4 1
305#define CONFIG_TSEC4_NAME "eTSEC3"
306#undef CONFIG_MPC85XX_FEC
307
308#define TSEC1_PHY_ADDR 0
309#define TSEC2_PHY_ADDR 1
310#define TSEC3_PHY_ADDR 2
311#define TSEC4_PHY_ADDR 3
312
313#define TSEC1_PHYIDX 0
314#define TSEC2_PHYIDX 0
315#define TSEC3_PHYIDX 0
316#define TSEC4_PHYIDX 0
317#define TSEC1_FLAGS TSEC_GIGABIT
318#define TSEC2_FLAGS TSEC_GIGABIT
319#define TSEC3_FLAGS TSEC_GIGABIT
320#define TSEC4_FLAGS TSEC_GIGABIT
321
322
323#define CONFIG_ETHPRIME "eTSEC2"
324#define CONFIG_PHY_GIGE 1
325#endif
326
327
328
329
330#define CONFIG_ENV_IS_IN_FLASH 1
331#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
332#define CONFIG_ENV_SECT_SIZE 0x40000
333#define CONFIG_ENV_SIZE 0x2000
334
335#define CONFIG_LOADS_ECHO 1
336#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
337
338
339
340
341#define CONFIG_BOOTP_BOOTFILESIZE
342#define CONFIG_BOOTP_BOOTPATH
343#define CONFIG_BOOTP_GATEWAY
344#define CONFIG_BOOTP_HOSTNAME
345
346
347
348
349
350#include <config_cmd_default.h>
351
352#define CONFIG_CMD_PING
353#define CONFIG_CMD_I2C
354#define CONFIG_CMD_MII
355
356#if defined(CONFIG_PCI)
357 #define CONFIG_CMD_PCI
358#endif
359
360
361#undef CONFIG_WATCHDOG
362
363
364
365
366#define CONFIG_SYS_LONGHELP
367#define CONFIG_SYS_LOAD_ADDR 0x2000000
368#define CONFIG_SYS_PROMPT "=> "
369#if defined(CONFIG_CMD_KGDB)
370#define CONFIG_SYS_CBSIZE 1024
371#else
372#define CONFIG_SYS_CBSIZE 256
373#endif
374#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
375#define CONFIG_SYS_MAXARGS 16
376#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
377#define CONFIG_SYS_HZ 1000
378
379
380
381
382
383
384#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
385
386
387
388
389
390
391#define BOOTFLAG_COLD 0x01
392#define BOOTFLAG_WARM 0x02
393
394#if defined(CONFIG_CMD_KGDB)
395#define CONFIG_KGDB_BAUDRATE 230400
396#define CONFIG_KGDB_SER_INDEX 2
397#endif
398
399
400
401
402
403
404#if defined(CONFIG_TSEC_ENET)
405#define CONFIG_HAS_ETH0
406#define CONFIG_ETHADDR 00:E0:0C:00:00:FD
407#define CONFIG_HAS_ETH1
408#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
409#define CONFIG_HAS_ETH2
410#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
411#define CONFIG_HAS_ETH3
412#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
413#endif
414
415#define CONFIG_IPADDR 10.101.43.142
416
417#define CONFIG_HOSTNAME atum
418#define CONFIG_ROOTPATH /nfsroot
419#define CONFIG_BOOTFILE /tftpboot/uImage.atum
420#define CONFIG_UBOOTPATH /tftpboot/uboot.bin
421
422#define CONFIG_SERVERIP 10.101.43.10
423#define CONFIG_GATEWAYIP 10.101.45.1
424#define CONFIG_NETMASK 255.255.248.0
425
426#define CONFIG_LOADADDR 1000000
427
428#define CONFIG_BOOTDELAY 10
429#undef CONFIG_BOOTARGS
430
431#define CONFIG_BAUDRATE 115200
432
433#define CONFIG_NFSBOOTCOMMAND \
434 "setenv bootargs root=/dev/nfs rw " \
435 "nfsroot=$serverip:$rootpath " \
436 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
437 "console=$consoledev,$baudrate $othbootargs;" \
438 "tftp $loadaddr $bootfile;" \
439 "tftp $dtbaddr $dtbfile;" \
440 "bootm $loadaddr - $dtbaddr"
441
442
443#define CONFIG_RAMBOOTCOMMAND \
444 "setenv bootargs root=/dev/ram rw " \
445 "console=$consoledev,$baudrate $othbootargs;" \
446 "tftp $ramdiskaddr $ramdiskfile;" \
447 "tftp $loadaddr $bootfile;" \
448 "tftp $dtbaddr $dtbfile;" \
449 "bootm $loadaddr $ramdiskaddr $dtbaddr"
450
451#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
452
453#endif
454