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28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31
32
33
34
35
36#define CONFIG_405GP 1
37#define CONFIG_4xx 1
38#define CONFIG_CPCI405 1
39#define CONFIG_CPCI405_VER2 1
40
41#define CONFIG_BOARD_EARLY_INIT_F 1
42
43#define CONFIG_SYS_CLK_FREQ 33330000
44
45#define CONFIG_BAUDRATE 9600
46#define CONFIG_BOOTDELAY 3
47
48#undef CONFIG_BOOTARGS
49#undef CONFIG_BOOTCOMMAND
50
51#define CONFIG_PREBOOT
52
53#define CONFIG_LOADS_ECHO 1
54#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
55
56#define CONFIG_PPC4xx_EMAC
57#define CONFIG_MII 1
58#define CONFIG_PHY_ADDR 0
59#define CONFIG_LXT971_NO_SLEEP 1
60#define CONFIG_RESET_PHY_R 1
61
62#define CONFIG_NET_MULTI 1
63#undef CONFIG_HAS_ETH1
64
65#define CONFIG_RTC_M48T35A 1
66
67
68
69
70#define CONFIG_BOOTP_SUBNETMASK
71#define CONFIG_BOOTP_GATEWAY
72#define CONFIG_BOOTP_HOSTNAME
73#define CONFIG_BOOTP_BOOTPATH
74#define CONFIG_BOOTP_DNS
75#define CONFIG_BOOTP_DNS2
76#define CONFIG_BOOTP_SEND_HOSTNAME
77
78
79
80
81
82#include <config_cmd_default.h>
83
84#define CONFIG_CMD_DHCP
85#define CONFIG_CMD_PCI
86#define CONFIG_CMD_IRQ
87#define CONFIG_CMD_IDE
88#define CONFIG_CMD_FAT
89#define CONFIG_CMD_ELF
90#define CONFIG_CMD_DATE
91#define CONFIG_CMD_I2C
92#define CONFIG_CMD_MII
93#define CONFIG_CMD_PING
94#define CONFIG_CMD_BSP
95#define CONFIG_CMD_EEPROM
96
97#define CONFIG_MAC_PARTITION
98#define CONFIG_DOS_PARTITION
99
100#define CONFIG_SUPPORT_VFAT
101
102#undef CONFIG_AUTO_UPDATE
103
104#undef CONFIG_WATCHDOG
105
106#define CONFIG_SDRAM_BANK0 1
107
108
109
110
111#define CONFIG_SYS_LONGHELP
112#define CONFIG_SYS_PROMPT "=> "
113
114#undef CONFIG_SYS_HUSH_PARSER
115#ifdef CONFIG_SYS_HUSH_PARSER
116#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
117#endif
118
119#if defined(CONFIG_CMD_KGDB)
120#define CONFIG_SYS_CBSIZE 1024
121#else
122#define CONFIG_SYS_CBSIZE 256
123#endif
124#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
125#define CONFIG_SYS_MAXARGS 16
126#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
127
128#define CONFIG_SYS_DEVICE_NULLDEV 1
129
130#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
131
132#define CONFIG_AUTO_COMPLETE 1
133
134#define CONFIG_SYS_MEMTEST_START 0x0400000
135#define CONFIG_SYS_MEMTEST_END 0x0C00000
136
137#undef CONFIG_SYS_EXT_SERIAL_CLOCK
138#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59
139#define CONFIG_SYS_BASE_BAUD 691200
140
141
142#define CONFIG_SYS_BAUDRATE_TABLE \
143 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
144 57600, 115200, 230400, 460800, 921600 }
145
146#define CONFIG_SYS_LOAD_ADDR 0x100000
147#define CONFIG_SYS_EXTBDINFO 1
148
149#define CONFIG_SYS_HZ 1000
150
151#define CONFIG_LOOPW 1
152
153#define CONFIG_ZERO_BOOTDELAY_CHECK
154
155
156#define CONFIG_AUTOBOOT_KEYED 1
157#define CONFIG_AUTOBOOT_PROMPT \
158 "Autobooting in %d seconds\n", bootdelay
159#undef CONFIG_AUTOBOOT_DELAY_STR
160#undef CONFIG_AUTOBOOT_STOP_STR
161#define CONFIG_AUTOBOOT_STOP_STR2 "esdesd"
162
163#define CONFIG_VERSION_VARIABLE 1
164
165#define CONFIG_SYS_RX_ETH_BUFFER 16
166
167
168
169
170
171#define PCI_HOST_ADAPTER 0
172#define PCI_HOST_FORCE 1
173#define PCI_HOST_AUTO 2
174
175#define CONFIG_PCI
176#define CONFIG_PCI_HOST PCI_HOST_AUTO
177#define CONFIG_PCI_PNP
178
179
180#define CONFIG_PCI_SCAN_SHOW
181
182#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1
183
184#define CONFIG_PCI_BOOTDELAY 0
185
186#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE
187#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405
188#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406
189#define CONFIG_SYS_PCI_CLASSCODE 0x0b20
190#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart)
191#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1)
192#define CONFIG_SYS_PCI_PTM1PCI 0x00000000
193#define CONFIG_SYS_PCI_PTM2LA 0xffc00000
194#define CONFIG_SYS_PCI_PTM2MS 0xffc00001
195#define CONFIG_SYS_PCI_PTM2PCI 0x04000000
196
197
198
199
200
201#undef CONFIG_IDE_8xx_DIRECT
202#undef CONFIG_IDE_LED
203#define CONFIG_IDE_RESET 1
204
205#define CONFIG_SYS_IDE_MAXBUS 1
206#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1)
207
208#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
209#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
210
211#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
212#define CONFIG_SYS_ATA_REG_OFFSET 0x0000
213#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000
214
215
216
217
218
219
220#define CONFIG_SYS_SDRAM_BASE 0x00000000
221#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
222#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
223#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
224#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
225
226
227
228
229
230
231#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
232
233
234
235#define CONFIG_SYS_MAX_FLASH_BANKS 2
236#define CONFIG_SYS_MAX_FLASH_SECT 256
237
238#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
239#define CONFIG_SYS_FLASH_WRITE_TOUT 500
240
241#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
242#define CONFIG_SYS_FLASH_ADDR0 0x5555
243#define CONFIG_SYS_FLASH_ADDR1 0x2AAA
244
245
246
247
248#define CONFIG_SYS_FLASH_READ0 0x0000
249#define CONFIG_SYS_FLASH_READ1 0x0001
250#define CONFIG_SYS_FLASH_READ2 0x0002
251
252#define CONFIG_SYS_FLASH_EMPTY_INFO
253
254#if 0
255
256
257
258#define CONFIG_ENV_IS_IN_NVRAM 1
259#define CONFIG_ENV_SIZE 0x0ff8
260#define CONFIG_ENV_ADDR \
261 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))
262
263#else
264
265#define CONFIG_ENV_IS_IN_EEPROM 1
266#define CONFIG_ENV_OFFSET 0x000
267#define CONFIG_ENV_SIZE 0x800
268
269#endif
270
271#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000
272#define CONFIG_SYS_NVRAM_SIZE (32*1024)
273#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900)
274
275
276
277
278#define CONFIG_HARD_I2C
279#define CONFIG_SYS_I2C_SPEED 400000
280#define CONFIG_SYS_I2C_SLAVE 0x7F
281
282#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
283#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
284
285#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
286#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
287
288
289#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
290
291
292
293
294
295
296
297#define FLASH_BASE0_PRELIM 0xFF800000
298#define FLASH_BASE1_PRELIM 0xFFC00000
299
300
301
302
303
304
305#define CONFIG_SYS_EBC_PB0AP 0x92015480
306#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
307
308
309#define CONFIG_SYS_EBC_PB1AP 0x92015480
310#define CONFIG_SYS_EBC_PB1CR 0xFF85A000
311
312
313#define CONFIG_SYS_EBC_PB2AP 0x010053C0
314#define CONFIG_SYS_EBC_PB2CR 0xF0018000
315#define CONFIG_SYS_LED_ADDR 0xF0000380
316
317
318#define CONFIG_SYS_EBC_PB3AP 0x010053C0
319#define CONFIG_SYS_EBC_PB3CR 0xF011A000
320
321
322
323#define CONFIG_SYS_EBC_PB4AP 0x01805680
324#define CONFIG_SYS_EBC_PB4CR 0xF0218000
325
326
327#define CONFIG_SYS_EBC_PB5AP 0x04005B80
328#define CONFIG_SYS_EBC_PB5CR 0xF0318000
329
330
331#define CONFIG_SYS_EBC_PB6AP 0x010053C0
332#define CONFIG_SYS_EBC_PB6CR 0xF041A000
333#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
334
335
336
337
338
339#define CONFIG_SYS_FPGA_MODE 0x00
340#define CONFIG_SYS_FPGA_STATUS 0x02
341#define CONFIG_SYS_FPGA_TS 0x04
342#define CONFIG_SYS_FPGA_TS_LOW 0x06
343#define CONFIG_SYS_FPGA_TS_CAP0 0x10
344#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
345#define CONFIG_SYS_FPGA_TS_CAP1 0x14
346#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
347#define CONFIG_SYS_FPGA_TS_CAP2 0x18
348#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
349#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
350#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
351
352
353#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
354#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
355#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004
356#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
357#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
358#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
359
360
361#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
362#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
363#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
364#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
365#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
366
367#define CONFIG_SYS_FPGA_SPARTAN2 1
368#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024
369
370
371#define CONFIG_SYS_FPGA_PRG 0x04000000
372#define CONFIG_SYS_FPGA_CLK 0x02000000
373#define CONFIG_SYS_FPGA_DATA 0x01000000
374#define CONFIG_SYS_FPGA_INIT 0x00010000
375#define CONFIG_SYS_FPGA_DONE 0x00008000
376
377
378
379
380#define CONFIG_SYS_INIT_DCACHE_CS 7
381
382#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
383#define CONFIG_SYS_INIT_RAM_END 0x2000
384#define CONFIG_SYS_GBL_DATA_SIZE 128
385#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
386#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
387
388
389
390
391
392
393#define BOOTFLAG_COLD 0x01
394#define BOOTFLAG_WARM 0x02
395
396#endif
397