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31
32#ifndef __CONFIG_H
33#define __CONFIG_H
34
35
36#define CONFIG_MPC86xx 1
37#define CONFIG_MPC8641 1
38#define CONFIG_MPC8641HPCN 1
39#define CONFIG_NUM_CPUS 2
40#define CONFIG_LINUX_RESET_VEC 0x100
41
42
43#ifdef RUN_DIAG
44#define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE
45#endif
46
47#define CONFIG_SYS_RESET_ADDRESS 0xfff00100
48
49
50
51
52
53#define CONFIG_SYS_SCRATCH_VA 0xe0000000
54
55
56
57
58
59
60#ifndef CONFIG_RIO
61#define CONFIG_PCI 1
62#define CONFIG_PCI1 1
63#define CONFIG_PCI2 1
64#define CONFIG_FSL_PCI_INIT 1
65#define CONFIG_SYS_PCI_64BIT 1
66#endif
67#define CONFIG_FSL_LAW 1
68
69#define CONFIG_TSEC_ENET
70#define CONFIG_ENV_OVERWRITE
71
72#define CONFIG_HIGH_BATS 1
73
74#define CONFIG_ALTIVEC 1
75
76
77
78
79#define CONFIG_SYS_L2
80#define L2_INIT 0
81#define L2_ENABLE (L2CR_L2E)
82
83#ifndef CONFIG_SYS_CLK_FREQ
84#ifndef __ASSEMBLY__
85extern unsigned long get_board_sys_clk(unsigned long dummy);
86#endif
87#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
88#endif
89
90#define CONFIG_BOARD_EARLY_INIT_F 1
91
92#define CONFIG_SYS_MEMTEST_START 0x00200000
93#define CONFIG_SYS_MEMTEST_END 0x00400000
94
95
96
97
98
99
100#ifdef CONFIG_PHYS_64BIT
101#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL
102#else
103#define CONFIG_SYS_PHYS_ADDR_HIGH 0x0
104#endif
105
106
107
108
109
110#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
111#define CONFIG_SYS_CCSRBAR 0xffe00000
112#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
113
114
115#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
116#ifdef CONFIG_PHYS_64BIT
117#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf
118#define CONFIG_SYS_CCSRBAR_PHYS (CONFIG_SYS_CCSRBAR_PHYS_LOW \
119 | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32))
120#else
121#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
122#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
123#endif
124
125#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
126#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
127
128
129
130
131#define CONFIG_FSL_DDR2
132#undef CONFIG_FSL_DDR_INTERACTIVE
133#define CONFIG_SPD_EEPROM
134#define CONFIG_DDR_SPD
135
136#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
137#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
138
139#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
140#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
141#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000
142#define CONFIG_VERY_BIG_RAM
143
144#define MPC86xx_DDR_SDRAM_CLK_CNTL
145
146#define CONFIG_NUM_DDR_CONTROLLERS 2
147#define CONFIG_DIMM_SLOTS_PER_CTLR 2
148#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
149
150
151
152
153#define SPD_EEPROM_ADDRESS1 0x51
154#define SPD_EEPROM_ADDRESS2 0x52
155#define SPD_EEPROM_ADDRESS3 0x53
156#define SPD_EEPROM_ADDRESS4 0x54
157
158
159
160
161
162#define CONFIG_SYS_SDRAM_SIZE 256
163#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
164#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102
165#define CONFIG_SYS_DDR_TIMING_3 0x00000000
166#define CONFIG_SYS_DDR_TIMING_0 0x00260802
167#define CONFIG_SYS_DDR_TIMING_1 0x39357322
168#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
169#define CONFIG_SYS_DDR_MODE_1 0x00480432
170#define CONFIG_SYS_DDR_MODE_2 0x00000000
171#define CONFIG_SYS_DDR_INTERVAL 0x06090100
172#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
173#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
174#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
175#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
176#define CONFIG_SYS_DDR_CONTROL 0xe3008000
177#define CONFIG_SYS_DDR_CONTROL2 0x04400000
178
179#define CONFIG_ID_EEPROM
180#define CONFIG_SYS_I2C_EEPROM_NXID
181#define CONFIG_ID_EEPROM
182#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
183#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
184
185#define CONFIG_SYS_FLASH_BASE 0xef800000
186#define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \
187 | CONFIG_SYS_PHYS_ADDR_HIGH)
188
189#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
190
191#define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
192 | 0x00001001)
193#define CONFIG_SYS_OR0_PRELIM 0xff806ff7
194
195#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \
196 | 0x00001001)
197#define CONFIG_SYS_OR2_PRELIM 0xffffeff7
198
199#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \
200 | 0x00000801)
201#define CONFIG_SYS_OR3_PRELIM 0xffffeff7
202
203
204
205
206
207
208#define CONFIG_SYS_LBC_BASE 0xffde0000
209#define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \
210 | CONFIG_SYS_PHYS_ADDR_HIGH)
211
212#define CONFIG_FSL_PIXIS 1
213#define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000)
214#define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000)
215#define PIXIS_SIZE 0x00008000
216#define PIXIS_ID 0x0
217#define PIXIS_VER 0x1
218#define PIXIS_PVER 0x2
219#define PIXIS_RST 0x4
220#define PIXIS_AUX 0x6
221#define PIXIS_SPD 0x7
222#define PIXIS_VCTL 0x10
223#define PIXIS_VCFGEN0 0x12
224#define PIXIS_VCFGEN1 0x13
225#define PIXIS_VBOOT 0x16
226#define PIXIS_VSPEED0 0x17
227#define PIXIS_VSPEED1 0x18
228#define PIXIS_VCLKH 0x19
229#define PIXIS_VCLKL 0x1A
230#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40
231
232
233#define CF_BASE (PIXIS_BASE + PIXIS_SIZE)
234#define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE)
235
236#define CONFIG_SYS_MAX_FLASH_BANKS 1
237#define CONFIG_SYS_MAX_FLASH_SECT 128
238
239#undef CONFIG_SYS_FLASH_CHECKSUM
240#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
241#define CONFIG_SYS_FLASH_WRITE_TOUT 500
242#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
243#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000
244
245#define CONFIG_FLASH_CFI_DRIVER
246#define CONFIG_SYS_FLASH_CFI
247#define CONFIG_SYS_FLASH_EMPTY_INFO
248
249#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
250#define CONFIG_SYS_RAMBOOT
251#else
252#undef CONFIG_SYS_RAMBOOT
253#endif
254
255#if defined(CONFIG_SYS_RAMBOOT)
256#undef CONFIG_SPD_EEPROM
257#define CONFIG_SYS_SDRAM_SIZE 256
258#endif
259
260#undef CONFIG_CLOCKS_IN_MHZ
261
262#define CONFIG_SYS_INIT_RAM_LOCK 1
263#ifndef CONFIG_SYS_INIT_RAM_LOCK
264#define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000
265#else
266#define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000
267#endif
268#define CONFIG_SYS_INIT_RAM_END 0x4000
269
270#define CONFIG_SYS_GBL_DATA_SIZE 128
271#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
272#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
273
274#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
275#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
276
277
278#define CONFIG_CONS_INDEX 1
279#undef CONFIG_SERIAL_SOFTWARE_FIFO
280#define CONFIG_SYS_NS16550
281#define CONFIG_SYS_NS16550_SERIAL
282#define CONFIG_SYS_NS16550_REG_SIZE 1
283#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
284
285#define CONFIG_SYS_BAUDRATE_TABLE \
286 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
287
288#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
289#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
290
291
292#define CONFIG_SYS_HUSH_PARSER
293#ifdef CONFIG_SYS_HUSH_PARSER
294#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
295#endif
296
297
298
299
300#define CONFIG_OF_LIBFDT 1
301#define CONFIG_OF_BOARD_SETUP 1
302#define CONFIG_OF_STDOUT_VIA_ALIAS 1
303
304
305#define CONFIG_SYS_64BIT_VSPRINTF 1
306#define CONFIG_SYS_64BIT_STRTOUL 1
307
308
309
310
311#define CONFIG_FSL_I2C
312#define CONFIG_HARD_I2C
313#undef CONFIG_SOFT_I2C
314#define CONFIG_SYS_I2C_SPEED 400000
315#define CONFIG_SYS_I2C_SLAVE 0x7F
316#define CONFIG_SYS_I2C_NOPROBES {0x69}
317#define CONFIG_SYS_I2C_OFFSET 0x3100
318
319
320
321
322#define CONFIG_SYS_RIO_MEM_BASE 0x80000000
323#ifdef CONFIG_PHYS_64BIT
324#define CONFIG_SYS_RIO_MEM_PHYS 0x0000000c00000000ULL
325#else
326#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
327#endif
328#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000
329
330
331
332
333
334#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
335#ifdef CONFIG_PHYS_64BIT
336#define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL
337#else
338#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
339#endif
340#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
341#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
342#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
343#define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \
344 | CONFIG_SYS_PHYS_ADDR_HIGH)
345#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000
346
347
348#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);})
349#define _IO_BASE 0x00000000
350
351#define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MEM_BASE \
352 + CONFIG_SYS_PCI1_MEM_SIZE)
353#define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \
354 + CONFIG_SYS_PCI1_MEM_SIZE)
355#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000
356#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
357#define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \
358 + CONFIG_SYS_PCI1_IO_SIZE)
359#define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \
360 + CONFIG_SYS_PCI1_IO_SIZE)
361#define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE
362
363#if defined(CONFIG_PCI)
364
365#define CONFIG_PCI_SCAN_SHOW
366
367#undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE
368
369#define CONFIG_NET_MULTI
370#define CONFIG_PCI_PNP
371
372#define CONFIG_RTL8139
373
374#undef CONFIG_EEPRO100
375#undef CONFIG_TULIP
376
377
378
379
380#define CONFIG_PCI_OHCI 1
381#define CONFIG_USB_OHCI_NEW 1
382#define CONFIG_USB_KEYBOARD 1
383#define CONFIG_SYS_DEVICE_DEREGISTER
384#define CONFIG_SYS_USB_EVENT_POLL 1
385#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
386#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
387#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
388
389
390#define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_VIRT
391
392
393
394
395
396#define CONFIG_VIDEO
397
398#if defined(CONFIG_VIDEO)
399#define CONFIG_BIOSEMU
400#define CONFIG_CFB_CONSOLE
401#define CONFIG_VIDEO_SW_CURSOR
402#define CONFIG_VGA_AS_SINGLE_DEVICE
403#define CONFIG_ATI_RADEON_FB
404#define CONFIG_VIDEO_LOGO
405
406#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT
407#endif
408
409#undef CONFIG_PCI_SCAN_SHOW
410
411#define CONFIG_DOS_PARTITION
412#define CONFIG_SCSI_AHCI
413
414#ifdef CONFIG_SCSI_AHCI
415#define CONFIG_SATA_ULI5288
416#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
417#define CONFIG_SYS_SCSI_MAX_LUN 1
418#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
419#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
420#endif
421
422#define CONFIG_MPC86XX_PCI2
423
424#endif
425
426#if defined(CONFIG_TSEC_ENET)
427
428#ifndef CONFIG_NET_MULTI
429#define CONFIG_NET_MULTI 1
430#endif
431
432#define CONFIG_MII 1
433
434#define CONFIG_TSEC1 1
435#define CONFIG_TSEC1_NAME "eTSEC1"
436#define CONFIG_TSEC2 1
437#define CONFIG_TSEC2_NAME "eTSEC2"
438#define CONFIG_TSEC3 1
439#define CONFIG_TSEC3_NAME "eTSEC3"
440#define CONFIG_TSEC4 1
441#define CONFIG_TSEC4_NAME "eTSEC4"
442
443#define TSEC1_PHY_ADDR 0
444#define TSEC2_PHY_ADDR 1
445#define TSEC3_PHY_ADDR 2
446#define TSEC4_PHY_ADDR 3
447#define TSEC1_PHYIDX 0
448#define TSEC2_PHYIDX 0
449#define TSEC3_PHYIDX 0
450#define TSEC4_PHYIDX 0
451#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
452#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
453#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
454#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
455
456#define CONFIG_ETHPRIME "eTSEC1"
457
458#endif
459
460
461#ifdef CONFIG_PHYS_64BIT
462#define BAT_PHYS_ADDR(x) ((unsigned long) \
463 ((x & 0x00000000ffffffffULL) | \
464 ((x & 0x0000000e00000000ULL) >> 24) | \
465 ((x & 0x0000000100000000ULL) >> 30)))
466#else
467#define BAT_PHYS_ADDR(x) (x)
468#endif
469
470
471
472#define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8)
473#define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2)
474
475
476
477
478#define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE)
479#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP)
480#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE )
481#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U
482
483
484
485
486#define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
487 | BATL_PP_RW | BATL_CACHEINHIBIT | \
488 BATL_GUARDEDSTORAGE)
489#define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \
490 | BATU_VS | BATU_VP)
491#define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \
492 | BATL_PP_RW | BATL_MEMCOHERENCE)
493#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
494
495
496
497
498
499
500#ifdef CONFIG_PCI
501#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
502 | BATL_PP_RW | BATL_CACHEINHIBIT \
503 | BATL_GUARDEDSTORAGE)
504#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_1G \
505 | BATU_VS | BATU_VP)
506#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \
507 | BATL_PP_RW | BATL_CACHEINHIBIT)
508#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
509#else
510#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
511 | BATL_PP_RW | BATL_CACHEINHIBIT | \
512 BATL_GUARDEDSTORAGE)
513#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \
514 | BATU_VS | BATU_VP)
515#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \
516 | BATL_PP_RW | BATL_CACHEINHIBIT)
517
518#define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \
519 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
520#define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP)
521#define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
522#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
523#endif
524
525
526
527
528
529
530#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \
531 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
532 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
533 | BATL_PP_RW | BATL_CACHEINHIBIT \
534 | BATL_GUARDEDSTORAGE)
535#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \
536 | BATU_VP)
537#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \
538 | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
539 | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \
540 | BATL_PP_RW | BATL_CACHEINHIBIT)
541#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
542
543#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
544#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
545 | BATL_PP_RW | BATL_CACHEINHIBIT \
546 | BATL_GUARDEDSTORAGE)
547#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
548 | BATU_BL_1M | BATU_VS | BATU_VP)
549#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
550 | BATL_PP_RW | BATL_CACHEINHIBIT)
551#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
552#endif
553
554
555
556
557#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
558 | BATL_PP_RW | BATL_CACHEINHIBIT \
559 | BATL_GUARDEDSTORAGE)
560#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \
561 | BATU_VS | BATU_VP)
562#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \
563 | BATL_PP_RW | BATL_CACHEINHIBIT)
564#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
565
566
567
568
569#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
570#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
571#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
572#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
573
574
575
576
577#define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
578 | BATL_PP_RW | BATL_CACHEINHIBIT \
579 | BATL_GUARDEDSTORAGE)
580#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \
581 | BATU_VP)
582#define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
583 | BATL_PP_RW | BATL_MEMCOHERENCE)
584#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
585
586
587#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
588 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
589#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
590#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
591 | BATL_MEMCOHERENCE)
592#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
593
594
595
596
597#define CONFIG_SYS_DBAT7L 0x00000000
598#define CONFIG_SYS_DBAT7U 0x00000000
599#define CONFIG_SYS_IBAT7L 0x00000000
600#define CONFIG_SYS_IBAT7U 0x00000000
601
602
603
604
605#ifndef CONFIG_SYS_RAMBOOT
606 #define CONFIG_ENV_IS_IN_FLASH 1
607 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
608 #define CONFIG_ENV_SECT_SIZE 0x10000
609#else
610 #define CONFIG_ENV_IS_NOWHERE 1
611 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
612#endif
613#define CONFIG_ENV_SIZE 0x2000
614
615#define CONFIG_LOADS_ECHO 1
616#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
617
618
619
620
621
622#define CONFIG_BOOTP_BOOTFILESIZE
623#define CONFIG_BOOTP_BOOTPATH
624#define CONFIG_BOOTP_GATEWAY
625#define CONFIG_BOOTP_HOSTNAME
626
627
628
629
630
631#include <config_cmd_default.h>
632
633#define CONFIG_CMD_PING
634#define CONFIG_CMD_I2C
635#define CONFIG_CMD_REGINFO
636
637#if defined(CONFIG_SYS_RAMBOOT)
638 #undef CONFIG_CMD_ENV
639#endif
640
641#if defined(CONFIG_PCI)
642 #define CONFIG_CMD_PCI
643 #define CONFIG_CMD_SCSI
644 #define CONFIG_CMD_EXT2
645 #define CONFIG_CMD_USB
646#endif
647
648
649#undef CONFIG_WATCHDOG
650
651
652
653
654#define CONFIG_SYS_LONGHELP
655#define CONFIG_CMDLINE_EDITING
656#define CONFIG_SYS_LOAD_ADDR 0x2000000
657#define CONFIG_SYS_PROMPT "=> "
658
659#if defined(CONFIG_CMD_KGDB)
660 #define CONFIG_SYS_CBSIZE 1024
661#else
662 #define CONFIG_SYS_CBSIZE 256
663#endif
664
665#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
666#define CONFIG_SYS_MAXARGS 16
667#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
668#define CONFIG_SYS_HZ 1000
669
670
671
672
673
674
675#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
676
677
678
679
680
681
682#define BOOTFLAG_COLD 0x01
683#define BOOTFLAG_WARM 0x02
684
685#if defined(CONFIG_CMD_KGDB)
686 #define CONFIG_KGDB_BAUDRATE 230400
687 #define CONFIG_KGDB_SER_INDEX 2
688#endif
689
690
691
692
693
694
695#if defined(CONFIG_TSEC_ENET)
696#define CONFIG_ETHADDR 00:E0:0C:00:00:01
697#define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
698#define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
699#define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
700#endif
701
702#define CONFIG_HAS_ETH0 1
703#define CONFIG_HAS_ETH1 1
704#define CONFIG_HAS_ETH2 1
705#define CONFIG_HAS_ETH3 1
706
707#define CONFIG_IPADDR 192.168.1.100
708
709#define CONFIG_HOSTNAME unknown
710#define CONFIG_ROOTPATH /opt/nfsroot
711#define CONFIG_BOOTFILE uImage
712#define CONFIG_UBOOTPATH u-boot.bin
713
714#define CONFIG_SERVERIP 192.168.1.1
715#define CONFIG_GATEWAYIP 192.168.1.1
716#define CONFIG_NETMASK 255.255.255.0
717
718
719#define CONFIG_LOADADDR 1000000
720
721#define CONFIG_BOOTDELAY 10
722#undef CONFIG_BOOTARGS
723
724#define CONFIG_BAUDRATE 115200
725
726#define CONFIG_EXTRA_ENV_SETTINGS \
727 "netdev=eth0\0" \
728 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
729 "tftpflash=tftpboot $loadaddr $uboot; " \
730 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
731 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
732 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
733 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
734 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
735 "consoledev=ttyS0\0" \
736 "ramdiskaddr=2000000\0" \
737 "ramdiskfile=your.ramdisk.u-boot\0" \
738 "fdtaddr=c00000\0" \
739 "fdtfile=mpc8641_hpcn.dtb\0" \
740 "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \
741 "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \
742 "maxcpus=2"
743
744
745#define CONFIG_NFSBOOTCOMMAND \
746 "setenv bootargs root=/dev/nfs rw " \
747 "nfsroot=$serverip:$rootpath " \
748 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
749 "console=$consoledev,$baudrate $othbootargs;" \
750 "tftp $loadaddr $bootfile;" \
751 "tftp $fdtaddr $fdtfile;" \
752 "bootm $loadaddr - $fdtaddr"
753
754#define CONFIG_RAMBOOTCOMMAND \
755 "setenv bootargs root=/dev/ram rw " \
756 "console=$consoledev,$baudrate $othbootargs;" \
757 "tftp $ramdiskaddr $ramdiskfile;" \
758 "tftp $loadaddr $bootfile;" \
759 "tftp $fdtaddr $fdtfile;" \
760 "bootm $loadaddr $ramdiskaddr $fdtaddr"
761
762#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
763
764#endif
765