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29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32#if !defined(CONFIG_NETPHONE_VERSION) || CONFIG_NETPHONE_VERSION > 2
33#error Unsupported CONFIG_NETPHONE version
34#endif
35
36
37
38
39
40
41#define CONFIG_MPC870 1
42#define CONFIG_NETPHONE 1
43
44#define CONFIG_8xx_CONS_SMC1 1
45#undef CONFIG_8xx_CONS_SMC2
46#undef CONFIG_8xx_CONS_NONE
47
48#define CONFIG_BAUDRATE 115200
49
50
51#define CONFIG_XIN 50000000
52
53#define MPC8XX_HZ 66666666
54
55#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
56
57#if 0
58#define CONFIG_BOOTDELAY -1
59#else
60#define CONFIG_BOOTDELAY 5
61#endif
62
63#undef CONFIG_CLOCKS_IN_MHZ
64
65#define CONFIG_PREBOOT "echo;"
66
67#undef CONFIG_BOOTARGS
68#define CONFIG_BOOTCOMMAND \
69 "tftpboot; " \
70 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
71 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
72 "bootm"
73
74#define CONFIG_AUTOSCRIPT
75#define CONFIG_LOADS_ECHO 0
76#undef CONFIG_SYS_LOADS_BAUD_CHANGE
77
78#undef CONFIG_WATCHDOG
79
80#undef CONFIG_CAN_DRIVER
81
82#define CONFIG_STATUS_LED 1
83#define CONFIG_BOARD_SPECIFIC_LED
84
85
86
87
88#define CONFIG_BOOTP_SUBNETMASK
89#define CONFIG_BOOTP_GATEWAY
90#define CONFIG_BOOTP_HOSTNAME
91#define CONFIG_BOOTP_BOOTPATH
92#define CONFIG_BOOTP_BOOTFILESIZE
93#define CONFIG_BOOTP_NISDOMAIN
94
95#undef CONFIG_MAC_PARTITION
96#undef CONFIG_DOS_PARTITION
97
98#define CONFIG_RTC_MPC8xx
99
100#define CONFIG_NET_MULTI 1
101#define FEC_ENET 1
102#undef CONFIG_SYS_DISCOVER_PHY
103#define CONFIG_MII 1
104#define CONFIG_MII_INIT 1
105#define CONFIG_RMII 1
106
107#define CONFIG_ETHER_ON_FEC1 1
108#define CONFIG_FEC1_PHY 8
109#define CONFIG_FEC1_PHY_NORXERR 1
110
111#define CONFIG_ETHER_ON_FEC2 1
112#define CONFIG_FEC2_PHY 4
113#define CONFIG_FEC2_PHY_NORXERR 1
114
115#define CONFIG_ENV_OVERWRITE 1
116
117
118
119
120
121#include <config_cmd_default.h>
122
123#define CONFIG_CMD_NAND
124#define CONFIG_CMD_DHCP
125#define CONFIG_CMD_PING
126#define CONFIG_CMD_MII
127#define CONFIG_CMD_CDP
128
129
130#define CONFIG_BOARD_EARLY_INIT_F 1
131#define CONFIG_MISC_INIT_R
132
133
134
135
136#define CONFIG_SYS_LONGHELP
137#define CONFIG_SYS_PROMPT "=> "
138
139#define CONFIG_SYS_HUSH_PARSER 1
140#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
141
142#if defined(CONFIG_CMD_KGDB)
143#define CONFIG_SYS_CBSIZE 1024
144#else
145#define CONFIG_SYS_CBSIZE 256
146#endif
147#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
148#define CONFIG_SYS_MAXARGS 16
149#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
150
151#define CONFIG_SYS_MEMTEST_START 0x0300000
152#define CONFIG_SYS_MEMTEST_END 0x0700000
153
154#define CONFIG_SYS_LOAD_ADDR 0x100000
155
156#define CONFIG_SYS_HZ 1000
157
158#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
159
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162
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165
166
167
168#define CONFIG_SYS_IMMR 0xFF000000
169
170
171
172
173#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
174#define CONFIG_SYS_INIT_RAM_END 0x3000
175#define CONFIG_SYS_GBL_DATA_SIZE 64
176#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
177#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
178
179
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182
183
184#define CONFIG_SYS_SDRAM_BASE 0x00000000
185#define CONFIG_SYS_FLASH_BASE 0x40000000
186#if defined(DEBUG)
187#define CONFIG_SYS_MONITOR_LEN (256 << 10)
188#else
189#define CONFIG_SYS_MONITOR_LEN (192 << 10)
190#endif
191#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
192#define CONFIG_SYS_MALLOC_LEN (128 << 10)
193#if CONFIG_NETPHONE_VERSION == 2
194#define CONFIG_SYS_FLASH_BASE4 0x40080000
195#endif
196
197#define CONFIG_SYS_RESET_ADDRESS 0x80000000
198
199
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202
203
204#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
205
206
207
208
209#if CONFIG_NETPHONE_VERSION == 1
210#define CONFIG_SYS_MAX_FLASH_BANKS 1
211#elif CONFIG_NETPHONE_VERSION == 2
212#define CONFIG_SYS_MAX_FLASH_BANKS 2
213#endif
214#define CONFIG_SYS_MAX_FLASH_SECT 8
215
216#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
217#define CONFIG_SYS_FLASH_WRITE_TOUT 500
218
219#define CONFIG_ENV_IS_IN_FLASH 1
220#define CONFIG_ENV_SECT_SIZE 0x10000
221
222#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
223#define CONFIG_ENV_OFFSET 0
224#define CONFIG_ENV_SIZE 0x4000
225
226#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
227#define CONFIG_ENV_OFFSET_REDUND 0
228#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
229
230
231
232
233#define CONFIG_SYS_CACHELINE_SIZE 16
234#if defined(CONFIG_CMD_KGDB)
235#define CONFIG_SYS_CACHELINE_SHIFT 4
236#endif
237
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243
244#if defined(CONFIG_WATCHDOG)
245#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
246 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
247#else
248#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
249#endif
250
251
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253
254
255
256#ifndef CONFIG_CAN_DRIVER
257#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
258#else
259#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
260#endif
261
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266
267#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
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272
273#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
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279
280#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
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289
290#if CONFIG_XIN == 10000000
291
292#if MPC8XX_HZ == 120000000
293#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
294 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
295 PLPRCR_TEXPS)
296#elif MPC8XX_HZ == 100000000
297#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
298 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
299 PLPRCR_TEXPS)
300#elif MPC8XX_HZ == 50000000
301#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
302 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
303 PLPRCR_TEXPS)
304#elif MPC8XX_HZ == 25000000
305#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
306 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
307 PLPRCR_TEXPS)
308#elif MPC8XX_HZ == 40000000
309#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
310 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
311 PLPRCR_TEXPS)
312#elif MPC8XX_HZ == 75000000
313#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
314 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
315 PLPRCR_TEXPS)
316#else
317#error unsupported CPU freq for XIN = 10MHz
318#endif
319
320#elif CONFIG_XIN == 50000000
321
322#if MPC8XX_HZ == 120000000
323#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
324 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
325 PLPRCR_TEXPS)
326#elif MPC8XX_HZ == 100000000
327#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
328 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
329 PLPRCR_TEXPS)
330#elif MPC8XX_HZ == 66666666
331#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
332 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
333 PLPRCR_TEXPS)
334#else
335#error unsupported CPU freq for XIN = 50MHz
336#endif
337
338#else
339
340#error unsupported XIN freq
341#endif
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353
354#define SCCR_MASK SCCR_EBDF11
355#if MPC8XX_HZ > 66666666
356#define CONFIG_SYS_SCCR ( SCCR_CRQEN | \
357 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
358 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
359 SCCR_DFALCD00 | SCCR_EBDF01)
360#else
361#define CONFIG_SYS_SCCR ( SCCR_CRQEN | \
362 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
363 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
364 SCCR_DFALCD00)
365#endif
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372
373#define CONFIG_SYS_DER 0
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380
381#define FLASH_BASE0_PRELIM 0x40000000
382
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386
387#define CONFIG_SYS_REMAP_OR_AM 0x80000000
388#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000
389
390
391#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
392
393#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
394#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
395#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
396
397#if CONFIG_NETPHONE_VERSION == 2
398
399#define FLASH_BASE4_PRELIM 0x40080000
400
401#define CONFIG_SYS_OR4_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
402#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
403#define CONFIG_SYS_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
404
405#endif
406
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409
410
411#define SDRAM_BASE3_PRELIM 0x00000000
412#define SDRAM_MAX_SIZE (256 << 20)
413
414
415#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
416
417#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
418#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
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451#define CONFIG_SYS_MAMR_PTA 234
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461#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16
462#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32
463
464
465#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8
466#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16
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472
473#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
474 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
475 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
476
477
478#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
479 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
480 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
481
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485
486
487#define BOOTFLAG_COLD 0x01
488#define BOOTFLAG_WARM 0x02
489
490#define CONFIG_LAST_STAGE_INIT
491
492
493
494#define DSP_SIZE 0x00010000
495#define NAND_SIZE 0x00010000
496
497#define DSP_BASE 0xF1000000
498#define NAND_BASE 0xF1010000
499
500
501
502
503#define CONFIG_NAND_LEGACY
504#define CONFIG_SYS_NAND_BASE NAND_BASE
505#define CONFIG_MTD_NAND_ECC_JFFS2
506#define CONFIG_MTD_NAND_VERIFY_WRITE
507#define CONFIG_MTD_NAND_UNSAFE
508
509#define CONFIG_SYS_MAX_NAND_DEVICE 1
510
511#define SECTORSIZE 512
512#define ADDR_COLUMN 1
513#define ADDR_PAGE 2
514#define ADDR_COLUMN_PAGE 3
515#define NAND_ChipID_UNKNOWN 0x00
516#define NAND_MAX_FLOORS 1
517#define NAND_MAX_CHIPS 1
518
519
520#define NAND_DISABLE_CE(nand) \
521 do { \
522 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 20)); \
523 } while(0)
524
525#define NAND_ENABLE_CE(nand) \
526 do { \
527 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 20)); \
528 } while(0)
529
530#define NAND_CTL_CLRALE(nandptr) \
531 do { \
532 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 17)); \
533 } while(0)
534
535#define NAND_CTL_SETALE(nandptr) \
536 do { \
537 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 17)); \
538 } while(0)
539
540#define NAND_CTL_CLRCLE(nandptr) \
541 do { \
542 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) &= ~(1 << (31 - 18)); \
543 } while(0)
544
545#define NAND_CTL_SETCLE(nandptr) \
546 do { \
547 (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat) |= (1 << (31 - 18)); \
548 } while(0)
549
550#if CONFIG_NETPHONE_VERSION == 1
551#define NAND_WAIT_READY(nand) \
552 do { \
553 int _tries = 0; \
554 while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & (1 << (31 - 31))) == 0) \
555 if (++_tries > 100000) \
556 break; \
557 } while (0)
558#elif CONFIG_NETPHONE_VERSION == 2
559#define NAND_WAIT_READY(nand) \
560 do { \
561 int _tries = 0; \
562 while ((((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat & (1 << (15 - 15))) == 0) \
563 if (++_tries > 100000) \
564 break; \
565 } while (0)
566#endif
567
568#define WRITE_NAND_COMMAND(d, adr) \
569 do { \
570 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
571 } while(0)
572
573#define WRITE_NAND_ADDRESS(d, adr) \
574 do { \
575 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
576 } while(0)
577
578#define WRITE_NAND(d, adr) \
579 do { \
580 *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
581 } while(0)
582
583#define READ_NAND(adr) \
584 ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
585
586
587
588#define CONFIG_SYS_DIRECT_FLASH_TFTP
589#define CONFIG_SYS_DIRECT_NAND_TFTP
590
591
592
593#if CONFIG_NETPHONE_VERSION == 1
594#define STATUS_LED_BIT 0x00000008
595#elif CONFIG_NETPHONE_VERSION == 2
596#define STATUS_LED_BIT 0x00000080
597#endif
598
599#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
600#define STATUS_LED_STATE STATUS_LED_BLINKING
601
602#define STATUS_LED_ACTIVE 0
603#define STATUS_LED_BOOT 0
604
605#ifndef __ASSEMBLY__
606
607
608
609
610typedef unsigned int led_id_t;
611
612#define __led_toggle(_msk) \
613 do { \
614 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \
615 } while(0)
616
617#define __led_set(_msk, _st) \
618 do { \
619 if ((_st)) \
620 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \
621 else \
622 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
623 } while(0)
624
625#define __led_init(msk, st) __led_set(msk, st)
626
627#endif
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756
757#define CONFIG_SED156X 1
758#define CONFIG_SED156X_PG12864Q 1
759
760
761
762#define SED156X_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
763#define SED156X_SPI_RXD_MASK 0x00000008
764
765#define SED156X_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
766#define SED156X_SPI_TXD_MASK 0x00000004
767
768#define SED156X_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
769#define SED156X_SPI_CLK_MASK 0x00000002
770
771#define SED156X_CS_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
772#define SED156X_CS_MASK 0x00000010
773
774#define SED156X_A0_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
775#define SED156X_A0_MASK 0x0020
776
777
778
779#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
780#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
781#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
782
783
784
785
786#undef CONFIG_WATCHDOG
787#define CONFIG_HW_WATCHDOG
788#define CONFIG_SHOW_ACTIVITY
789
790
791
792
793
794#define PHONE_CONSOLE_POLL_HZ (CONFIG_SYS_HZ/200)
795
796
797
798#define CONFIG_CDP_DEVICE_ID 20
799#define CONFIG_CDP_DEVICE_ID_PREFIX "NP"
800#define CONFIG_CDP_PORT_ID "eth%d"
801#define CONFIG_CDP_CAPABILITIES 0x00000010
802#define CONFIG_CDP_VERSION "u-boot" " " U_BOOT_DATE " " U_BOOT_TIME
803#define CONFIG_CDP_PLATFORM "Intracom NetPhone"
804#define CONFIG_CDP_TRIGGER 0x20020001
805#define CONFIG_CDP_POWER_CONSUMPTION 4300
806#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01
807
808
809
810#define CONFIG_AUTO_COMPLETE 1
811
812
813
814#define CONFIG_CRC32_VERIFY 1
815
816
817
818#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
819
820
821#endif
822