1/* 2 * (C) Copyright 2001 3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 4 * 5 * (C) Copyright 2001 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26 27/* 28 * board/config.h - configuration options, board specific 29 */ 30 31#ifndef __CONFIG_H 32#define __CONFIG_H 33 34/* 35 * High Level Configuration Options 36 * (easy to change) 37 */ 38 39#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ 40#define CONFIG_NX823 1 /* ...on a NEXUS 823 module */ 41 42/*#define CONFIG_VIDEO 1 */ 43 44#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED 45#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 46#undef CONFIG_8xx_CONS_SMC2 47#undef CONFIG_8xx_CONS_NONE 48#define CONFIG_BAUDRATE 57600 /* console baudrate = 115kbps */ 49#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ 50#define CONFIG_BOOTARGS "ramdisk_size=8000 "\ 51 "root=/dev/nfs rw nfsroot=10.77.77.250:/ppcroot "\ 52 "nfsaddrs=10.77.77.20:10.77.77.250" 53#define CONFIG_BOOTCOMMAND "bootm 400e0000" 54 55#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 56#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 57#undef CONFIG_WATCHDOG /* watchdog disabled, for now */ 58#define CONFIG_AUTOSCRIPT 59 60/* 61 * BOOTP options 62 */ 63#define CONFIG_BOOTP_SUBNETMASK 64#define CONFIG_BOOTP_GATEWAY 65#define CONFIG_BOOTP_HOSTNAME 66#define CONFIG_BOOTP_BOOTPATH 67#define CONFIG_BOOTP_BOOTFILESIZE 68 69 70/* 71 * Command line configuration. 72 */ 73#include <config_cmd_default.h> 74 75#define CONFIG_CMD_AUTOSCRIPT 76 77 78/* call various generic functions */ 79#define CONFIG_MISC_INIT_R 80 81/* 82 * Miscellaneous configurable options 83 */ 84#define CONFIG_SYS_LONGHELP /* undef to save memory */ 85#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 86#if defined(CONFIG_CMD_KGDB) 87#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 88#else 89#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 90#endif 91#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 92#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 93#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 94 95#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 96#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 97 98#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 99 100#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 101 102#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 103 104/* 105 * Low Level Configuration Settings 106 * (address mappings, register initial values, etc.) 107 * You should know what you are doing if you make changes here. 108 */ 109/*----------------------------------------------------------------------- 110 * Internal Memory Mapped Register 111 */ 112#define CONFIG_SYS_IMMR 0xFFF00000 113 114/*----------------------------------------------------------------------- 115 * Definitions for initial stack pointer and data area (in DPRAM) 116 */ 117#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 118#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 119#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ 120#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 121#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 122 123/*----------------------------------------------------------------------- 124 * Start addresses for the final memory configuration 125 * (Set up by the startup code) 126 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 127 */ 128#define CONFIG_SYS_SDRAM_BASE 0x00000000 129#define CONFIG_SYS_FLASH_BASE 0x40000000 130#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ 131#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 132#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 133 134/* 135 * For booting Linux, the board info and command line data 136 * have to be in the first 8 MB of memory, since this is 137 * the maximum mapped by the Linux kernel during initialization. 138 */ 139#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 140 141/*----------------------------------------------------------------------- 142 * FLASH organization 143 */ 144#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 145#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ 146 147#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 148#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 149 150#define CONFIG_ENV_IS_IN_FLASH 1 151#define xEMBED 152#ifdef EMBED 153#define CONFIG_ENV_SIZE 0x200 /* FIXME How big when embedded?? */ 154#define CONFIG_ENV_ADDR CONFIG_SYS_MONITOR_BASE 155#else 156#define CONFIG_ENV_ADDR 0x40020000 /* absolute address for now */ 157#define CONFIG_ENV_SIZE 0x20000 /* 8K ouch, this may later be */ 158#endif 159 160#define CONFIG_SYS_FLASH_SN_BASE 0x4001fff0 /* programmer automagically puts */ 161#define CONFIG_SYS_FLASH_SN_SECTOR 0x40000000 /* a serial number here */ 162#define CONFIG_SYS_FLASH_SN_BYTES 8 163 164/*----------------------------------------------------------------------- 165 * Cache Configuration 166 */ 167#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 168#if defined(CONFIG_CMD_KGDB) 169#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 170#endif 171 172/*----------------------------------------------------------------------- 173 * SYPCR - System Protection Control 11-9 174 * SYPCR can only be written once after reset! 175 *----------------------------------------------------------------------- 176 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 177 */ 178#if defined(CONFIG_WATCHDOG) 179#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 180 SYPCR_SWE | SYPCR_SWP) 181#else 182#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 183#endif 184 185/*----------------------------------------------------------------------- 186 * SIUMCR - SIU Module Configuration 12-30 187 *----------------------------------------------------------------------- 188 * PCMCIA config., multi-function pin tri-state 189 */ 190#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00) 191 192/*----------------------------------------------------------------------- 193 * TBSCR - Time Base Status and Control 12-16 194 *----------------------------------------------------------------------- 195 * Clear Reference Interrupt Status, Timebase freezing enabled 196 */ 197#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 198 199/*----------------------------------------------------------------------- 200 * RTCSC - Real-Time Clock Status and Control Register 12-18 201 *----------------------------------------------------------------------- 202 */ 203#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 204 205/*----------------------------------------------------------------------- 206 * PISCR - Periodic Interrupt Status and Control 12-23 207 *----------------------------------------------------------------------- 208 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 209 */ 210#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 211 212/*----------------------------------------------------------------------- 213 * PLPRCR - PLL, Low-Power, and Reset Control Register 5-7 214 *----------------------------------------------------------------------- 215 * Reset PLL lock status sticky bit, timer expired status bit and timer 216 * interrupt status bit 217 */ 218#define MPC8XX_SPEED 66666666L 219#define MPC8XX_XIN 32768 /* 32.768 kHz crystal */ 220#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN) 221#define CONFIG_SYS_PLPRCR_MF ((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) 222#define CONFIG_SYS_PLPRCR (CONFIG_SYS_PLPRCR_MF | PLPRCR_TEXPS | PLPRCR_TMIST) 223 224/*----------------------------------------------------------------------- 225 * SCCR - System Clock and reset Control Register 5-3 226 *----------------------------------------------------------------------- 227 * Set clock output, timebase and RTC source and divider, 228 * power management and some other internal clocks 229 */ 230#define SCCR_MASK SCCR_EBDF11 231#define CONFIG_SYS_SCCR (SCCR_TBS | \ 232 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 233 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 234 SCCR_DFALCD00) 235 236/*----------------------------------------------------------------------- 237 * 238 *----------------------------------------------------------------------- 239 * 240 */ 241#define CONFIG_SYS_DER 0 242 243/* 244 * Init Memory Controller: 245 * 246 * BR0 and OR0 (FLASH) 247 */ 248 249#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 250 251/* used to re-map FLASH both when starting from SRAM or FLASH: 252 * restrict access enough to keep SRAM working (if any) 253 * but not too much to meddle with FLASH accesses 254 */ 255#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 256#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 257 258/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0 */ 259#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ 260 OR_SCY_8_CLK ) 261 262#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 263#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 264#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) 265 266/* 267 * BR1/2 and OR1/2 (SDRAM) 268 */ 269#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ 270#define SDRAM_BASE2_PRELIM 0x20000000 /* SDRAM bank #1 */ 271#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 272 273/* SDRAM timing: Multiplexed addresses, drive GPL5 high on first cycle */ 274#define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS | OR_CSNT_SAM) 275 276#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 277#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 278#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR1_PRELIM 279#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 280 281/* IO and memory mapped stuff */ 282#define NX823_IO_OR_AM 0xFFFF0000 /* mask for IO addresses */ 283#define NX823_IO_BASE 0xFF000000 /* start of IO */ 284#define GPOUT_OFFSET (3<<16) 285#define QUART_OFFSET (4<<16) 286#define VIDAC_OFFSET (5<<16) 287#define CPLD_OFFSET (6<<16) 288#define SED1386_OFFSET (7<<16) 289 290/* 291 * BR3 and OR3 (general purpose output latches) 292 */ 293#define GPOUT_BASE (NX823_IO_BASE + GPOUT_OFFSET) 294#define GPOUT_TIMING (OR_CSNT_SAM | OR_TRLX | OR_BI) 295#define CONFIG_SYS_OR3_PRELIM (NX823_IO_OR_AM | GPOUT_TIMING) 296#define CONFIG_SYS_BR3_PRELIM (GPOUT_BASE | BR_V) 297 298/* 299 * BR4 and OR4 (QUART) 300 */ 301#define QUART_BASE (NX823_IO_BASE + QUART_OFFSET) 302#define QUART_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_TRLX) 303#define CONFIG_SYS_OR4_PRELIM (NX823_IO_OR_AM | QUART_TIMING | OR_BI) 304#define CONFIG_SYS_BR4_PRELIM (QUART_BASE | BR_PS_8 | BR_V) 305 306/* 307 * BR5 and OR5 (Video DAC) 308 */ 309#define VIDAC_BASE (NX823_IO_BASE + VIDAC_OFFSET) 310#define VIDAC_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR) 311#define CONFIG_SYS_OR5_PRELIM (NX823_IO_OR_AM | VIDAC_TIMING | OR_BI) 312#define CONFIG_SYS_BR5_PRELIM (VIDAC_BASE | BR_PS_8 | BR_V) 313 314/* 315 * BR6 and OR6 (CPLD) 316 * FIXME timing not verified for CPLD 317 */ 318#define CPLD_BASE (NX823_IO_BASE + CPLD_OFFSET) 319#define CPLD_TIMING (OR_ACS_DIV4 | OR_SCY_3_CLK | OR_CSNT_SAM | OR_EHTR) 320#define CONFIG_SYS_OR6_PRELIM (NX823_IO_OR_AM | CPLD_TIMING | OR_BI) 321#define CONFIG_SYS_BR6_PRELIM (CPLD_BASE | BR_PS_8 | BR_V ) 322 323/* 324 * BR7 and OR7 (SED1386) 325 * FIXME timing not verified for SED controller 326 */ 327#define SED1386_BASE 0xF7000000 328#define CONFIG_SYS_OR7_PRELIM (0xFF000000 | OR_BI | OR_SETA) 329#define CONFIG_SYS_BR7_PRELIM (SED1386_BASE | BR_PS_16 | BR_V ) 330 331/* 332 * Memory Periodic Timer Prescaler 333 */ 334 335/* periodic timer for refresh */ 336#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ 337 338/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ 339#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 340#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 341 342/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 343#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 344#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 345 346/* 347 * MAMR settings for SDRAM 348 */ 349 350/* 8 column SDRAM */ 351#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 352 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 353 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 354/* 9 column SDRAM */ 355#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 356 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 357 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 358 359 360/* 361 * Internal Definitions 362 * 363 * Boot Flags 364 */ 365#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 366#define BOOTFLAG_WARM 0x02 /* Software reboot */ 367 368#define CONFIG_ENV_OVERWRITE /* allow changes to ethaddr (for now) */ 369#define CONFIG_ETHADDR 00:10:20:30:40:50 370#define CONFIG_IPADDR 10.77.77.20 371#define CONFIG_SERVERIP 10.77.77.250 372 373#endif /* __CONFIG_H */ 374