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26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30
31
32
33
34#define CONFIG_405EP 1
35#define CONFIG_4xx 1
36#define CONFIG_VOM405 1
37
38#define CONFIG_BOARD_EARLY_INIT_F 1
39#define CONFIG_MISC_INIT_R 1
40
41#define CONFIG_SYS_CLK_FREQ 33330000
42
43#define CONFIG_BAUDRATE 9600
44#define CONFIG_BOOTDELAY 3
45
46#undef CONFIG_BOOTARGS
47#undef CONFIG_BOOTCOMMAND
48
49#define CONFIG_PREBOOT
50
51#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
52
53#define CONFIG_NET_MULTI 1
54#undef CONFIG_HAS_ETH1
55
56#define CONFIG_PPC4xx_EMAC
57#define CONFIG_MII 1
58#define CONFIG_PHY_ADDR 0
59#define CONFIG_LXT971_NO_SLEEP 1
60#define CONFIG_RESET_PHY_R 1
61
62
63
64
65#define CONFIG_BOOTP_SUBNETMASK
66#define CONFIG_BOOTP_GATEWAY
67#define CONFIG_BOOTP_HOSTNAME
68#define CONFIG_BOOTP_BOOTPATH
69#define CONFIG_BOOTP_DNS
70#define CONFIG_BOOTP_DNS2
71#define CONFIG_BOOTP_SEND_HOSTNAME
72
73
74
75
76#include <config_cmd_default.h>
77
78#define CONFIG_CMD_DHCP
79#define CONFIG_CMD_BSP
80#define CONFIG_CMD_IRQ
81#define CONFIG_CMD_ELF
82#define CONFIG_CMD_I2C
83#define CONFIG_CMD_MII
84#define CONFIG_CMD_PING
85#define CONFIG_CMD_EEPROM
86
87#define CONFIG_OF_LIBFDT
88#define CONFIG_OF_BOARD_SETUP
89
90#undef CONFIG_WATCHDOG
91
92#define CONFIG_SDRAM_BANK0 1
93
94#undef CONFIG_PRAM
95
96
97
98
99#define CONFIG_SYS_LONGHELP
100#define CONFIG_SYS_PROMPT "=> "
101
102#undef CONFIG_SYS_HUSH_PARSER
103#ifdef CONFIG_SYS_HUSH_PARSER
104#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
105#endif
106
107#if defined(CONFIG_CMD_KGDB)
108#define CONFIG_SYS_CBSIZE 1024
109#else
110#define CONFIG_SYS_CBSIZE 256
111#endif
112#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
113#define CONFIG_SYS_MAXARGS 16
114#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
115
116#define CONFIG_SYS_DEVICE_NULLDEV 1
117
118#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
119
120#define CONFIG_SYS_MEMTEST_START 0x0400000
121#define CONFIG_SYS_MEMTEST_END 0x0C00000
122
123#undef CONFIG_SYS_EXT_SERIAL_CLOCK
124#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59
125#define CONFIG_SYS_BASE_BAUD 691200
126#undef CONFIG_UART1_CONSOLE
127
128
129#define CONFIG_SYS_BAUDRATE_TABLE \
130 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
131 57600, 115200, 230400, 460800, 921600 }
132
133#define CONFIG_SYS_LOAD_ADDR 0x100000
134#define CONFIG_SYS_EXTBDINFO 1
135
136#define CONFIG_SYS_HZ 1000
137
138#define CONFIG_CMDLINE_EDITING 1
139#define CONFIG_ZERO_BOOTDELAY_CHECK
140
141#define CONFIG_VERSION_VARIABLE 1
142
143#define CONFIG_SYS_RX_ETH_BUFFER 16
144
145
146
147
148
149
150#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
151
152
153
154#define FLASH_BASE0_PRELIM 0xFFC00000
155
156#define CONFIG_SYS_MAX_FLASH_BANKS 1
157#define CONFIG_SYS_MAX_FLASH_SECT 256
158
159#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
160#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
161
162#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
163#define CONFIG_SYS_FLASH_ADDR0 0x5555
164#define CONFIG_SYS_FLASH_ADDR1 0x2AAA
165
166
167
168
169#define CONFIG_SYS_FLASH_READ0 0x0000
170#define CONFIG_SYS_FLASH_READ1 0x0001
171#define CONFIG_SYS_FLASH_READ2 0x0002
172
173#define CONFIG_SYS_FLASH_EMPTY_INFO
174
175
176
177
178
179
180#define CONFIG_SYS_SDRAM_BASE 0x00000000
181#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
182#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
183#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
184#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
185
186#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
187# define CONFIG_SYS_RAMBOOT 1
188#else
189# undef CONFIG_SYS_RAMBOOT
190#endif
191
192
193
194
195#define CONFIG_ENV_IS_IN_EEPROM 1
196#define CONFIG_ENV_OFFSET 0x100
197#define CONFIG_ENV_SIZE 0x700
198
199
200#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500
201#define CONFIG_SYS_NVRAM_SIZE 242
202
203
204
205
206#define CONFIG_HARD_I2C
207#define CONFIG_SYS_I2C_SPEED 400000
208#define CONFIG_SYS_I2C_SLAVE 0x7F
209
210#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
211#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
212
213#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
214#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
215
216
217#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
218
219
220
221
222#define CAN_BA 0xF0000000
223
224
225#define CONFIG_SYS_EBC_PB0AP 0x92015480
226#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
227
228
229#define CONFIG_SYS_EBC_PB2AP 0x010053C0
230#define CONFIG_SYS_EBC_PB2CR 0xF0018000
231
232
233
234
235#define CONFIG_SYS_FPGA_XC95XL 1
236#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024
237
238
239#define CONFIG_SYS_FPGA_PRG 0x04000000
240#define CONFIG_SYS_FPGA_CLK 0x02000000
241#define CONFIG_SYS_FPGA_DATA 0x01000000
242#define CONFIG_SYS_FPGA_INIT 0x00010000
243#define CONFIG_SYS_FPGA_DONE 0x00008000
244
245
246
247
248
249#define CONFIG_SYS_TEMP_STACK_OCM 1
250
251
252#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
253#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
254#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
255#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
256
257#define CONFIG_SYS_GBL_DATA_SIZE 128
258#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
259#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
260
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275
276
277#define CONFIG_SYS_GPIO0_OSRH 0x40000500
278#define CONFIG_SYS_GPIO0_OSRL 0x00000110
279#define CONFIG_SYS_GPIO0_ISR1H 0x00000000
280#define CONFIG_SYS_GPIO0_ISR1L 0x14000045
281#define CONFIG_SYS_GPIO0_TSRH 0x00000000
282#define CONFIG_SYS_GPIO0_TSRL 0x00000000
283#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
284
285
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288
289
290#define BOOTFLAG_COLD 0x01
291#define BOOTFLAG_WARM 0x02
292
293
294
295
296
297#if 0
298#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
299#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
300#endif
301#if 0
302#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
303#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
304#endif
305#if 1
306#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
307#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
308#endif
309
310#endif
311