LXR uboot/include/configs/kilauea.h

   1/*
   2 * Copyright (c) 2008 Nuovation System Designs, LLC
   3 *   Grant Erickson <gerickson@nuovations.com>
   4 *
   5 * (C) Copyright 2007
   6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27/************************************************************************
  28 * kilauea.h - configuration for AMCC Kilauea (405EX)
  29 ***********************************************************************/
  30
  31#ifndef __CONFIG_H
  32#define __CONFIG_H
  33
  34/*-----------------------------------------------------------------------
  35 * High Level Configuration Options
  36 *----------------------------------------------------------------------*/
  37#define CONFIG_KILAUEA          1               /* Board is Kilauea     */
  38#define CONFIG_4xx              1               /* ... PPC4xx family    */
  39#define CONFIG_405EX            1               /* Specifc 405EX support*/
  40#define CONFIG_SYS_CLK_FREQ     33333333        /* ext frequency to pll */
  41
  42/*
  43 * Include common defines/options for all AMCC eval boards
  44 */
  45#define CONFIG_HOSTNAME         kilauea
  46#include "amcc-common.h"
  47
  48#define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  49#define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
  50#define CONFIG_BOARD_EMAC_COUNT
  51
  52/*-----------------------------------------------------------------------
  53 * Base addresses -- Note these are effective addresses where the
  54 * actual resources get mapped (not physical addresses)
  55 *----------------------------------------------------------------------*/
  56#define CONFIG_SYS_FLASH_BASE           0xFC000000
  57#define CONFIG_SYS_NAND_ADDR            0xF8000000
  58#define CONFIG_SYS_FPGA_BASE            0xF0000000
  59#define CONFIG_SYS_PERIPHERAL_BASE      0xEF600000      /* internal peripherals*/
  60
  61/*-----------------------------------------------------------------------
  62 * Initial RAM & Stack Pointer Configuration Options
  63 *
  64 *   There are traditionally three options for the primordial
  65 *   (i.e. initial) stack usage on the 405-series:
  66 *
  67 *      1) On-chip Memory (OCM) (i.e. SRAM)
  68 *      2) Data cache
  69 *      3) SDRAM
  70 *
  71 *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
  72 *   the latter of which is less than desireable since it requires
  73 *   setting up the SDRAM and ECC in assembly code.
  74 *
  75 *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
  76 *   select on the External Bus Controller (EBC) and then select a
  77 *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
  78 *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
  79 *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
  80 *   physical SDRAM to use (3).
  81 *-----------------------------------------------------------------------*/
  82
  83#define CONFIG_SYS_INIT_DCACHE_CS       4
  84
  85#if defined(CONFIG_SYS_INIT_DCACHE_CS)
  86#define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_SDRAM_BASE + ( 1 << 30))    /*  1 GiB */
  87#else
  88#define CONFIG_SYS_INIT_RAM_ADDR        (CONFIG_SYS_SDRAM_BASE + (32 << 20))    /* 32 MiB */
  89#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
  90
  91#define CONFIG_SYS_INIT_RAM_END        (4 << 10)                        /*  4 KiB */
  92#define CONFIG_SYS_GBL_DATA_SIZE        256             /* num bytes initial data */
  93#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  94
  95/*
  96 * If the data cache is being used for the primordial stack and global
  97 * data area, the POST word must be placed somewhere else. The General
  98 * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
  99 * its compare and mask register contents across reset, so it is used
 100 * for the POST word.
 101 */
 102
 103#if defined(CONFIG_SYS_INIT_DCACHE_CS)
 104# define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 105# define CONFIG_SYS_POST_ALT_WORD_ADDR  (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
 106#else
 107# define CONFIG_SYS_INIT_EXTRA_SIZE     16
 108# define CONFIG_SYS_INIT_SP_OFFSET      (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
 109# define CONFIG_SYS_POST_WORD_ADDR      (CONFIG_SYS_GBL_DATA_OFFSET - 4)
 110# define CONFIG_SYS_OCM_DATA_ADDR       CONFIG_SYS_INIT_RAM_ADDR
 111#endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
 112
 113/*-----------------------------------------------------------------------
 114 * Serial Port
 115 *----------------------------------------------------------------------*/
 116#define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200        /* ext. 11.059MHz clk   */
 117/* define this if you want console on UART1 */
 118#undef CONFIG_UART1_CONSOLE
 119
 120/*-----------------------------------------------------------------------
 121 * Environment
 122 *----------------------------------------------------------------------*/
 123#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
 124#define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
 125#else
 126#define CONFIG_ENV_IS_IN_NAND   1       /* use NAND for environment vars        */
 127#define CONFIG_ENV_IS_EMBEDDED  1       /* use embedded environment */
 128#endif
 129
 130/*-----------------------------------------------------------------------
 131 * FLASH related
 132 *----------------------------------------------------------------------*/
 133#define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 134#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 135
 136#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 137#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 138#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 139
 140#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 141#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 142
 143#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 144#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 145
 146#ifdef CONFIG_ENV_IS_IN_FLASH
 147#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector  */
 148#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 149#define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 150
 151/* Address and size of Redundant Environment Sector     */
 152#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 153#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 154#endif /* CONFIG_ENV_IS_IN_FLASH */
 155
 156/*
 157 * IPL (Initial Program Loader, integrated inside CPU)
 158 * Will load first 4k from NAND (SPL) into cache and execute it from there.
 159 *
 160 * SPL (Secondary Program Loader)
 161 * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
 162 * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
 163 * controller and the NAND controller so that the special U-Boot image can be
 164 * loaded from NAND to SDRAM.
 165 *
 166 * NUB (NAND U-Boot)
 167 * This NAND U-Boot (NUB) is a special U-Boot version which can be started
 168 * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
 169 *
 170 * On 405EX the SPL is copied to SDRAM before the NAND controller is
 171 * set up. While still running from location 0xfffff000...0xffffffff the
 172 * NAND controller cannot be accessed since it is attached to CS0 too.
 173 */
 174#define CONFIG_SYS_NAND_BOOT_SPL_SRC    0xfffff000      /* SPL location                 */
 175#define CONFIG_SYS_NAND_BOOT_SPL_SIZE   (4 << 10)       /* SPL size                     */
 176#define CONFIG_SYS_NAND_BOOT_SPL_DST    0x00800000      /* Copy SPL here                */
 177#define CONFIG_SYS_NAND_U_BOOT_DST      0x01000000      /* Load NUB to this addr        */
 178#define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from this addr  */
 179#define CONFIG_SYS_NAND_BOOT_SPL_DELTA  (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
 180
 181/*
 182 * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
 183 */
 184#define CONFIG_SYS_NAND_U_BOOT_OFFS     (16 << 10)      /* Offset to RAM U-Boot image   */
 185#define CONFIG_SYS_NAND_U_BOOT_SIZE     (384 << 10)     /* Size of RAM U-Boot image     */
 186
 187/*
 188 * Now the NAND chip has to be defined (no autodetection used!)
 189 */
 190#define CONFIG_SYS_NAND_PAGE_SIZE       512             /* NAND chip page size          */
 191#define CONFIG_SYS_NAND_BLOCK_SIZE      (16 << 10)      /* NAND chip block size         */
 192#define CONFIG_SYS_NAND_PAGE_COUNT      32              /* NAND chip page count         */
 193#define CONFIG_SYS_NAND_BAD_BLOCK_POS   5               /* Location of bad block marker */
 194#define CONFIG_SYS_NAND_4_ADDR_CYCLE    1               /* Fourth addr used (>32MB)     */
 195
 196#define CONFIG_SYS_NAND_ECCSIZE 256
 197#define CONFIG_SYS_NAND_ECCBYTES        3
 198#define CONFIG_SYS_NAND_ECCSTEPS        (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
 199#define CONFIG_SYS_NAND_OOBSIZE 16
 200#define CONFIG_SYS_NAND_ECCTOTAL        (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
 201#define CONFIG_SYS_NAND_ECCPOS          {0, 1, 2, 3, 6, 7}
 202
 203#ifdef CONFIG_ENV_IS_IN_NAND
 204/*
 205 * For NAND booting the environment is embedded in the U-Boot image. Please take
 206 * look at the file board/amcc/sequoia/u-boot-nand.lds for details.
 207 */
 208#define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 209#define CONFIG_ENV_OFFSET               (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
 210#define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
 211#endif
 212
 213/*-----------------------------------------------------------------------
 214 * NAND FLASH
 215 *----------------------------------------------------------------------*/
 216#define CONFIG_SYS_MAX_NAND_DEVICE      1
 217#define NAND_MAX_CHIPS          1
 218#define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 219#define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips   */
 220
 221/*-----------------------------------------------------------------------
 222 * DDR SDRAM
 223 *----------------------------------------------------------------------*/
 224#define CONFIG_SYS_MBYTES_SDRAM        (256)            /* 256MB                        */
 225
 226/*
 227 * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
 228 *
 229 * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
 230 *       SDRAM Controller DDR autocalibration values and takes a lot longer
 231 *       to run than Method_B.
 232 * (See the Method_A and Method_B algorithm discription in the file:
 233 *      cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
 234 * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
 235 *
 236 * DDR Autocalibration Method_B is the default.
 237 */
 238#if 0
 239/*
 240 * Needs FIX!!!
 241 * Disable autocalibration for now, because of the unresolved problem
 242 * with kilauea board using 200MHz PLB/DDR2 frequency
 243 */
 244#define CONFIG_PPC4xx_DDR_AUTOCALIBRATION       /* IBM DDR autocalibration */
 245#define DEBUG_PPC4xx_DDR_AUTOCALIBRATION        /* dynamic DDR autocal debug */
 246#undef  CONFIG_PPC4xx_DDR_METHOD_A
 247#endif
 248
 249#define CONFIG_SYS_SDRAM0_MB0CF_BASE    ((  0 << 20) + CONFIG_SYS_SDRAM_BASE)
 250
 251/* DDR1/2 SDRAM Device Control Register Data Values */
 252#define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3)    | \
 253                                 SDRAM_RXBAS_SDSZ_256MB         | \
 254                                 SDRAM_RXBAS_SDAM_MODE7         | \
 255                                 SDRAM_RXBAS_SDBE_ENABLE)
 256#define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
 257#define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
 258#define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
 259#define CONFIG_SYS_SDRAM0_MCOPT1        (SDRAM_MCOPT1_PMU_OPEN          | \
 260                                 SDRAM_MCOPT1_8_BANKS           | \
 261                                 SDRAM_MCOPT1_DDR2_TYPE         | \
 262                                 SDRAM_MCOPT1_QDEP              | \
 263                                 SDRAM_MCOPT1_DCOO_DISABLED)
 264#define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 265#define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
 266                                 SDRAM_MODT_EB0R_ENABLE)
 267#define CONFIG_SYS_SDRAM0_MODT1 0x00000000
 268#define CONFIG_SYS_SDRAM0_CODT          (SDRAM_CODT_RK0R_ON             | \
 269                                 SDRAM_CODT_CKLZ_36OHM          | \
 270                                 SDRAM_CODT_DQS_1_8_V_DDR2      | \
 271                                 SDRAM_CODT_IO_NMODE)
 272#define CONFIG_SYS_SDRAM0_RTR           SDRAM_RTR_RINT_ENCODE(1560)
 273#define CONFIG_SYS_SDRAM0_INITPLR0      (SDRAM_INITPLR_ENABLE                   | \
 274                SDRAM_INITPLR_IMWT_ENCODE(80)                           | \
 275                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
 276#define CONFIG_SYS_SDRAM0_INITPLR1      (SDRAM_INITPLR_ENABLE                   | \
 277                SDRAM_INITPLR_IMWT_ENCODE(3)                            | \
 278                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)          | \
 279                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
 280                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 281#define CONFIG_SYS_SDRAM0_INITPLR2      (SDRAM_INITPLR_ENABLE                   | \
 282                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 283                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 284                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2)                 | \
 285                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
 286#define CONFIG_SYS_SDRAM0_INITPLR3      (SDRAM_INITPLR_ENABLE                   | \
 287                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 288                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 289                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3)                 | \
 290                SDRAM_INITPLR_IMA_ENCODE(0))
 291#define CONFIG_SYS_SDRAM0_INITPLR4      (SDRAM_INITPLR_ENABLE                   | \
 292                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 293                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 294                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
 295                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
 296                                         JEDEC_MA_EMR_RTT_75OHM))
 297#define CONFIG_SYS_SDRAM0_INITPLR5      (SDRAM_INITPLR_ENABLE                   | \
 298                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 299                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 300                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
 301                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
 302                                         JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
 303                                         JEDEC_MA_MR_BLEN_4 | \
 304                                         JEDEC_MA_MR_DLL_RESET))
 305#define CONFIG_SYS_SDRAM0_INITPLR6      (SDRAM_INITPLR_ENABLE                   | \
 306                SDRAM_INITPLR_IMWT_ENCODE(3)                            | \
 307                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE)          | \
 308                SDRAM_INITPLR_IBA_ENCODE(0x0)                           | \
 309                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 310#define CONFIG_SYS_SDRAM0_INITPLR7      (SDRAM_INITPLR_ENABLE                   | \
 311                SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 312                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 313#define CONFIG_SYS_SDRAM0_INITPLR8      (SDRAM_INITPLR_ENABLE                   | \
 314                SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 315                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 316#define CONFIG_SYS_SDRAM0_INITPLR9      (SDRAM_INITPLR_ENABLE                   | \
 317                SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 318                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 319#define CONFIG_SYS_SDRAM0_INITPLR10     (SDRAM_INITPLR_ENABLE                   | \
 320                SDRAM_INITPLR_IMWT_ENCODE(26)                           | \
 321                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 322#define CONFIG_SYS_SDRAM0_INITPLR11     (SDRAM_INITPLR_ENABLE                   | \
 323                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 324                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 325                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR)                   | \
 326                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
 327                                         JEDEC_MA_MR_CL_DDR2_4_0_CLK | \
 328                                         JEDEC_MA_MR_BLEN_4))
 329#define CONFIG_SYS_SDRAM0_INITPLR12     (SDRAM_INITPLR_ENABLE                   | \
 330                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 331                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 332                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
 333                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
 334                                         JEDEC_MA_EMR_RDQS_DISABLE | \
 335                                         JEDEC_MA_EMR_DQS_DISABLE | \
 336                                         JEDEC_MA_EMR_RTT_DISABLED | \
 337                                         JEDEC_MA_EMR_ODS_NORMAL))
 338#define CONFIG_SYS_SDRAM0_INITPLR13     (SDRAM_INITPLR_ENABLE                   | \
 339                SDRAM_INITPLR_IMWT_ENCODE(2)                            | \
 340                SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR)                | \
 341                SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR)                  | \
 342                SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
 343                                         JEDEC_MA_EMR_RDQS_DISABLE | \
 344                                         JEDEC_MA_EMR_DQS_DISABLE | \
 345                                         JEDEC_MA_EMR_RTT_DISABLED | \
 346                                         JEDEC_MA_EMR_ODS_NORMAL))
 347#define CONFIG_SYS_SDRAM0_INITPLR14     (SDRAM_INITPLR_DISABLE)
 348#define CONFIG_SYS_SDRAM0_INITPLR15     (SDRAM_INITPLR_DISABLE)
 349#define CONFIG_SYS_SDRAM0_RQDC          (SDRAM_RQDC_RQDE_ENABLE | \
 350                                 SDRAM_RQDC_RQFD_ENCODE(56))
 351#define CONFIG_SYS_SDRAM0_RFDC          SDRAM_RFDC_RFFD_ENCODE(521)
 352#define CONFIG_SYS_SDRAM0_RDCC          (SDRAM_RDCC_RDSS_T2)
 353#define CONFIG_SYS_SDRAM0_DLCR          (SDRAM_DLCR_DCLM_AUTO           | \
 354                                 SDRAM_DLCR_DLCS_CONT_DONE      | \
 355                                 SDRAM_DLCR_DLCV_ENCODE(165))
 356#define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
 357#define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
 358#define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
 359                                 SDRAM_SDTR1_RTW_2_CLK  | \
 360                                 SDRAM_SDTR1_RTRO_1_CLK)
 361#define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK          | \
 362                                 SDRAM_SDTR2_WTR_2_CLK          | \
 363                                 SDRAM_SDTR2_XSNR_32_CLK        | \
 364                                 SDRAM_SDTR2_WPC_4_CLK          | \
 365                                 SDRAM_SDTR2_RPC_2_CLK          | \
 366                                 SDRAM_SDTR2_RP_3_CLK           | \
 367                                 SDRAM_SDTR2_RRD_2_CLK)
 368#define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(8)      | \
 369                                 SDRAM_SDTR3_RC_ENCODE(11)      | \
 370                                 SDRAM_SDTR3_XCS                | \
 371                                 SDRAM_SDTR3_RFC_ENCODE(26))
 372#define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
 373                                 SDRAM_MMODE_DCL_DDR2_4_0_CLK | \
 374                                 SDRAM_MMODE_BLEN_4)
 375#define CONFIG_SYS_SDRAM0_MEMODE        (SDRAM_MEMODE_DQS_DISABLE | \
 376                                 SDRAM_MEMODE_RTT_75OHM)
 377
 378/*-----------------------------------------------------------------------
 379 * I2C
 380 *----------------------------------------------------------------------*/
 381#define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
 382
 383#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   6       /* 24C02 requires 5ms delay */
 384#define CONFIG_SYS_I2C_EEPROM_ADDR      0x52    /* I2C boot EEPROM (24C02BN)    */
 385#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1       /* Bytes of address             */
 386
 387/* Standard DTT sensor configuration */
 388#define CONFIG_DTT_DS1775       1
 389#define CONFIG_DTT_SENSORS      { 0 }
 390#define CONFIG_SYS_I2C_DTT_ADDR 0x48
 391
 392/* RTC configuration */
 393#define CONFIG_RTC_DS1338       1
 394#define CONFIG_SYS_I2C_RTC_ADDR 0x68
 395
 396/*-----------------------------------------------------------------------
 397 * Ethernet
 398 *----------------------------------------------------------------------*/
 399#define CONFIG_M88E1111_PHY     1
 400#define CONFIG_IBM_EMAC4_V4     1
 401#define CONFIG_EMAC_PHY_MODE    EMAC_PHY_MODE_RGMII_RGMII
 402#define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 403
 404#define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 405#define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 406
 407#define CONFIG_HAS_ETH0         1
 408
 409#define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 410#define CONFIG_PHY1_ADDR        2
 411
 412/* Debug messages for the DDR autocalibration */
 413#define CONFIG_AUTOCALIB                "silent\0"  /* default is non-verbose */
 414
 415/*
 416 * Default environment variables
 417 */
 418#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 419        CONFIG_AMCC_DEF_ENV                                             \
 420        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 421        CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 422        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 423        CONFIG_AMCC_DEF_ENV_NAND_UPD                                    \
 424        "logversion=2\0"                                                \
 425        "kernel_addr=fc000000\0"                                        \
 426        "fdt_addr=fc1e0000\0"                                           \
 427        "ramdisk_addr=fc200000\0"                                       \
 428        "pciconfighost=1\0"                                             \
 429        "pcie_mode=RP:RP\0"                                             \
 430        ""
 431
 432/*
 433 * Commands additional to the ones defined in amcc-common.h
 434 */
 435#define CONFIG_CMD_DATE
 436#define CONFIG_CMD_LOG
 437#define CONFIG_CMD_NAND
 438#define CONFIG_CMD_PCI
 439#define CONFIG_CMD_SNTP
 440
 441/* POST support */
 442#define CONFIG_POST             (CONFIG_SYS_POST_CACHE          | \
 443                                 CONFIG_SYS_POST_CPU            | \
 444                                 CONFIG_SYS_POST_ETHER          | \
 445                                 CONFIG_SYS_POST_I2C            | \
 446                                 CONFIG_SYS_POST_MEMORY | \
 447                                 CONFIG_SYS_POST_UART)
 448
 449/* Define here the base-addresses of the UARTs to test in POST */
 450#define CONFIG_SYS_POST_UART_TABLE      {UART0_BASE, UART1_BASE}
 451
 452#define CONFIG_LOGBUFFER
 453#define CONFIG_SYS_POST_CACHE_ADDR      0x00800000 /* free virtual address      */
 454
 455#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 456
 457/*-----------------------------------------------------------------------
 458 * PCI stuff
 459 *----------------------------------------------------------------------*/
 460#define CONFIG_PCI                      /* include pci support          */
 461#define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
 462#define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 463#define CONFIG_PCI_CONFIG_HOST_BRIDGE
 464
 465/*-----------------------------------------------------------------------
 466 * PCIe stuff
 467 *----------------------------------------------------------------------*/
 468#define CONFIG_SYS_PCIE_MEMBASE 0x90000000      /* mapped PCIe memory   */
 469#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* 128 Meg, smallest incr per port */
 470
 471#define CONFIG_SYS_PCIE0_CFGBASE        0xa0000000      /* remote access */
 472#define CONFIG_SYS_PCIE0_XCFGBASE       0xb0000000      /* local access */
 473#define CONFIG_SYS_PCIE0_CFGMASK        0xe0000001      /* 512 Meg */
 474
 475#define CONFIG_SYS_PCIE1_CFGBASE        0xc0000000      /* remote access */
 476#define CONFIG_SYS_PCIE1_XCFGBASE       0xd0000000      /* local access */
 477#define CONFIG_SYS_PCIE1_CFGMASK        0xe0000001      /* 512 Meg */
 478
 479#define CONFIG_SYS_PCIE0_UTLBASE        0xef502000
 480#define CONFIG_SYS_PCIE1_UTLBASE        0xef503000
 481
 482/* base address of inbound PCIe window */
 483#define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000000000000ULL
 484
 485/*-----------------------------------------------------------------------
 486 * External Bus Controller (EBC) Setup
 487 *----------------------------------------------------------------------*/
 488#if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 489/* booting from NAND, so NAND chips select has to be on CS 0 */
 490#define CONFIG_SYS_NAND_CS              0               /* NAND chip connected to CSx   */
 491
 492/* Memory Bank 1 (NOR-FLASH) initialization                                     */
 493#define CONFIG_SYS_EBC_PB1AP            0x05806500
 494#define CONFIG_SYS_EBC_PB1CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
 495
 496/* Memory Bank 0 (NAND-FLASH) initialization                                    */
 497#define CONFIG_SYS_EBC_PB0AP            0x018003c0
 498#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1e000)
 499#else
 500#define CONFIG_SYS_NAND_CS              1               /* NAND chip connected to CSx   */
 501
 502/* Memory Bank 0 (NOR-FLASH) initialization                                     */
 503#define CONFIG_SYS_EBC_PB0AP            0x05806500
 504#define CONFIG_SYS_EBC_PB0CR           0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit*/
 505
 506/* Memory Bank 1 (NAND-FLASH) initialization                                    */
 507#define CONFIG_SYS_EBC_PB1AP            0x018003c0
 508#define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_NAND_ADDR | 0x1e000)
 509#endif
 510
 511/* Memory Bank 2 (FPGA) initialization                                          */
 512#define CONFIG_SYS_EBC_PB2AP           0x9400C800
 513#define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_FPGA_BASE | 0x18000)
 514
 515#define CONFIG_SYS_EBC_CFG              0x7FC00000 /*  EBC0_CFG */
 516
 517/*-----------------------------------------------------------------------
 518 * GPIO Setup
 519 *----------------------------------------------------------------------*/
 520#define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 521{                                                                                       \
 522/* GPIO Core 0 */                                                                       \
 523{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0)                 */      \
 524{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1)                 */      \
 525{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2)                 */      \
 526{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3)                 */      \
 527{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20)    USB2_DATA(4)    */      \
 528{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21)    USB2_DATA(5)    */      \
 529{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22)    USB2_DATA(6)    */      \
 530{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23)    USB2_DATA(7)    */      \
 531{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1)   IRQ(7)          */      \
 532{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2)   IRQ(8)          */      \
 533{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3)  IRQ(9)          */      \
 534{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 IRQ(6)                         */      \
 535{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)   USB2_DATA(0)    */      \
 536{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)   USB2_DATA(1)    */      \
 537{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18)   USB2_DATA(2)    */      \
 538{GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19)   USB2_DATA(3)    */      \
 539{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD      UART1_CTS       */      \
 540{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR      UART1_RTS       */      \
 541{GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS                      */      \
 542{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS                      */      \
 543{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO20 UART0_DTR      UART1_TX        */      \
 544{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO21 UART0_RI       UART1_RX        */      \
 545{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ   DMA_ACK2        */      \
 546{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK   DMA_REQ2        */      \
 547{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ    DMA_EOT2        IRQ(4) */ \
 548{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK    DMA_ACK3        IRQ(3) */ \
 549{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)    DMA_EOT0        TS(3) */ \
 550{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ    DMA_EOT3        IRQ(5) */ \
 551{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO28                                */      \
 552{GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO29 DMA_EOT1       IRQ(2)          */      \
 553{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO30 DMA_REQ1       IRQ(1)          */      \
 554{GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO31 DMA_ACK1       IRQ(0)          */      \
 555}                                                                                               \
 556}
 557
 558/*-----------------------------------------------------------------------
 559 * Some Kilauea stuff..., mainly fpga registers
 560 */
 561#define CONFIG_SYS_FPGA_REG_BASE                CONFIG_SYS_FPGA_BASE
 562#define CONFIG_SYS_FPGA_FIFO_BASE               (in32(CONFIG_SYS_FPGA_BASE) | (1 << 10))
 563
 564/* interrupt */
 565#define CONFIG_SYS_FPGA_SLIC0_R_DPRAM_INT       0x80000000
 566#define CONFIG_SYS_FPGA_SLIC0_W_DPRAM_INT       0x40000000
 567#define CONFIG_SYS_FPGA_SLIC1_R_DPRAM_INT       0x20000000
 568#define CONFIG_SYS_FPGA_SLIC1_W_DPRAM_INT       0x10000000
 569#define CONFIG_SYS_FPGA_PHY0_INT                0x08000000
 570#define CONFIG_SYS_FPGA_PHY1_INT                0x04000000
 571#define CONFIG_SYS_FPGA_SLIC0_INT               0x02000000
 572#define CONFIG_SYS_FPGA_SLIC1_INT               0x01000000
 573
 574/* DPRAM setting */
 575/* 00: 32B; 01: 64B; 10: 128B; 11: 256B  */
 576#define CONFIG_SYS_FPGA_DPRAM_R_INT_LINE        0x00400000      /* 64 B */
 577#define CONFIG_SYS_FPGA_DPRAM_W_INT_LINE        0x00100000      /* 64 B */
 578#define CONFIG_SYS_FPGA_DPRAM_RW_TYPE           0x00080000
 579#define CONFIG_SYS_FPGA_DPRAM_RST               0x00040000
 580#define CONFIG_SYS_FPGA_UART0_FO                0x00020000
 581#define CONFIG_SYS_FPGA_UART1_FO                0x00010000
 582
 583/* loopback */
 584#define CONFIG_SYS_FPGA_CHIPSIDE_LOOPBACK       0x00004000
 585#define CONFIG_SYS_FPGA_LINESIDE_LOOPBACK       0x00008000
 586#define CONFIG_SYS_FPGA_SLIC0_ENABLE            0x00002000
 587#define CONFIG_SYS_FPGA_SLIC1_ENABLE            0x00001000
 588#define CONFIG_SYS_FPGA_SLIC0_CS                0x00000800
 589#define CONFIG_SYS_FPGA_SLIC1_CS                0x00000400
 590#define CONFIG_SYS_FPGA_USER_LED0               0x00000200
 591#define CONFIG_SYS_FPGA_USER_LED1               0x00000100
 592
 593#endif  /* __CONFIG_H */
 594