1/* 2 * (C) Copyright 2002 3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 4 * 5 * (C) Copyright 2002 6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 7 * Marius Groeger <mgroeger@sysgo.de> 8 * 9 * Configuation settings for the LUBBOCK board. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30#ifndef __CONFIG_H 31#define __CONFIG_H 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ 38#define CONFIG_LUBBOCK 1 /* on an LUBBOCK Board */ 39#define CONFIG_LCD 1 40#ifdef CONFIG_LCD 41#define CONFIG_SHARP_LM8V31 42#endif 43#define CONFIG_MMC 1 44#define BOARD_LATE_INIT 1 45#define CONFIG_DOS_PARTITION 46 47#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 48 49/* 50 * Size of malloc() pool 51 */ 52#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 53#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 54 55/* 56 * Hardware drivers 57 */ 58#define CONFIG_DRIVER_LAN91C96 59#define CONFIG_LAN91C96_BASE 0x0C000000 60 61/* 62 * select serial console configuration 63 */ 64#define CONFIG_FFUART 1 /* we use FFUART on LUBBOCK */ 65 66/* allow to overwrite serial and ethaddr */ 67#define CONFIG_ENV_OVERWRITE 68 69#define CONFIG_BAUDRATE 115200 70 71 72/* 73 * BOOTP options 74 */ 75#define CONFIG_BOOTP_BOOTFILESIZE 76#define CONFIG_BOOTP_BOOTPATH 77#define CONFIG_BOOTP_GATEWAY 78#define CONFIG_BOOTP_HOSTNAME 79 80 81/* 82 * Command line configuration. 83 */ 84#include <config_cmd_default.h> 85 86#define CONFIG_CMD_MMC 87#define CONFIG_CMD_FAT 88 89 90#define CONFIG_BOOTDELAY 3 91#define CONFIG_ETHADDR 08:00:3e:26:0a:5b 92#define CONFIG_NETMASK 255.255.0.0 93#define CONFIG_IPADDR 192.168.0.21 94#define CONFIG_SERVERIP 192.168.0.250 95#define CONFIG_BOOTCOMMAND "bootm 80000" 96#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" 97#define CONFIG_CMDLINE_TAG 98#define CONFIG_TIMESTAMP 99 100#if defined(CONFIG_CMD_KGDB) 101#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 102#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 103#endif 104 105/* 106 * Miscellaneous configurable options 107 */ 108#define CONFIG_SYS_HUSH_PARSER 1 109#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 110 111#define CONFIG_SYS_LONGHELP /* undef to save memory */ 112#ifdef CONFIG_SYS_HUSH_PARSER 113#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ 114#else 115#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 116#endif 117#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 118#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 119#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 120#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 121#define CONFIG_SYS_DEVICE_NULLDEV 1 122 123#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 124#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 125 126#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ 127 128#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */ 129 130#define CONFIG_SYS_HZ 3686400 /* incrementer freq: 3.6864 MHz */ 131#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/200/100 MHz */ 132 133 /* valid baudrates */ 134#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 135 136#define CONFIG_SYS_MMC_BASE 0xF0000000 137 138/* 139 * Stack sizes 140 * 141 * The stack sizes are set up in start.S using the settings below 142 */ 143#define CONFIG_STACKSIZE (128*1024) /* regular stack */ 144#ifdef CONFIG_USE_IRQ 145#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ 146#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ 147#endif 148 149/* 150 * Physical Memory Map 151 */ 152#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ 153#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 154#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 155#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ 156#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ 157#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ 158#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ 159#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ 160#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ 161 162#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 163#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ 164#define PHYS_FLASH_SIZE 0x02000000 /* 32 MB */ 165#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ 166#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ 167 168#define CONFIG_SYS_DRAM_BASE 0xa0000000 169#define CONFIG_SYS_DRAM_SIZE 0x04000000 170 171#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 172 173#define FPGA_REGS_BASE_PHYSICAL 0x08000000 174 175/* 176 * GPIO settings 177 */ 178#define CONFIG_SYS_GPSR0_VAL 0x00008000 179#define CONFIG_SYS_GPSR1_VAL 0x00FC0382 180#define CONFIG_SYS_GPSR2_VAL 0x0001FFFF 181#define CONFIG_SYS_GPCR0_VAL 0x00000000 182#define CONFIG_SYS_GPCR1_VAL 0x00000000 183#define CONFIG_SYS_GPCR2_VAL 0x00000000 184#define CONFIG_SYS_GPDR0_VAL 0x0060A800 185#define CONFIG_SYS_GPDR1_VAL 0x00FF0382 186#define CONFIG_SYS_GPDR2_VAL 0x0001C000 187#define CONFIG_SYS_GAFR0_L_VAL 0x98400000 188#define CONFIG_SYS_GAFR0_U_VAL 0x00002950 189#define CONFIG_SYS_GAFR1_L_VAL 0x000A9558 190#define CONFIG_SYS_GAFR1_U_VAL 0x0005AAAA 191#define CONFIG_SYS_GAFR2_L_VAL 0xA0000000 192#define CONFIG_SYS_GAFR2_U_VAL 0x00000002 193 194#define CONFIG_SYS_PSSR_VAL 0x20 195 196/* 197 * Memory settings 198 */ 199#define CONFIG_SYS_MSC0_VAL 0x23F223F2 200#define CONFIG_SYS_MSC1_VAL 0x3FF1A441 201#define CONFIG_SYS_MSC2_VAL 0x7FF97FF1 202#define CONFIG_SYS_MDCNFG_VAL 0x00001AC9 203#define CONFIG_SYS_MDREFR_VAL 0x00018018 204#define CONFIG_SYS_MDMRS_VAL 0x00000000 205 206/* 207 * PCMCIA and CF Interfaces 208 */ 209#define CONFIG_SYS_MECR_VAL 0x00000000 210#define CONFIG_SYS_MCMEM0_VAL 0x00010504 211#define CONFIG_SYS_MCMEM1_VAL 0x00010504 212#define CONFIG_SYS_MCATT0_VAL 0x00010504 213#define CONFIG_SYS_MCATT1_VAL 0x00010504 214#define CONFIG_SYS_MCIO0_VAL 0x00004715 215#define CONFIG_SYS_MCIO1_VAL 0x00004715 216 217#define _LED 0x08000010 218#define LED_BLANK 0x08000040 219 220/* 221 * FLASH and environment organization 222 */ 223#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 224#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ 225 226/* timeout values are in ticks */ 227#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 228#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ 229 230/* NOTE: many default partitioning schemes assume the kernel starts at the 231 * second sector, not an environment. You have been warned! 232 */ 233#define CONFIG_SYS_MONITOR_LEN PHYS_FLASH_SECT_SIZE 234#define CONFIG_ENV_IS_IN_FLASH 1 235#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) 236#define CONFIG_ENV_SECT_SIZE PHYS_FLASH_SECT_SIZE 237#define CONFIG_ENV_SIZE (PHYS_FLASH_SECT_SIZE / 16) 238 239 240/* 241 * FPGA Offsets 242 */ 243#define WHOAMI_OFFSET 0x00 244#define HEXLED_OFFSET 0x10 245#define BLANKLED_OFFSET 0x40 246#define DISCRETELED_OFFSET 0x40 247#define CNFG_SWITCHES_OFFSET 0x50 248#define USER_SWITCHES_OFFSET 0x60 249#define MISC_WR_OFFSET 0x80 250#define MISC_RD_OFFSET 0x90 251#define INT_MASK_OFFSET 0xC0 252#define INT_CLEAR_OFFSET 0xD0 253#define GP_OFFSET 0x100 254 255#endif /* __CONFIG_H */ 256