1/* 2 * (C) Copyright 2008 3 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24#ifndef __CONFIG_H 25#define __CONFIG_H 26 27/* 28 * High Level Configuration Options 29 * (easy to change) 30 */ 31 32#define CONFIG_8260 1 33#define CONFIG_MPC8260 1 34#define CONFIG_MUAS3001 1 35 36#define CONFIG_CPM2 1 /* Has a CPM2 */ 37 38/* Do boardspecific init */ 39#define CONFIG_BOARD_EARLY_INIT_R 1 40 41/* enable Watchdog */ 42#define CONFIG_WATCHDOG 1 43 44/* 45 * Select serial console configuration 46 * 47 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 48 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 49 * for SCC). 50 */ 51#define CONFIG_CONS_ON_SMC /* Console is on SMC */ 52#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ 53#undef CONFIG_CONS_NONE /* It's not on external UART */ 54#if defined(CONFIG_MUAS_DEV_BOARD) 55#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ 56#else 57#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ 58#endif 59 60/* 61 * Select ethernet configuration 62 * 63 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, 64 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for 65 * SCC, 1-3 for FCC) 66 * 67 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines 68 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET 69 * must be unset. 70 */ 71#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ 72#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ 73#undef CONFIG_ETHER_NONE /* No external Ethernet */ 74 75#define CONFIG_ETHER_INDEX 1 76#define CONFIG_ETHER_ON_FCC1 77#define FCC_ENET 78 79/* 80 * - Rx-CLK is CLK11 81 * - Tx-CLK is CLK12 82 */ 83# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12) 84# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) 85/* 86 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 87 */ 88# define CONFIG_SYS_CPMFCR_RAMTYPE (0) 89/* know on local Bus */ 90/* define CONFIG_SYS_CPMFCR_RAMTYPE (CPMFCR_DTB | CPMFCR_BDB) */ 91/* 92 * - Enable Full Duplex in FSMR 93 */ 94# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 95 96#define CONFIG_MII /* MII PHY management */ 97#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ 98# define CONFIG_SYS_PHY_ADDR 1 99/* 100 * GPIO pins used for bit-banged MII communications 101 */ 102#define MDIO_PORT 0 /* Port A */ 103 104#define CONFIG_SYS_MDIO_PIN 0x00200000 /* PA10 */ 105#define CONFIG_SYS_MDC_PIN 0x00400000 /* PA9 */ 106 107#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN) 108#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN) 109#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0) 110 111#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \ 112 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN 113 114#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \ 115 else iop->pdat &= ~CONFIG_SYS_MDC_PIN 116 117#define MIIDELAY udelay(1) 118 119#ifndef CONFIG_8260_CLKIN 120#define CONFIG_8260_CLKIN 66000000 /* in Hz */ 121#endif 122 123#define CONFIG_BAUDRATE 115200 124 125/* 126 * Command line configuration. 127 */ 128#include <config_cmd_default.h> 129 130#define CONFIG_CMD_DTT 131#define CONFIG_CMD_ECHO 132#define CONFIG_CMD_IMMAP 133#define CONFIG_CMD_MII 134#define CONFIG_CMD_PING 135#define CONFIG_CMD_I2C 136 137/* 138 * Default environment settings 139 */ 140#define CONFIG_EXTRA_ENV_SETTINGS \ 141 "netdev=eth0\0" \ 142 "u-boot_addr_r=100000\0" \ 143 "kernel_addr_r=200000\0" \ 144 "fdt_addr_r=400000\0" \ 145 "rootpath=/opt/eldk/ppc_6xx\0" \ 146 "u-boot=muas3001/u-boot.bin\0" \ 147 "bootfile=muas3001/uImage\0" \ 148 "fdt_file=muas3001/muas3001.dtb\0" \ 149 "ramdisk_file=uRamdisk\0" \ 150 "load=tftp ${u-boot_addr_r} ${u-boot}\0" \ 151 "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ 152 "cp.b ${u-boot_addr_r} ff000000 ${filesize};" \ 153 "prot on ff000000 ff03ffff\0" \ 154 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 155 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 156 "nfsroot=${serverip}:${rootpath}\0" \ 157 "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \ 158 "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ 159 "addip=setenv bootargs ${bootargs} " \ 160 "ip=${ipaddr}:${serverip}:${gatewayip}:" \ 161 "${netmask}:${hostname}:${netdev}:off panic=1\0" \ 162 "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ 163 "tftp ${fdt_addr_r} ${fdt_file}; run nfsargs addip addcons;" \ 164 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ 165 "net_self=tftp ${kernel_addr_r} ${bootfile}; " \ 166 "tftp ${fdt_addr_r} ${fdt_file}; " \ 167 "tftp ${ramdisk_addr} ${ramdisk_file}; " \ 168 "run ramargs addip; " \ 169 "bootm ${kernel_addr_r} ${ramdisk_addr} ${fdt_addr_r}\0" \ 170 "ramdisk_addr=ff210000\0" \ 171 "kernel_addr=ff050000\0" \ 172 "fdt_addr=ff200000\0" \ 173 "flash_self=run ramargs addip addcons;bootm ${kernel_addr}" \ 174 " ${ramdisk_addr} ${fdt_addr}\0" \ 175 "updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr_r}" \ 176 " ${ramdisk_file};" \ 177 "cp.b ${kernel_addr_r} ${ramdisk_addr} ${filesize}\0" \ 178 "updatekernel=era ${kernel_addr} +1b0000;tftpb ${kernel_addr_r}" \ 179 " ${bootfile};" \ 180 "cp.b ${kernel_addr_r} ${kernel_addr} ${filesize}\0" \ 181 "updatefdt=era ${fdt_addr} +10000;tftpb ${fdt_addr_r} ${fdt_file};" \ 182 "cp.b ${fdt_addr_r} ${fdt_addr} ${filesize}\0" \ 183 "" 184 185#define CONFIG_BOOTCOMMAND "run net_nfs" 186#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 187 188/* 189 * Miscellaneous configurable options 190 */ 191#define CONFIG_SYS_HUSH_PARSER 192#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 193#define CONFIG_SYS_LONGHELP /* undef to save memory */ 194#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 195#if defined(CONFIG_CMD_KGDB) 196#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 197#else 198#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 199#endif 200#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 201#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 202#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 203 204#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 205#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 206 207#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 208 209#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 210 211#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 212 213#define CONFIG_SYS_SDRAM_BASE 0x00000000 214#define CONFIG_SYS_FLASH_BASE 0xFF000000 215#define CONFIG_SYS_FLASH_SIZE 32 216#define CONFIG_SYS_FLASH_CFI 217#define CONFIG_FLASH_CFI_DRIVER 218#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 219#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 220 221#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 222 223#define CONFIG_SYS_MONITOR_BASE TEXT_BASE 224#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 225#define CONFIG_SYS_RAMBOOT 226#endif 227 228#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */ 229 230#define CONFIG_ENV_IS_IN_FLASH 231 232#ifdef CONFIG_ENV_IS_IN_FLASH 233#define CONFIG_ENV_SECT_SIZE 0x10000 234#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 235#endif /* CONFIG_ENV_IS_IN_FLASH */ 236 237/* 238 * I2C Bus 239 */ 240#define CONFIG_HARD_I2C 1 /* To enable I2C support */ 241#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ 242#define CONFIG_SYS_I2C_SLAVE 0x7F 243 244#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 245/* I2C SYSMON (LM75, AD7414 is almost compatible) */ 246#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ 247#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ 248#define CONFIG_SYS_DTT_MAX_TEMP 70 249#define CONFIG_SYS_DTT_LOW_TEMP -30 250#define CONFIG_SYS_DTT_HYSTERESIS 3 251 252#define CONFIG_SYS_IMMR 0xF0000000 253#define CONFIG_SYS_DEFAULT_IMMR 0x0F010000 254 255#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 256#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ 257#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 258#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 259#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 260 261/* Hard reset configuration word */ 262#define CONFIG_SYS_HRCW_MASTER 0x0E028200 /* BPS=11 CIP=1 ISB=010 BMS=1 */ 263 264/* No slaves */ 265#define CONFIG_SYS_HRCW_SLAVE1 0 266#define CONFIG_SYS_HRCW_SLAVE2 0 267#define CONFIG_SYS_HRCW_SLAVE3 0 268#define CONFIG_SYS_HRCW_SLAVE4 0 269#define CONFIG_SYS_HRCW_SLAVE5 0 270#define CONFIG_SYS_HRCW_SLAVE6 0 271#define CONFIG_SYS_HRCW_SLAVE7 0 272 273#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 274#define BOOTFLAG_WARM 0x02 /* Software reboot */ 275 276#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ 277#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 278 279#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ 280#if defined(CONFIG_CMD_KGDB) 281# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 282#endif 283 284#define CONFIG_SYS_HID0_INIT 0 285#define CONFIG_SYS_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) 286 287#define CONFIG_SYS_HID2 0 288 289#define CONFIG_SYS_SIUMCR 0x00200000 290#define CONFIG_SYS_BCR 0x004c0000 291#define CONFIG_SYS_SCCR 0x0 292 293/*----------------------------------------------------------------------- 294 * SYPCR - System Protection Control 4-35 295 * SYPCR can only be written once after reset! 296 *----------------------------------------------------------------------- 297 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable 298 */ 299#if defined(CONFIG_WATCHDOG) 300#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 301 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) 302#else 303#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 304 SYPCR_SWRI|SYPCR_SWP) 305#endif /* CONFIG_WATCHDOG */ 306 307/*----------------------------------------------------------------------- 308 * RMR - Reset Mode Register 5-5 309 *----------------------------------------------------------------------- 310 * turn on Checkstop Reset Enable 311 */ 312#define CONFIG_SYS_RMR 0 313 314/*----------------------------------------------------------------------- 315 * TMCNTSC - Time Counter Status and Control 4-40 316 *----------------------------------------------------------------------- 317 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 318 * and enable Time Counter 319 */ 320#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 321 322/*----------------------------------------------------------------------- 323 * PISCR - Periodic Interrupt Status and Control 4-42 324 *----------------------------------------------------------------------- 325 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 326 * Periodic timer 327 */ 328#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 329 330/*----------------------------------------------------------------------- 331 * RCCR - RISC Controller Configuration 13-7 332 *----------------------------------------------------------------------- 333 */ 334#define CONFIG_SYS_RCCR 0 335 336/* 337 * Init Memory Controller: 338 * 339 * Bank Bus Machine PortSz Device 340 * ---- --- ------- ------ ------ 341 * 0 60x GPCM 32 bit FLASH 342 * 1 60x SDRAM 64 bit SDRAM 343 * 4 60x GPCM 16 bit I/O Ctrl 344 * 345 */ 346/* Bank 0 - FLASH 347 */ 348#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ 349 BRx_PS_32 |\ 350 BRx_MS_GPCM_P |\ 351 BRx_V) 352 353#define CONFIG_SYS_OR0_PRELIM (0xff000020) 354 355/* Bank 1 - 60x bus SDRAM 356 */ 357#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ 358 359#define CONFIG_SYS_MPTPR 0x2800 360 361/*----------------------------------------------------------------------------- 362 * Address for Mode Register Set (MRS) command 363 *----------------------------------------------------------------------------- 364 */ 365#define CONFIG_SYS_MRS_OFFS 0x00000110 366#define CONFIG_SYS_PSRT 0x13 367 368#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ 369 BRx_PS_64 |\ 370 BRx_MS_SDRAM_P |\ 371 BRx_V) 372 373#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_LITTLE 374 375/* SDRAM initialization values 376*/ 377#define CONFIG_SYS_OR1_LITTLE ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ 378 ORxS_BPD_4 |\ 379 ORxS_ROWST_PBI1_A7 |\ 380 ORxS_NUMR_12) 381 382#define CONFIG_SYS_PSDMR_LITTLE 0x004b36a3 383 384#define CONFIG_SYS_OR1_BIG ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ 385 ORxS_BPD_4 |\ 386 ORxS_ROWST_PBI1_A4 |\ 387 ORxS_NUMR_12) 388 389#define CONFIG_SYS_PSDMR_BIG 0x014f36a3 390 391/* IO on CS4 initialization values 392*/ 393#define CONFIG_SYS_IO_BASE 0xc0000000 394#define CONFIG_SYS_IO_SIZE 1 395 396#define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_IO_BASE & BRx_BA_MSK) |\ 397 BRx_PS_16 | BRx_MS_GPCM_L | BRx_V) 398 399#define CONFIG_SYS_OR4_PRELIM (0xfff80020) 400 401#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ 402 403/* pass open firmware flat tree */ 404#define CONFIG_OF_LIBFDT 1 405#define CONFIG_OF_BOARD_SETUP 1 406 407#define OF_CPU "PowerPC,8270@0" 408#define OF_SOC "soc@f0000000" 409#define OF_TBCLK (bd->bi_busfreq / 4) 410#if defined(CONFIG_MUAS_DEV_BOARD) 411#define OF_STDOUT_PATH "/soc/cpm/serial@11a90" 412#else 413#define OF_STDOUT_PATH "/soc/cpm/serial@11a80" 414#endif 415 416#endif /* __CONFIG_H */ 417