1/* 2 * (C) Copyright 2002 3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 4 * 5 * (C) Copyright 2002 6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 7 * Marius Groeger <mgroeger@sysgo.de> 8 * 9 * Configuation settings for the Zylonite board. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30#ifndef __CONFIG_H 31#define __CONFIG_H 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37#define CONFIG_CPU_MONAHANS 1 /* Intel Monahan CPU */ 38#define CONFIG_ZYLONITE 1 /* Zylonite board */ 39 40/* #define CONFIG_LCD 1 */ 41#ifdef CONFIG_LCD 42#define CONFIG_SHARP_LM8V31 43#endif 44/* #define CONFIG_MMC 1 */ 45#define BOARD_LATE_INIT 1 46 47#undef CONFIG_SKIP_RELOCATE_UBOOT 48#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 49 50/* 51 * Size of malloc() pool 52 */ 53#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 54#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 55 56/* 57 * Hardware drivers 58 */ 59 60#undef TURN_ON_ETHERNET 61#ifdef TURN_ON_ETHERNET 62# define CONFIG_DRIVER_SMC91111 1 63# define CONFIG_SMC91111_BASE 0x14000300 64# define CONFIG_SMC91111_EXT_PHY 65# define CONFIG_SMC_USE_32_BIT 66# undef CONFIG_SMC_USE_IOFUNCS /* just for use with the kernel */ 67#endif 68 69/* 70 * select serial console configuration 71 */ 72#define CONFIG_FFUART 1 73 74/* allow to overwrite serial and ethaddr */ 75#define CONFIG_ENV_OVERWRITE 76 77#define CONFIG_BAUDRATE 115200 78 79 80/* 81 * BOOTP options 82 */ 83#define CONFIG_BOOTP_BOOTFILESIZE 84#define CONFIG_BOOTP_BOOTPATH 85#define CONFIG_BOOTP_GATEWAY 86#define CONFIG_BOOTP_HOSTNAME 87 88 89/* 90 * Command line configuration. 91 */ 92#include <config_cmd_default.h> 93 94#ifdef TURN_ON_ETHERNET 95 #define CONFIG_CMD_PING 96#else 97 #define CONFIG_CMD_ENV 98 #define CONFIG_CMD_NAND 99 100 #undef CONFIG_CMD_NET 101 #undef CONFIG_CMD_FLASH 102 #undef CONFIG_CMD_IMLS 103#endif 104 105 106#define CONFIG_BOOTDELAY -1 107#define CONFIG_ETHADDR 08:00:3e:26:0a:5b 108#define CONFIG_NETMASK 255.255.0.0 109#define CONFIG_IPADDR 192.168.0.21 110#define CONFIG_SERVERIP 192.168.0.250 111#define CONFIG_BOOTCOMMAND "bootm 80000" 112#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" 113#define CONFIG_CMDLINE_TAG 114#define CONFIG_TIMESTAMP 115 116#if defined(CONFIG_CMD_KGDB) 117#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 118#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 119#endif 120 121/* 122 * Miscellaneous configurable options 123 */ 124#define CONFIG_SYS_HUSH_PARSER 1 125#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 126 127#define CONFIG_SYS_LONGHELP /* undef to save memory */ 128#ifdef CONFIG_SYS_HUSH_PARSER 129#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ 130#else 131#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 132#endif 133#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 134#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 135#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 136#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 137#define CONFIG_SYS_DEVICE_NULLDEV 1 138 139#define CONFIG_SYS_MEMTEST_START 0x9c000000 /* memtest works on */ 140#define CONFIG_SYS_MEMTEST_END 0x9c400000 /* 4 ... 8 MB in DRAM */ 141 142#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ 143 144#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DRAM_BASE + 0x8000) /* default load address */ 145 146#define CONFIG_SYS_HZ 3250000 /* incrementer freq: 3.25 MHz */ 147 148/* Monahans Core Frequency */ 149#define CONFIG_SYS_MONAHANS_RUN_MODE_OSC_RATIO 16 /* valid values: 8, 16, 24, 31 */ 150#define CONFIG_SYS_MONAHANS_TURBO_RUN_MODE_RATIO 1 /* valid values: 1, 2 */ 151 152 /* valid baudrates */ 153#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 154 155/* #define CONFIG_SYS_MMC_BASE 0xF0000000 */ 156 157/* 158 * Stack sizes 159 * 160 * The stack sizes are set up in start.S using the settings below 161 */ 162#define CONFIG_STACKSIZE (128*1024) /* regular stack */ 163#ifdef CONFIG_USE_IRQ 164#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ 165#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ 166#endif 167 168/* 169 * Physical Memory Map 170 */ 171#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ 172#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 173#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 174#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ 175#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ 176#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ 177#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ 178#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ 179#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ 180 181#define CONFIG_SYS_DRAM_BASE 0x80000000 /* at CS0 */ 182#define CONFIG_SYS_DRAM_SIZE 0x04000000 /* 64 MB Ram */ 183 184#undef CONFIG_SYS_SKIP_DRAM_SCRUB 185 186 187/* 188 * NAND Flash 189 */ 190#define CONFIG_NEW_NAND_CODE 191#define CONFIG_SYS_NAND0_BASE 0x0 192#undef CONFIG_SYS_NAND1_BASE 193 194#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE } 195#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 196 197/* nand timeout values */ 198#define CONFIG_SYS_NAND_PROG_ERASE_TO 3000 199#define CONFIG_SYS_NAND_OTHER_TO 100 200#define CONFIG_SYS_NAND_SENDCMD_RETRY 3 201#undef NAND_ALLOW_ERASE_ALL /* Allow erasing bad blocks - don't use */ 202 203/* NAND Timing Parameters (in ns) */ 204#define NAND_TIMING_tCH 10 205#define NAND_TIMING_tCS 0 206#define NAND_TIMING_tWH 20 207#define NAND_TIMING_tWP 40 208 209#define NAND_TIMING_tRH 20 210#define NAND_TIMING_tRP 40 211 212#define NAND_TIMING_tR 11123 213#define NAND_TIMING_tWHR 100 214#define NAND_TIMING_tAR 10 215 216/* NAND debugging */ 217#define CONFIG_SYS_DFC_DEBUG1 /* usefull */ 218#undef CONFIG_SYS_DFC_DEBUG2 /* noisy */ 219#undef CONFIG_SYS_DFC_DEBUG3 /* extremly noisy */ 220 221#define CONFIG_MTD_DEBUG 222#define CONFIG_MTD_DEBUG_VERBOSE 1 223 224#define ADDR_COLUMN 1 225#define ADDR_PAGE 2 226#define ADDR_COLUMN_PAGE 3 227 228#define NAND_ChipID_UNKNOWN 0x00 229#define NAND_MAX_FLOORS 1 230#define NAND_MAX_CHIPS 1 231 232#define CONFIG_SYS_NO_FLASH 1 233 234#define CONFIG_ENV_IS_IN_NAND 1 235#define CONFIG_ENV_OFFSET 0x40000 236#define CONFIG_ENV_OFFSET_REDUND 0x44000 237#define CONFIG_ENV_SIZE 0x4000 238 239 240#endif /* __CONFIG_H */ 241