LXR uboot/post/board/lwmon5/fpga.c

   1/*
   2 * (C) Copyright 2008 Dmitry Rakhchev, EmCraft Systems, rda@emcraft.com
   3 *
   4 * Developed for DENX Software Engineering GmbH
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 of
  12 * the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24#include <common.h>
  25
  26/* This test performs testing of FPGA SCRATCH register,
  27 * gets FPGA version and run get_ram_size() on FPGA memory
  28 */
  29
  30#include <post.h>
  31
  32#include <asm/io.h>
  33
  34DECLARE_GLOBAL_DATA_PTR;
  35
  36#define FPGA_SCRATCH_REG        0xC4000050
  37#define FPGA_VERSION_REG        0xC4000040
  38#define FPGA_RAM_START          0xC4200000
  39#define FPGA_RAM_END            0xC4203FFF
  40#define FPGA_STAT               0xC400000C
  41
  42#if CONFIG_POST & CONFIG_SYS_POST_BSPEC3
  43
  44/* Testpattern for fpga memorytest */
  45static uint pattern[] = {
  46        0x55555555,
  47        0xAAAAAAAA,
  48        0xAA5555AA,
  49        0x55AAAA55,
  50        0x0
  51};
  52
  53static int one_scratch_test(uint value)
  54{
  55        uint read_value;
  56        int ret = 0;
  57
  58        out_be32((void *)FPGA_SCRATCH_REG, value);
  59        /* read other location (protect against data lines capacity) */
  60        ret = in_be16((void *)FPGA_VERSION_REG);
  61        /* verify test pattern */
  62        read_value = in_be32((void *)FPGA_SCRATCH_REG);
  63        if (read_value != value) {
  64                post_log("FPGA SCRATCH test failed write %08X, read %08X\n",
  65                        value, read_value);
  66                ret = 1;
  67        }
  68
  69        return ret;
  70}
  71
  72/* FPGA Memory-pattern-test */
  73static int fpga_mem_test(void * address)
  74{
  75        int ret = 1;
  76        uint read_value;
  77        uint old_value;
  78        uint i = 0;
  79        /* save content */
  80        old_value = in_be32(address);
  81
  82        while (pattern[i] != 0) {
  83                out_be32(address, pattern[i]);
  84                /* read other location (protect against data lines capacity) */
  85                ret = in_be16((void *)FPGA_VERSION_REG);
  86                /* verify test pattern */
  87                read_value = in_be32(address);
  88
  89                if (read_value != pattern[i]) {
  90                        post_log("FPGA Memory test failed.");
  91                        post_log(" write %08X, read %08X at address %08X\n",
  92                                pattern[i], read_value, address);
  93                        ret = 1;
  94                        goto out;
  95                }
  96                i++;
  97        }
  98
  99        ret = 0;
 100out:
 101        out_be32(address, old_value);
 102        return ret;
 103}
 104/* Verify FPGA, get version & memory size */
 105int fpga_post_test(int flags)
 106{
 107        uint   address;
 108        uint   old_value;
 109        ushort version;
 110        uint   read_value;
 111        int    ret = 0;
 112
 113        post_log("\n");
 114        old_value = in_be32((void *)FPGA_SCRATCH_REG);
 115
 116        if (one_scratch_test(0x55555555))
 117                ret = 1;
 118        if (one_scratch_test(0xAAAAAAAA))
 119                ret = 1;
 120
 121        out_be32((void *)FPGA_SCRATCH_REG, old_value);
 122
 123        version = in_be16((void *)FPGA_VERSION_REG);
 124        post_log("FPGA : version %u.%u\n",
 125                (version >> 8) & 0xFF, version & 0xFF);
 126
 127        /* Enable write to FPGA RAM */
 128        out_be32((void *)FPGA_STAT, in_be32((void *)FPGA_STAT) | 0x1000);
 129
 130        read_value = get_ram_size((void *)CONFIG_SYS_FPGA_BASE_1, 0x4000);
 131        post_log("FPGA RAM size: %d bytes\n", read_value);
 132
 133        for (address = 0; address < 0x1000; address++) {
 134                if (fpga_mem_test((void *)(FPGA_RAM_START + 4*address)) == 1) {
 135                        ret = 1;
 136                        goto out;
 137                }
 138        }
 139
 140out:
 141        return ret;
 142}
 143
 144#endif /* CONFIG_POST & CONFIG_SYS_POST_BSPEC3 */
 145