LXR uboot/board/assabet/assabet.c

   1/*
   2 * (C) Copyright 2002
   3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
   4 * Marius Groeger <mgroeger@sysgo.de>
   5 *
   6 * 2004 (c) MontaVista Software, Inc.
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27#include <common.h>
  28#include <SA-1100.h>
  29
  30DECLARE_GLOBAL_DATA_PTR;
  31
  32/* ------------------------------------------------------------------------- */
  33
  34/*
  35 * Board dependent initialisation
  36 */
  37
  38#define ECOR                    0x8000
  39#define ECOR_RESET              0x80
  40#define ECOR_LEVEL_IRQ          0x40
  41#define ECOR_WR_ATTRIB          0x04
  42#define ECOR_ENABLE             0x01
  43
  44#define ECSR                    0x8002
  45#define ECSR_IOIS8              0x20
  46#define ECSR_PWRDWN             0x04
  47#define ECSR_INT                0x02
  48#define SMC_IO_SHIFT            2
  49#define NCR_0                   (*((volatile u_char *)(0x100000a0)))
  50#define NCR_ENET_OSC_EN         (1<<3)
  51
  52static inline u8
  53readb(volatile u8 * p)
  54{
  55        return *p;
  56}
  57
  58static inline void
  59writeb(u8 v, volatile u8 * p)
  60{
  61        *p = v;
  62}
  63
  64static void
  65smc_init(void)
  66{
  67        u8 ecor;
  68        u8 ecsr;
  69        volatile u8 *addr = (volatile u8 *)(0x18000000 + (1 << 25));
  70
  71        NCR_0 |= NCR_ENET_OSC_EN;
  72        udelay(100);
  73
  74        ecor = readb(addr + (ECOR << SMC_IO_SHIFT)) & ~ECOR_RESET;
  75        writeb(ecor | ECOR_RESET, addr + (ECOR << SMC_IO_SHIFT));
  76        udelay(100);
  77
  78        /*
  79         * The device will ignore all writes to the enable bit while
  80         * reset is asserted, even if the reset bit is cleared in the
  81         * same write.  Must clear reset first, then enable the device.
  82         */
  83        writeb(ecor, addr + (ECOR << SMC_IO_SHIFT));
  84        writeb(ecor | ECOR_ENABLE, addr + (ECOR << SMC_IO_SHIFT));
  85
  86        /*
  87         * Set the appropriate byte/word mode.
  88         */
  89        ecsr = readb(addr + (ECSR << SMC_IO_SHIFT)) & ~ECSR_IOIS8;
  90        ecsr |= ECSR_IOIS8;
  91        writeb(ecsr, addr + (ECSR << SMC_IO_SHIFT));
  92        udelay(100);
  93}
  94
  95static void
  96neponset_init(void)
  97{
  98        smc_init();
  99}
 100
 101int
 102board_init(void)
 103{
 104        gd->bd->bi_arch_number = MACH_TYPE_ASSABET;
 105        gd->bd->bi_boot_params = 0xc0000100;
 106
 107        neponset_init();
 108
 109        return 0;
 110}
 111
 112int
 113dram_init(void)
 114{
 115        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
 116        gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
 117
 118        return (0);
 119}
 120