LXR uboot/board/atmel/at91sam9261ek/at91sam9261ek.c

   1/*
   2 * (C) Copyright 2007-2008
   3 * Stelian Pop <stelian.pop@leadtechdesign.com>
   4 * Lead Tech Design <www.leadtechdesign.com>
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation; either version 2 of
  12 * the License, or (at your option) any later version.
  13 *
  14 * This program is distributed in the hope that it will be useful,
  15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 * GNU General Public License for more details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this program; if not, write to the Free Software
  21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22 * MA 02111-1307 USA
  23 */
  24
  25#include <common.h>
  26#include <asm/arch/at91sam9261.h>
  27#include <asm/arch/at91sam9261_matrix.h>
  28#include <asm/arch/at91sam9_smc.h>
  29#include <asm/arch/at91_pmc.h>
  30#include <asm/arch/at91_rstc.h>
  31#include <asm/arch/gpio.h>
  32#include <asm/arch/io.h>
  33#include <lcd.h>
  34#include <atmel_lcdc.h>
  35#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_DRIVER_DM9000)
  36#include <net.h>
  37#endif
  38
  39DECLARE_GLOBAL_DATA_PTR;
  40
  41/* ------------------------------------------------------------------------- */
  42/*
  43 * Miscelaneous platform dependent initialisations
  44 */
  45
  46static void at91sam9261ek_serial_hw_init(void)
  47{
  48#ifdef CONFIG_USART0
  49        at91_set_A_periph(AT91_PIN_PC8, 1);             /* TXD0 */
  50        at91_set_A_periph(AT91_PIN_PC9, 0);             /* RXD0 */
  51        at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US0);
  52#endif
  53
  54#ifdef CONFIG_USART1
  55        at91_set_A_periph(AT91_PIN_PC12, 1);            /* TXD1 */
  56        at91_set_A_periph(AT91_PIN_PC13, 0);            /* RXD1 */
  57        at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US1);
  58#endif
  59
  60#ifdef CONFIG_USART2
  61        at91_set_A_periph(AT91_PIN_PC14, 1);            /* TXD2 */
  62        at91_set_A_periph(AT91_PIN_PC15, 0);            /* RXD2 */
  63        at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_US2);
  64#endif
  65
  66#ifdef CONFIG_USART3    /* DBGU */
  67        at91_set_A_periph(AT91_PIN_PA9, 0);             /* DRXD */
  68        at91_set_A_periph(AT91_PIN_PA10, 1);            /* DTXD */
  69        at91_sys_write(AT91_PMC_PCER, 1 << AT91_ID_SYS);
  70#endif
  71}
  72
  73#ifdef CONFIG_CMD_NAND
  74static void at91sam9261ek_nand_hw_init(void)
  75{
  76        unsigned long csa;
  77
  78        /* Enable CS3 */
  79        csa = at91_sys_read(AT91_MATRIX_EBICSA);
  80        at91_sys_write(AT91_MATRIX_EBICSA,
  81                       csa | AT91_MATRIX_CS3A_SMC_SMARTMEDIA);
  82
  83        /* Configure SMC CS3 for NAND/SmartMedia */
  84        at91_sys_write(AT91_SMC_SETUP(3),
  85                       AT91_SMC_NWESETUP_(1) | AT91_SMC_NCS_WRSETUP_(0) |
  86                       AT91_SMC_NRDSETUP_(1) | AT91_SMC_NCS_RDSETUP_(0));
  87        at91_sys_write(AT91_SMC_PULSE(3),
  88                       AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3) |
  89                       AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  90        at91_sys_write(AT91_SMC_CYCLE(3),
  91                       AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  92        at91_sys_write(AT91_SMC_MODE(3),
  93                       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
  94                       AT91_SMC_EXNWMODE_DISABLE |
  95#ifdef CONFIG_SYS_NAND_DBW_16
  96                       AT91_SMC_DBW_16 |
  97#else /* CONFIG_SYS_NAND_DBW_8 */
  98                       AT91_SMC_DBW_8 |
  99#endif
 100                       AT91_SMC_TDF_(2));
 101
 102        at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_PIOC);
 103
 104        /* Configure RDY/BSY */
 105        at91_set_gpio_input(AT91_PIN_PC15, 1);
 106
 107        /* Enable NandFlash */
 108        at91_set_gpio_output(AT91_PIN_PC14, 1);
 109
 110        at91_set_A_periph(AT91_PIN_PC0, 0);     /* NANDOE */
 111        at91_set_A_periph(AT91_PIN_PC1, 0);     /* NANDWE */
 112}
 113#endif
 114
 115#ifdef CONFIG_HAS_DATAFLASH
 116static void at91sam9261ek_spi_hw_init(void)
 117{
 118        at91_set_A_periph(AT91_PIN_PA3, 0);     /* SPI0_NPCS0 */
 119
 120        at91_set_A_periph(AT91_PIN_PA0, 0);     /* SPI0_MISO */
 121        at91_set_A_periph(AT91_PIN_PA1, 0);     /* SPI0_MOSI */
 122        at91_set_A_periph(AT91_PIN_PA2, 0);     /* SPI0_SPCK */
 123
 124        /* Enable clock */
 125        at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9261_ID_SPI0);
 126}
 127#endif
 128
 129#ifdef CONFIG_DRIVER_DM9000
 130static void at91sam9261ek_dm9000_hw_init(void)
 131{
 132        /* Configure SMC CS2 for DM9000 */
 133        at91_sys_write(AT91_SMC_SETUP(2),
 134                       AT91_SMC_NWESETUP_(2) | AT91_SMC_NCS_WRSETUP_(0) |
 135                       AT91_SMC_NRDSETUP_(2) | AT91_SMC_NCS_RDSETUP_(0));
 136        at91_sys_write(AT91_SMC_PULSE(2),
 137                       AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(8) |
 138                       AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(8));
 139        at91_sys_write(AT91_SMC_CYCLE(2),
 140                       AT91_SMC_NWECYCLE_(16) | AT91_SMC_NRDCYCLE_(16));
 141        at91_sys_write(AT91_SMC_MODE(2),
 142                       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
 143                       AT91_SMC_EXNWMODE_DISABLE |
 144                       AT91_SMC_BAT_WRITE | AT91_SMC_DBW_16 |
 145                       AT91_SMC_TDF_(1));
 146
 147        /* Configure Reset signal as output */
 148        at91_set_gpio_output(AT91_PIN_PC10, 0);
 149
 150        /* Configure Interrupt pin as input, no pull-up */
 151        at91_set_gpio_input(AT91_PIN_PC11, 0);
 152}
 153#endif
 154
 155#ifdef CONFIG_LCD
 156vidinfo_t panel_info = {
 157        vl_col:         240,
 158        vl_row:         320,
 159        vl_clk:         4965000,
 160        vl_sync:        ATMEL_LCDC_INVLINE_INVERTED |
 161                        ATMEL_LCDC_INVFRAME_INVERTED,
 162        vl_bpix:        3,
 163        vl_tft:         1,
 164        vl_hsync_len:   5,
 165        vl_left_margin: 1,
 166        vl_right_margin:33,
 167        vl_vsync_len:   1,
 168        vl_upper_margin:1,
 169        vl_lower_margin:0,
 170        mmio:           AT91SAM9261_LCDC_BASE,
 171};
 172
 173void lcd_enable(void)
 174{
 175        at91_set_gpio_value(AT91_PIN_PA12, 0);  /* power up */
 176}
 177
 178void lcd_disable(void)
 179{
 180        at91_set_gpio_value(AT91_PIN_PA12, 1);  /* power down */
 181}
 182
 183static void at91sam9261ek_lcd_hw_init(void)
 184{
 185        at91_set_A_periph(AT91_PIN_PB1, 0);     /* LCDHSYNC */
 186        at91_set_A_periph(AT91_PIN_PB2, 0);     /* LCDDOTCK */
 187        at91_set_A_periph(AT91_PIN_PB3, 0);     /* LCDDEN */
 188        at91_set_A_periph(AT91_PIN_PB4, 0);     /* LCDCC */
 189        at91_set_A_periph(AT91_PIN_PB7, 0);     /* LCDD2 */
 190        at91_set_A_periph(AT91_PIN_PB8, 0);     /* LCDD3 */
 191        at91_set_A_periph(AT91_PIN_PB9, 0);     /* LCDD4 */
 192        at91_set_A_periph(AT91_PIN_PB10, 0);    /* LCDD5 */
 193        at91_set_A_periph(AT91_PIN_PB11, 0);    /* LCDD6 */
 194        at91_set_A_periph(AT91_PIN_PB12, 0);    /* LCDD7 */
 195        at91_set_A_periph(AT91_PIN_PB15, 0);    /* LCDD10 */
 196        at91_set_A_periph(AT91_PIN_PB16, 0);    /* LCDD11 */
 197        at91_set_A_periph(AT91_PIN_PB17, 0);    /* LCDD12 */
 198        at91_set_A_periph(AT91_PIN_PB18, 0);    /* LCDD13 */
 199        at91_set_A_periph(AT91_PIN_PB19, 0);    /* LCDD14 */
 200        at91_set_A_periph(AT91_PIN_PB20, 0);    /* LCDD15 */
 201        at91_set_B_periph(AT91_PIN_PB23, 0);    /* LCDD18 */
 202        at91_set_B_periph(AT91_PIN_PB24, 0);    /* LCDD19 */
 203        at91_set_B_periph(AT91_PIN_PB25, 0);    /* LCDD20 */
 204        at91_set_B_periph(AT91_PIN_PB26, 0);    /* LCDD21 */
 205        at91_set_B_periph(AT91_PIN_PB27, 0);    /* LCDD22 */
 206        at91_set_B_periph(AT91_PIN_PB28, 0);    /* LCDD23 */
 207
 208        at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1);
 209
 210        gd->fb_base = AT91SAM9261_SRAM_BASE;
 211}
 212
 213#ifdef CONFIG_LCD_INFO
 214#include <nand.h>
 215#include <version.h>
 216
 217void lcd_show_board_info(void)
 218{
 219        ulong dram_size, nand_size;
 220        int i;
 221        char temp[32];
 222
 223        lcd_printf ("%s\n", U_BOOT_VERSION);
 224        lcd_printf ("(C) 2008 ATMEL Corp\n");
 225        lcd_printf ("at91support@atmel.com\n");
 226        lcd_printf ("%s CPU at %s MHz\n",
 227                AT91_CPU_NAME,
 228                strmhz(temp, AT91_CPU_CLOCK));
 229
 230        dram_size = 0;
 231        for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 232                dram_size += gd->bd->bi_dram[i].size;
 233        nand_size = 0;
 234        for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 235                nand_size += nand_info[i].size;
 236        lcd_printf ("  %ld MB SDRAM, %ld MB NAND\n",
 237                dram_size >> 20,
 238                nand_size >> 20 );
 239}
 240#endif /* CONFIG_LCD_INFO */
 241#endif
 242
 243int board_init(void)
 244{
 245        /* Enable Ctrlc */
 246        console_init_f();
 247
 248        /* arch number of AT91SAM9261EK-Board */
 249        gd->bd->bi_arch_number = MACH_TYPE_AT91SAM9261EK;
 250        /* adress of boot parameters */
 251        gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 252
 253        at91sam9261ek_serial_hw_init();
 254#ifdef CONFIG_CMD_NAND
 255        at91sam9261ek_nand_hw_init();
 256#endif
 257#ifdef CONFIG_HAS_DATAFLASH
 258        at91sam9261ek_spi_hw_init();
 259#endif
 260#ifdef CONFIG_DRIVER_DM9000
 261        at91sam9261ek_dm9000_hw_init();
 262#endif
 263#ifdef CONFIG_LCD
 264        at91sam9261ek_lcd_hw_init();
 265#endif
 266        return 0;
 267}
 268
 269int dram_init(void)
 270{
 271        gd->bd->bi_dram[0].start = PHYS_SDRAM;
 272        gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
 273        return 0;
 274}
 275
 276#ifdef CONFIG_RESET_PHY_R
 277void reset_phy(void)
 278{
 279#ifdef CONFIG_DRIVER_DM9000
 280        /*
 281         * Initialize ethernet HW addr prior to starting Linux,
 282         * needed for nfsroot
 283         */
 284        eth_init(gd->bd);
 285#endif
 286}
 287#endif
 288