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27#include <common.h>
28#include <asm/processor.h>
29#include <asm/io.h>
30#include <command.h>
31#include <malloc.h>
32#include <flash.h>
33#include <asm/4xx_pci.h>
34#include <pci.h>
35
36DECLARE_GLOBAL_DATA_PTR;
37
38#undef FPGA_DEBUG
39
40extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]);
41extern void lxt971_no_sleep(void);
42extern ulong flash_get_size (ulong base, int banknum);
43
44int flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT;
45
46
47const unsigned char fpgadata[] =
48{
49#include "fpgadata.c"
50};
51
52
53
54
55#include "../common/fpga.c"
56
57
58int gunzip(void *, int, unsigned char *, unsigned long *);
59
60#ifdef CONFIG_LCD_USED
61
62unsigned char logo_bmp[] =
63{
64#include "logo_640_480_24bpp.c"
65};
66
67
68
69
70#include "../common/lcd.c"
71#include "../common/s1d13505_640_480_16bpp.h"
72#include "../common/s1d13806_640_480_16bpp.h"
73#endif
74
75
76
77
78#include "../common/auto_update.h"
79
80au_image_t au_image[] = {
81 {"preinst.img", 0, -1, AU_SCRIPT},
82 {"u-boot.img", 0xfff80000, 0x00080000, AU_FIRMWARE | AU_PROTECT},
83 {"pImage", 0xfe000000, 0x00100000, AU_NOR | AU_PROTECT},
84 {"pImage.initrd", 0xfe100000, 0x00400000, AU_NOR | AU_PROTECT},
85 {"work.img", 0xfe500000, 0x01400000, AU_NOR},
86 {"data.img", 0xff900000, 0x00580000, AU_NOR},
87 {"logo.img", 0xffe80000, 0x00100000, AU_NOR | AU_PROTECT},
88 {"postinst.img", 0, 0, AU_SCRIPT},
89};
90
91int N_AU_IMAGES = (sizeof(au_image) / sizeof(au_image[0]));
92
93int board_revision(void)
94{
95 unsigned long cntrl0Reg;
96 volatile unsigned long value;
97
98
99
100
101
102
103 cntrl0Reg = mfdcr(cntrl0);
104 mtdcr(cntrl0, cntrl0Reg | 0x03800000);
105 out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x001c0000);
106 out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x001c0000);
107
108
109 udelay(1000);
110
111
112 value = in_be32((void*)GPIO0_IR) & 0x001c0000;
113
114
115
116 mtdcr(cntrl0, cntrl0Reg);
117
118 switch (value) {
119 case 0x001c0000:
120
121 return 2;
122 case 0x000c0000:
123
124 return 3;
125 case 0x00180000:
126
127 return 6;
128 case 0x00140000:
129
130 return 8;
131 default:
132
133 return 0;
134 }
135}
136
137int board_early_init_f (void)
138{
139
140
141
142 out_be32((void*)GPIO0_ODR, 0x00000000);
143 out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG);
144 out_be32((void*)GPIO0_OR, 0);
145
146
147
148
149
150
151
152
153
154
155
156
157
158 mtdcr(uicsr, 0xFFFFFFFF);
159 mtdcr(uicer, 0x00000000);
160 mtdcr(uiccr, 0x00000000);
161 mtdcr(uicpr, 0xFFFFFF81);
162 mtdcr(uictr, 0x10000000);
163 mtdcr(uicvcr, 0x00000001);
164 mtdcr(uicsr, 0xFFFFFFFF);
165
166
167
168
169 mtebc(epcr, 0xa8400000);
170
171
172
173
174
175 if (board_revision() >= 8) {
176
177 mtebc(pb1ap, 0);
178 mtebc(pb1cr, 0);
179
180
181 mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP_HWREV8);
182 mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR_HWREV8);
183 }
184
185 return 0;
186}
187
188int board_early_init_r(void)
189{
190 if (gd->board_type >= 8)
191 flash_banks = 1;
192
193 return 0;
194}
195
196#define FUJI_BASE 0xf0100200
197#define LCDBL_PWM 0xa0
198#define LCDBL_PWMMIN 0xa4
199#define LCDBL_PWMMAX 0xa8
200
201int misc_init_r(void)
202{
203 u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
204 u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
205 u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
206 u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
207 unsigned char *dst;
208 ulong len = sizeof(fpgadata);
209 int status;
210 int index;
211 int i;
212 unsigned long cntrl0Reg;
213 char *str;
214 uchar *logo_addr;
215 ulong logo_size;
216 ushort minb, maxb;
217 int result;
218
219
220
221
222 cntrl0Reg = mfdcr(cntrl0);
223 mtdcr(cntrl0, cntrl0Reg | 0x00300000);
224
225 dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
226 if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
227 printf("GUNZIP ERROR - must RESET board to recover\n");
228 do_reset(NULL, 0, 0, NULL);
229 }
230
231 status = fpga_boot(dst, len);
232 if (status != 0) {
233 printf("\nFPGA: Booting failed ");
234 switch (status) {
235 case ERROR_FPGA_PRG_INIT_LOW:
236 printf("(Timeout: "
237 "INIT not low after asserting PROGRAM*)\n ");
238 break;
239 case ERROR_FPGA_PRG_INIT_HIGH:
240 printf("(Timeout: "
241 "INIT not high after deasserting PROGRAM*)\n ");
242 break;
243 case ERROR_FPGA_PRG_DONE:
244 printf("(Timeout: "
245 "DONE not high after programming FPGA)\n ");
246 break;
247 }
248
249
250 index = 15;
251 for (i = 0; i < 4; i++) {
252 len = dst[index];
253 printf("FPGA: %s\n", &(dst[index+1]));
254 index += len + 3;
255 }
256 putc('\n');
257
258 for (i = 20; i > 0; i--) {
259 printf("Rebooting in %2d seconds \r",i);
260 for (index = 0; index < 1000; index++)
261 udelay(1000);
262 }
263 putc('\n');
264 do_reset(NULL, 0, 0, NULL);
265 }
266
267
268 mtdcr(cntrl0, cntrl0Reg);
269
270 puts("FPGA: ");
271
272
273 index = 15;
274 for (i = 0; i < 4; i++) {
275 len = dst[index];
276 printf("%s ", &(dst[index + 1]));
277 index += len + 3;
278 }
279 putc('\n');
280
281 free(dst);
282
283
284
285
286 SET_FPGA(FPGA_PRG | FPGA_CLK);
287 udelay(1000);
288 SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
289 udelay(1000);
290
291
292
293
294 out_be16(fpga_ctrl2,
295 (in_be16(fpga_ctrl2) & 0xfff0) | (gd->board_type & 0x000f));
296
297
298
299
300 out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
301 for (i=0;i<100;i++)
302 udelay(1000);
303 udelay(1000);
304 out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
305
306
307
308
309 out_8(duart0_mcr, 0x08);
310 out_8(duart1_mcr, 0x08);
311
312
313
314
315 str = getenv("splashimage");
316 if (str) {
317 logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
318 logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
319 } else {
320 logo_addr = logo_bmp;
321 logo_size = sizeof(logo_bmp);
322 }
323
324 if (gd->board_type >= 6) {
325 result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
326 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
327 regs_13505_640_480_16bpp,
328 sizeof(regs_13505_640_480_16bpp) /
329 sizeof(regs_13505_640_480_16bpp[0]),
330 logo_addr, logo_size);
331 if (result && str) {
332
333 logo_addr = logo_bmp;
334 logo_size = sizeof(logo_bmp);
335 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
336 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
337 regs_13505_640_480_16bpp,
338 sizeof(regs_13505_640_480_16bpp) /
339 sizeof(regs_13505_640_480_16bpp[0]),
340 logo_addr, logo_size);
341 }
342 } else {
343 result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
344 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
345 regs_13806_640_480_16bpp,
346 sizeof(regs_13806_640_480_16bpp) /
347 sizeof(regs_13806_640_480_16bpp[0]),
348 logo_addr, logo_size);
349 if (result && str) {
350
351 logo_addr = logo_bmp;
352 logo_size = sizeof(logo_bmp);
353 lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
354 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
355 regs_13806_640_480_16bpp,
356 sizeof(regs_13806_640_480_16bpp) /
357 sizeof(regs_13806_640_480_16bpp[0]),
358 logo_addr, logo_size);
359 }
360 }
361
362
363
364
365 out_be16(fpga_mode, in_be16(fpga_mode) | 0x0014);
366 for (i=0;i<10;i++)
367 udelay(1000);
368 out_be16(fpga_mode, in_be16(fpga_mode) | 0x001c);
369
370 minb = 0;
371 maxb = 0xff;
372 str = getenv("lcdbl");
373 if (str) {
374 minb = (ushort)simple_strtoul(str, &str, 16) & 0x00ff;
375 if (str && (*str=',')) {
376 str++;
377 maxb = (ushort)simple_strtoul(str, NULL, 16) & 0x00ff;
378 } else
379 minb = 0;
380
381 out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMIN), minb);
382 out_be16((u16 *)(FUJI_BASE + LCDBL_PWMMAX), maxb);
383
384 printf("LCDBL: min=0x%02x, max=0x%02x\n", minb, maxb);
385 }
386 out_be16((u16 *)(FUJI_BASE + LCDBL_PWM), 0xff);
387
388
389
390
391 if (getenv("altbootcmd") == NULL) {
392 setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
393 setenv("usbargs", CONFIG_SYS_USB_ARGS);
394 setenv("bootcmd", CONFIG_BOOTCOMMAND);
395 setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
396 setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
397 setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
398 saveenv();
399 }
400
401 return (0);
402}
403
404
405
406
407int checkboard (void)
408{
409 char str[64];
410 int i = getenv_r ("serial#", str, sizeof(str));
411
412 puts ("Board: ");
413
414 if (i == -1) {
415 puts ("### No HW ID - assuming APC405");
416 } else {
417 puts(str);
418 }
419
420 gd->board_type = board_revision();
421 printf(", Rev. 1.%ld\n", gd->board_type);
422
423 return 0;
424}
425
426#ifdef CONFIG_IDE_RESET
427void ide_set_reset(int on)
428{
429 u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
430
431
432
433
434 if (on) {
435 out_be16(fpga_mode,
436 in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
437 } else {
438 out_be16(fpga_mode,
439 in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
440 }
441}
442#endif
443
444void reset_phy(void)
445{
446
447
448
449 lxt971_no_sleep();
450}
451
452#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
453int usb_board_init(void)
454{
455 return 0;
456}
457
458int usb_board_stop(void)
459{
460 unsigned short tmp;
461 int i;
462
463
464
465
466
467
468 pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &tmp);
469 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (tmp | 0x1000));
470
471 for (i = 0; i < 100; i++)
472 udelay(1000);
473
474 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, tmp);
475 return 0;
476}
477
478int usb_board_init_fail(void)
479{
480 usb_board_stop();
481 return 0;
482}
483#endif
484