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27#include <common.h>
28#include <asm/immap.h>
29
30int checkboard(void)
31{
32 puts("Board: ");
33 puts("Freescale MCF5253 EVBE\n");
34 return 0;
35};
36
37phys_size_t initdram(int board_type)
38{
39
40
41
42
43 if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
44 u32 RC, dramsize;
45
46 RC = (CONFIG_SYS_CLK / 1000000) >> 1;
47 RC = (RC * 15) >> 4;
48
49
50 mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
51 asm("nop");
52
53 mbar_writeLong(MCFSIM_DACR0, 0x00002320);
54 asm("nop");
55
56
57 dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
58 mbar_writeLong(MCFSIM_DMR0, dramsize | 1);
59 asm("nop");
60
61 mbar_writeLong(MCFSIM_DACR0, 0x00002328);
62 asm("nop");
63
64
65 *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
66 asm("nop");
67
68
69 mbar_writeLong(MCFSIM_DACR0,
70 mbar_readLong(MCFSIM_DACR0) | 0x8000);
71 asm("nop");
72
73
74 udelay(500);
75
76
77 mbar_writeLong(MCFSIM_DACR0,
78 mbar_readLong(MCFSIM_DACR0) | 0x0040);
79 asm("nop");
80
81 *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
82 }
83
84 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
85}
86
87int testdram(void)
88{
89
90 printf("DRAM test not implemented!\n");
91
92 return (0);
93}
94
95#ifdef CONFIG_CMD_IDE
96#include <ata.h>
97int ide_preinit(void)
98{
99 return (0);
100}
101
102void ide_set_reset(int idereset)
103{
104 volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
105 long period;
106
107 int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},
108 {50, 125, 45, 20, 35, 5, 15, 0, 35},
109 {30, 100, 30, 15, 20, 5, 10, 0, 35},
110 {30, 80, 30, 10, 20, 5, 10, 0, 35},
111 {25, 70, 20, 10, 20, 5, 10, 0, 35}
112 };
113
114 if (idereset) {
115 ata->cr = 0;
116 udelay(100);
117 } else {
118 mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
119
120#define CALC_TIMING(t) (t + period - 1) / period
121 period = 1000000000 / (CONFIG_SYS_CLK / 2);
122
123
124 ata->t1 = CALC_TIMING(piotms[2][0]);
125 ata->t2w = CALC_TIMING(piotms[2][1]);
126 ata->t2r = CALC_TIMING(piotms[2][1]);
127 ata->ta = CALC_TIMING(piotms[2][8]);
128 ata->trd = CALC_TIMING(piotms[2][7]);
129 ata->t4 = CALC_TIMING(piotms[2][3]);
130 ata->t9 = CALC_TIMING(piotms[2][6]);
131
132 ata->cr = 0x40;
133 udelay(2000);
134 ata->cr |= 0x01;
135 }
136}
137#endif
138