LXR uboot/board/freescale/mpc8560ads/mpc8560ads.c

   1/*
   2 * Copyright 2004 Freescale Semiconductor.
   3 * (C) Copyright 2003,Motorola Inc.
   4 * Xianghua Xiao, (X.Xiao@motorola.com)
   5 *
   6 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27
  28#include <common.h>
  29#include <pci.h>
  30#include <asm/processor.h>
  31#include <asm/mmu.h>
  32#include <asm/immap_85xx.h>
  33#include <asm/fsl_ddr_sdram.h>
  34#include <ioports.h>
  35#include <spd_sdram.h>
  36#include <miiphy.h>
  37#include <libfdt.h>
  38#include <fdt_support.h>
  39
  40#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  41extern void ddr_enable_ecc(unsigned int dram_size);
  42#endif
  43
  44
  45void local_bus_init(void);
  46void sdram_init(void);
  47long int fixed_sdram(void);
  48
  49
  50/*
  51 * I/O Port configuration table
  52 *
  53 * if conf is 1, then that port pin will be configured at boot time
  54 * according to the five values podr/pdir/ppar/psor/pdat for that entry
  55 */
  56
  57const iop_conf_t iop_conf_tab[4][32] = {
  58
  59    /* Port A configuration */
  60    {   /*            conf ppar psor pdir podr pdat */
  61        /* PA31 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxENB */
  62        /* PA30 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 TxClav   */
  63        /* PA29 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 TxSOC  */
  64        /* PA28 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 RxENB */
  65        /* PA27 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxSOC */
  66        /* PA26 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 RxClav */
  67        /* PA25 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[0] */
  68        /* PA24 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[1] */
  69        /* PA23 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[2] */
  70        /* PA22 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[3] */
  71        /* PA21 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[4] */
  72        /* PA20 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[5] */
  73        /* PA19 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[6] */
  74        /* PA18 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXD[7] */
  75        /* PA17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[7] */
  76        /* PA16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[6] */
  77        /* PA15 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[5] */
  78        /* PA14 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[4] */
  79        /* PA13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[3] */
  80        /* PA12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[2] */
  81        /* PA11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[1] */
  82        /* PA10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXD[0] */
  83        /* PA9  */ {   0,   1,   1,   1,   0,   0   }, /* FCC1 L1TXD */
  84        /* PA8  */ {   0,   1,   1,   0,   0,   0   }, /* FCC1 L1RXD */
  85        /* PA7  */ {   0,   0,   0,   1,   0,   0   }, /* PA7 */
  86        /* PA6  */ {   0,   1,   1,   1,   0,   0   }, /* TDM A1 L1RSYNC */
  87        /* PA5  */ {   0,   0,   0,   1,   0,   0   }, /* PA5 */
  88        /* PA4  */ {   0,   0,   0,   1,   0,   0   }, /* PA4 */
  89        /* PA3  */ {   0,   0,   0,   1,   0,   0   }, /* PA3 */
  90        /* PA2  */ {   0,   0,   0,   1,   0,   0   }, /* PA2 */
  91        /* PA1  */ {   1,   0,   0,   0,   0,   0   }, /* FREERUN */
  92        /* PA0  */ {   0,   0,   0,   1,   0,   0   }  /* PA0 */
  93    },
  94
  95    /* Port B configuration */
  96    {   /*            conf ppar psor pdir podr pdat */
  97        /* PB31 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TX_ER */
  98        /* PB30 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_DV */
  99        /* PB29 */ {   1,   1,   1,   1,   0,   0   }, /* FCC2 MII TX_EN */
 100        /* PB28 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_ER */
 101        /* PB27 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII COL */
 102        /* PB26 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII CRS */
 103        /* PB25 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[3] */
 104        /* PB24 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[2] */
 105        /* PB23 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[1] */
 106        /* PB22 */ {   1,   1,   0,   1,   0,   0   }, /* FCC2 MII TxD[0] */
 107        /* PB21 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[0] */
 108        /* PB20 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[1] */
 109        /* PB19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[2] */
 110        /* PB18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RxD[3] */
 111        /* PB17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_DIV */
 112        /* PB16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RX_ERR */
 113        /* PB15 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_ERR */
 114        /* PB14 */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TX_EN */
 115        /* PB13 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:COL */
 116        /* PB12 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:CRS */
 117        /* PB11 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 118        /* PB10 */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 119        /* PB9  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 120        /* PB8  */ {   0,   1,   0,   0,   0,   0   }, /* FCC3:RXD */
 121        /* PB7  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 122        /* PB6  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 123        /* PB5  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 124        /* PB4  */ {   0,   1,   0,   1,   0,   0   }, /* FCC3:TXD */
 125        /* PB3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 126        /* PB2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 127        /* PB1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 128        /* PB0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 129    },
 130
 131    /* Port C */
 132    {   /*            conf ppar psor pdir podr pdat */
 133        /* PC31 */ {   0,   0,   0,   1,   0,   0   }, /* PC31 */
 134        /* PC30 */ {   0,   0,   0,   1,   0,   0   }, /* PC30 */
 135        /* PC29 */ {   0,   1,   1,   0,   0,   0   }, /* SCC1 EN *CLSN */
 136        /* PC28 */ {   0,   0,   0,   1,   0,   0   }, /* PC28 */
 137        /* PC27 */ {   0,   0,   0,   1,   0,   0   }, /* UART Clock in */
 138        /* PC26 */ {   0,   0,   0,   1,   0,   0   }, /* PC26 */
 139        /* PC25 */ {   0,   0,   0,   1,   0,   0   }, /* PC25 */
 140        /* PC24 */ {   0,   0,   0,   1,   0,   0   }, /* PC24 */
 141        /* PC23 */ {   0,   1,   0,   1,   0,   0   }, /* ATMTFCLK */
 142        /* PC22 */ {   0,   1,   0,   0,   0,   0   }, /* ATMRFCLK */
 143        /* PC21 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN RXCLK */
 144        /* PC20 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN TXCLK */
 145        /* PC19 */ {   1,   1,   0,   0,   0,   0   }, /* FCC2 MII RX_CLK CLK13 */
 146        /* PC18 */ {   1,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK14) */
 147        /* PC17 */ {   0,   0,   0,   1,   0,   0   }, /* PC17 */
 148        /* PC16 */ {   0,   1,   0,   0,   0,   0   }, /* FCC Tx Clock (CLK16) */
 149        /* PC15 */ {   1,   1,   0,   0,   0,   0   }, /* PC15 */
 150        /* PC14 */ {   0,   1,   0,   0,   0,   0   }, /* SCC1 EN *CD */
 151        /* PC13 */ {   0,   0,   0,   1,   0,   0   }, /* PC13 */
 152        /* PC12 */ {   0,   1,   0,   1,   0,   0   }, /* PC12 */
 153        /* PC11 */ {   0,   0,   0,   1,   0,   0   }, /* LXT971 transmit control */
 154        /* PC10 */ {   1,   0,   0,   1,   0,   0   }, /* FETHMDC */
 155        /* PC9  */ {   1,   0,   0,   0,   0,   0   }, /* FETHMDIO */
 156        /* PC8  */ {   0,   0,   0,   1,   0,   0   }, /* PC8 */
 157        /* PC7  */ {   0,   0,   0,   1,   0,   0   }, /* PC7 */
 158        /* PC6  */ {   0,   0,   0,   1,   0,   0   }, /* PC6 */
 159        /* PC5  */ {   0,   0,   0,   1,   0,   0   }, /* PC5 */
 160        /* PC4  */ {   0,   0,   0,   1,   0,   0   }, /* PC4 */
 161        /* PC3  */ {   0,   0,   0,   1,   0,   0   }, /* PC3 */
 162        /* PC2  */ {   0,   0,   0,   1,   0,   1   }, /* ENET FDE */
 163        /* PC1  */ {   0,   0,   0,   1,   0,   0   }, /* ENET DSQE */
 164        /* PC0  */ {   0,   0,   0,   1,   0,   0   }, /* ENET LBK */
 165    },
 166
 167    /* Port D */
 168    {   /*            conf ppar psor pdir podr pdat */
 169        /* PD31 */ {   1,   1,   0,   0,   0,   0   }, /* SCC1 EN RxD */
 170        /* PD30 */ {   1,   1,   1,   1,   0,   0   }, /* SCC1 EN TxD */
 171        /* PD29 */ {   1,   1,   0,   1,   0,   0   }, /* SCC1 EN TENA */
 172        /* PD28 */ {   0,   1,   0,   0,   0,   0   }, /* PD28 */
 173        /* PD27 */ {   0,   1,   1,   1,   0,   0   }, /* PD27 */
 174        /* PD26 */ {   0,   0,   0,   1,   0,   0   }, /* PD26 */
 175        /* PD25 */ {   0,   0,   0,   1,   0,   0   }, /* PD25 */
 176        /* PD24 */ {   0,   0,   0,   1,   0,   0   }, /* PD24 */
 177        /* PD23 */ {   0,   0,   0,   1,   0,   0   }, /* PD23 */
 178        /* PD22 */ {   0,   0,   0,   1,   0,   0   }, /* PD22 */
 179        /* PD21 */ {   0,   0,   0,   1,   0,   0   }, /* PD21 */
 180        /* PD20 */ {   0,   0,   0,   1,   0,   0   }, /* PD20 */
 181        /* PD19 */ {   0,   0,   0,   1,   0,   0   }, /* PD19 */
 182        /* PD18 */ {   0,   0,   0,   1,   0,   0   }, /* PD18 */
 183        /* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
 184        /* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
 185        /* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
 186        /* PD14 */ {   0,   0,   0,   1,   0,   0   }, /* LED */
 187        /* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
 188        /* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
 189        /* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
 190        /* PD10 */ {   0,   0,   0,   0,   0,   0   }, /* PD10 */
 191        /* PD9  */ {   0,   1,   0,   1,   0,   0   }, /* SMC1 TXD */
 192        /* PD8  */ {   0,   1,   0,   0,   0,   0   }, /* SMC1 RXD */
 193        /* PD7  */ {   0,   0,   0,   1,   0,   1   }, /* PD7 */
 194        /* PD6  */ {   0,   0,   0,   1,   0,   1   }, /* PD6 */
 195        /* PD5  */ {   0,   0,   0,   1,   0,   1   }, /* PD5 */
 196        /* PD4  */ {   0,   0,   0,   1,   0,   1   }, /* PD4 */
 197        /* PD3  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 198        /* PD2  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 199        /* PD1  */ {   0,   0,   0,   0,   0,   0   }, /* pin doesn't exist */
 200        /* PD0  */ {   0,   0,   0,   0,   0,   0   }  /* pin doesn't exist */
 201    }
 202};
 203
 204
 205/*
 206 * MPC8560ADS Board Status & Control Registers
 207 */
 208typedef struct bcsr_ {
 209        volatile unsigned char bcsr0;
 210        volatile unsigned char bcsr1;
 211        volatile unsigned char bcsr2;
 212        volatile unsigned char bcsr3;
 213        volatile unsigned char bcsr4;
 214        volatile unsigned char bcsr5;
 215} bcsr_t;
 216
 217void reset_phy (void)
 218{
 219#if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
 220        volatile bcsr_t *bcsr = (bcsr_t *) CONFIG_SYS_BCSR;
 221#endif
 222        /* reset Giga bit Ethernet port if needed here */
 223
 224        /* reset the CPM FEC port */
 225#if (CONFIG_ETHER_INDEX == 2)
 226        bcsr->bcsr2 &= ~FETH2_RST;
 227        udelay(2);
 228        bcsr->bcsr2 |=  FETH2_RST;
 229        udelay(1000);
 230#elif (CONFIG_ETHER_INDEX == 3)
 231        bcsr->bcsr3 &= ~FETH3_RST;
 232        udelay(2);
 233        bcsr->bcsr3 |=  FETH3_RST;
 234        udelay(1000);
 235#endif
 236#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
 237        /* reset PHY */
 238        miiphy_reset("FCC1 ETHERNET", 0x0);
 239
 240        /* change PHY address to 0x02 */
 241        bb_miiphy_write(NULL, 0, PHY_MIPSCR, 0xf028);
 242
 243        bb_miiphy_write(NULL, 0x02, PHY_BMCR,
 244                        PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 245#endif /* CONFIG_MII */
 246}
 247
 248
 249int checkboard (void)
 250{
 251        puts("Board: ADS\n");
 252
 253#ifdef CONFIG_PCI
 254        printf("    PCI1: 32 bit, %d MHz (compiled)\n",
 255               CONFIG_SYS_CLK_FREQ / 1000000);
 256#else
 257        printf("    PCI1: disabled\n");
 258#endif
 259
 260        /*
 261         * Initialize local bus.
 262         */
 263        local_bus_init();
 264
 265        return 0;
 266}
 267
 268
 269phys_size_t
 270initdram(int board_type)
 271{
 272        long dram_size = 0;
 273
 274        puts("Initializing\n");
 275
 276#if defined(CONFIG_DDR_DLL)
 277        {
 278            volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 279            uint temp_ddrdll = 0;
 280
 281            /*
 282             * Work around to stabilize DDR DLL
 283             */
 284            temp_ddrdll = gur->ddrdllcr;
 285            gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000;
 286            asm("sync;isync;msync");
 287        }
 288#endif
 289
 290#ifdef CONFIG_SPD_EEPROM
 291        dram_size = fsl_ddr_sdram();
 292        dram_size = setup_ddr_tlbs(dram_size / 0x100000);
 293
 294        dram_size *= 0x100000;
 295#else
 296        dram_size = fixed_sdram();
 297#endif
 298
 299#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 300        /*
 301         * Initialize and enable DDR ECC.
 302         */
 303        ddr_enable_ecc(dram_size);
 304#endif
 305
 306        /*
 307         * Initialize SDRAM.
 308         */
 309        sdram_init();
 310
 311        puts("    DDR: ");
 312        return dram_size;
 313}
 314
 315
 316/*
 317 * Initialize Local Bus
 318 */
 319
 320void
 321local_bus_init(void)
 322{
 323        volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 324        volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 325
 326        uint clkdiv;
 327        uint lbc_hz;
 328        sys_info_t sysinfo;
 329
 330        /*
 331         * Errata LBC11.
 332         * Fix Local Bus clock glitch when DLL is enabled.
 333         *
 334         * If localbus freq is < 66MHz, DLL bypass mode must be used.
 335         * If localbus freq is > 133MHz, DLL can be safely enabled.
 336         * Between 66 and 133, the DLL is enabled with an override workaround.
 337         */
 338
 339        get_sys_info(&sysinfo);
 340        clkdiv = lbc->lcrr & LCRR_CLKDIV;
 341        lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 342
 343        if (lbc_hz < 66) {
 344                lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000;   /* DLL Bypass */
 345
 346        } else if (lbc_hz >= 133) {
 347                lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 348
 349        } else {
 350                /*
 351                 * On REV1 boards, need to change CLKDIV before enable DLL.
 352                 * Default CLKDIV is 8, change it to 4 temporarily.
 353                 */
 354                uint pvr = get_pvr();
 355                uint temp_lbcdll = 0;
 356
 357                if (pvr == PVR_85xx_REV1) {
 358                        /* FIXME: Justify the high bit here. */
 359                        lbc->lcrr = 0x10000004;
 360                }
 361
 362                lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */
 363                udelay(200);
 364
 365                /*
 366                 * Sample LBC DLL ctrl reg, upshift it to set the
 367                 * override bits.
 368                 */
 369                temp_lbcdll = gur->lbcdllcr;
 370                gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000);
 371                asm("sync;isync;msync");
 372        }
 373}
 374
 375
 376/*
 377 * Initialize SDRAM memory on the Local Bus.
 378 */
 379
 380void
 381sdram_init(void)
 382{
 383        volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 384        uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 385
 386        puts("    SDRAM: ");
 387        print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 388
 389        /*
 390         * Setup SDRAM Base and Option Registers
 391         */
 392        lbc->or2 = CONFIG_SYS_OR2_PRELIM;
 393        lbc->br2 = CONFIG_SYS_BR2_PRELIM;
 394        lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 395        asm("msync");
 396
 397        lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 398        lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 399        asm("sync");
 400
 401        /*
 402         * Configure the SDRAM controller.
 403         */
 404        lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
 405        asm("sync");
 406        *sdram_addr = 0xff;
 407        ppcDcbf((unsigned long) sdram_addr);
 408        udelay(100);
 409
 410        lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
 411        asm("sync");
 412        *sdram_addr = 0xff;
 413        ppcDcbf((unsigned long) sdram_addr);
 414        udelay(100);
 415
 416        lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
 417        asm("sync");
 418        *sdram_addr = 0xff;
 419        ppcDcbf((unsigned long) sdram_addr);
 420        udelay(100);
 421
 422        lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
 423        asm("sync");
 424        *sdram_addr = 0xff;
 425        ppcDcbf((unsigned long) sdram_addr);
 426        udelay(100);
 427
 428        lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
 429        asm("sync");
 430        *sdram_addr = 0xff;
 431        ppcDcbf((unsigned long) sdram_addr);
 432        udelay(100);
 433}
 434
 435#if !defined(CONFIG_SPD_EEPROM)
 436/*************************************************************************
 437 *  fixed sdram init -- doesn't use serial presence detect.
 438 ************************************************************************/
 439long int fixed_sdram (void)
 440{
 441  #ifndef CONFIG_SYS_RAMBOOT
 442        volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 443
 444        ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
 445        ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 446        ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
 447        ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 448        ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
 449        ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 450    #if defined (CONFIG_DDR_ECC)
 451        ddr->err_disable = 0x0000000D;
 452        ddr->err_sbe = 0x00ff0000;
 453    #endif
 454        asm("sync;isync;msync");
 455        udelay(500);
 456    #if defined (CONFIG_DDR_ECC)
 457        /* Enable ECC checking */
 458        ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
 459    #else
 460        ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 461    #endif
 462        asm("sync; isync; msync");
 463        udelay(500);
 464  #endif
 465        return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 466}
 467#endif  /* !defined(CONFIG_SPD_EEPROM) */
 468
 469
 470#if defined(CONFIG_PCI)
 471/*
 472 * Initialize PCI Devices, report devices found.
 473 */
 474
 475#ifndef CONFIG_PCI_PNP
 476static struct pci_config_table pci_mpc85xxads_config_table[] = {
 477    { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
 478      PCI_IDSEL_NUMBER, PCI_ANY_ID,
 479      pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
 480                                   PCI_ENET0_MEMADDR,
 481                                   PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER
 482      } },
 483    { }
 484};
 485#endif
 486
 487
 488static struct pci_controller hose = {
 489#ifndef CONFIG_PCI_PNP
 490        config_table: pci_mpc85xxads_config_table,
 491#endif
 492};
 493
 494#endif  /* CONFIG_PCI */
 495
 496
 497void
 498pci_init_board(void)
 499{
 500#ifdef CONFIG_PCI
 501        pci_mpc85xx_init(&hose);
 502#endif /* CONFIG_PCI */
 503}
 504
 505
 506#if defined(CONFIG_OF_BOARD_SETUP)
 507void
 508ft_board_setup(void *blob, bd_t *bd)
 509{
 510        int node, tmp[2];
 511        const char *path;
 512
 513        ft_cpu_setup(blob, bd);
 514
 515        node = fdt_path_offset(blob, "/aliases");
 516        tmp[0] = 0;
 517        if (node >= 0) {
 518#ifdef CONFIG_PCI
 519                path = fdt_getprop(blob, node, "pci0", NULL);
 520                if (path) {
 521                        tmp[1] = hose.last_busno - hose.first_busno;
 522                        do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 523                }
 524#endif
 525        }
 526}
 527#endif
 528