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27#include <config.h>
28#include <common.h>
29#include <config.h>
30#include <pci.h>
31#ifdef CONFIG_SC520_SSI
32#include <asm/ic/ssi.h>
33#endif
34#include <asm/io.h>
35#include <asm/pci.h>
36#include <asm/ic/sc520.h>
37
38DECLARE_GLOBAL_DATA_PTR;
39
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60
61
62static u32 mmcr_base= 0xfffef000;
63
64void write_mmcr_byte(u16 mmcr, u8 data)
65{
66 writeb(data, mmcr+mmcr_base);
67}
68
69void write_mmcr_word(u16 mmcr, u16 data)
70{
71 writew(data, mmcr+mmcr_base);
72}
73
74void write_mmcr_long(u16 mmcr, u32 data)
75{
76 writel(data, mmcr+mmcr_base);
77}
78
79u8 read_mmcr_byte(u16 mmcr)
80{
81 return readb(mmcr+mmcr_base);
82}
83
84u16 read_mmcr_word(u16 mmcr)
85{
86 return readw(mmcr+mmcr_base);
87}
88
89u32 read_mmcr_long(u16 mmcr)
90{
91 return readl(mmcr+mmcr_base);
92}
93
94
95void init_sc520(void)
96{
97
98
99
100 write_mmcr_byte(SC520_UART1CTL, 7);
101 write_mmcr_byte(SC520_UART2CTL, 7);
102
103
104 write_mmcr_byte(SC520_CLKSEL, 0x72);
105
106
107 write_mmcr_byte(SC520_SYSARBCTL,0x02);
108
109 write_mmcr_word(SC520_SYSARBMENB,0x1f);
110 write_mmcr_word(SC520_HBCTL,0x04);
111
112
113 if (CONFIG_SYS_SC520_HIGH_SPEED) {
114 write_mmcr_byte(SC520_CPUCTL, 0x2);
115 gd->cpu_clk = 133000000;
116 printf("## CPU Speed set to 133MHz\n");
117 } else {
118 write_mmcr_byte(SC520_CPUCTL, 1);
119 printf("## CPU Speed set to 100MHz\n");
120 gd->cpu_clk = 100000000;
121 }
122
123
124
125 asm("movl $0x2000,%%ecx\n"
126 "wait_loop: pushl %%ecx\n"
127 "popl %%ecx\n"
128 "loop wait_loop\n": : : "ecx");
129
130
131 write_mmcr_byte(SC520_DBCTL, 0x11);
132
133
134 asm("movl %%cr0, %%eax\n"
135 "andl $0x9fffffff, %%eax\n"
136 "movl %%eax, %%cr0\n" : : : "eax");
137}
138
139unsigned long init_sc520_dram(void)
140{
141 bd_t *bd = gd->bd;
142
143 u32 dram_present=0;
144 u32 dram_ctrl;
145#ifdef CONFIG_SYS_SDRAM_DRCTMCTL
146
147
148
149
150
151
152
153#else
154 int val;
155
156 int cas_precharge_delay = CONFIG_SYS_SDRAM_PRECHARGE_DELAY;
157 int refresh_rate = CONFIG_SYS_SDRAM_REFRESH_RATE;
158 int ras_cas_delay = CONFIG_SYS_SDRAM_RAS_CAS_DELAY;
159
160
161
162 refresh_rate/=78;
163 if (refresh_rate<=1) {
164 val = 0;
165 } else if (refresh_rate==2) {
166 val = 1;
167 } else if (refresh_rate==3 || refresh_rate==4) {
168 val = 2;
169 } else {
170 val = 3;
171 }
172
173 write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
174
175 val = read_mmcr_byte(SC520_DRCTMCTL);
176 val &= 0xf0;
177
178 if (cas_precharge_delay==3) {
179 val |= 0x04;
180 } else if (cas_precharge_delay==4) {
181 val |= 0x08;
182 } else if (cas_precharge_delay>4) {
183 val |= 0x0c;
184 }
185
186 if (ras_cas_delay > 3) {
187 val |= 2;
188 } else {
189 val |= 1;
190 }
191 write_mmcr_byte(SC520_DRCTMCTL, val);
192#endif
193
194
195
196 dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
197
198 bd->bi_dram[0].start = 0;
199 if (dram_ctrl & 0x80) {
200
201 dram_present = bd->bi_dram[1].start = (dram_ctrl & 0x7f) << 22;
202 bd->bi_dram[0].size = bd->bi_dram[1].start;
203
204 } else {
205 bd->bi_dram[0].size = 0;
206 bd->bi_dram[1].start = bd->bi_dram[0].start;
207 }
208
209 if (dram_ctrl & 0x8000) {
210
211 dram_present = bd->bi_dram[2].start = (dram_ctrl & 0x7f00) << 14;
212 bd->bi_dram[1].size = bd->bi_dram[2].start - bd->bi_dram[1].start;
213 } else {
214 bd->bi_dram[1].size = 0;
215 bd->bi_dram[2].start = bd->bi_dram[1].start;
216 }
217
218 if (dram_ctrl & 0x800000) {
219
220 dram_present = bd->bi_dram[3].start = (dram_ctrl & 0x7f0000) << 6;
221 bd->bi_dram[2].size = bd->bi_dram[3].start - bd->bi_dram[2].start;
222 } else {
223 bd->bi_dram[2].size = 0;
224 bd->bi_dram[3].start = bd->bi_dram[2].start;
225 }
226
227 if (dram_ctrl & 0x80000000) {
228
229 dram_present = (dram_ctrl & 0x7f000000) >> 2;
230 bd->bi_dram[3].size = dram_present - bd->bi_dram[3].start;
231 } else {
232 bd->bi_dram[3].size = 0;
233 }
234
235
236#if 0
237 printf("Configured %d bytes of dram\n", dram_present);
238#endif
239 gd->ram_size = dram_present;
240
241 return dram_present;
242}
243
244
245#ifdef CONFIG_PCI
246
247
248static struct {
249 u8 priority;
250 u16 level_reg;
251 u8 level_bit;
252} sc520_irq[] = {
253 { SC520_IRQ0, SC520_MPICMODE, 0x01 },
254 { SC520_IRQ1, SC520_MPICMODE, 0x02 },
255 { SC520_IRQ2, SC520_SL1PICMODE, 0x02 },
256 { SC520_IRQ3, SC520_MPICMODE, 0x08 },
257 { SC520_IRQ4, SC520_MPICMODE, 0x10 },
258 { SC520_IRQ5, SC520_MPICMODE, 0x20 },
259 { SC520_IRQ6, SC520_MPICMODE, 0x40 },
260 { SC520_IRQ7, SC520_MPICMODE, 0x80 },
261
262 { SC520_IRQ8, SC520_SL1PICMODE, 0x01 },
263 { SC520_IRQ9, SC520_SL1PICMODE, 0x02 },
264 { SC520_IRQ10, SC520_SL1PICMODE, 0x04 },
265 { SC520_IRQ11, SC520_SL1PICMODE, 0x08 },
266 { SC520_IRQ12, SC520_SL1PICMODE, 0x10 },
267 { SC520_IRQ13, SC520_SL1PICMODE, 0x20 },
268 { SC520_IRQ14, SC520_SL1PICMODE, 0x40 },
269 { SC520_IRQ15, SC520_SL1PICMODE, 0x80 }
270};
271
272
273
274int sc520_pci_ints[15] = {
275 -1, -1, -1, -1, -1, -1, -1, -1,
276 -1, -1, -1, -1, -1, -1, -1
277};
278
279
280int pci_sc520_set_irq(int pci_pin, int irq)
281{
282 int i;
283
284# if 1
285 printf("set_irq(): map INT%c to IRQ%d\n", pci_pin + 'A', irq);
286#endif
287 if (irq < 0 || irq > 15) {
288 return -1;
289 }
290
291 if (pci_pin < 0 || pci_pin > 15) {
292 return -1;
293 }
294
295
296
297 for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) {
298 if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) {
299 continue;
300 }
301 if (read_mmcr_byte(i) == sc520_irq[irq].priority) {
302 write_mmcr_byte(i, SC520_IRQ_DISABLED);
303 }
304 }
305
306
307 write_mmcr_byte(sc520_irq[irq].level_reg,
308 read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit);
309
310
311 if (pci_pin < 4) {
312
313
314 write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority);
315
316
317 } else {
318
319 write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority);
320
321
322 write_mmcr_word(SC520_INTPINPOL,
323 read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4)));
324
325 }
326
327
328 sc520_pci_ints[pci_pin] = irq;
329
330
331 return 0;
332}
333
334void pci_sc520_init(struct pci_controller *hose)
335{
336 hose->first_busno = 0;
337 hose->last_busno = 0xff;
338
339
340 pci_set_region(hose->regions + 0,
341 SC520_PCI_MEMORY_BUS,
342 SC520_PCI_MEMORY_PHYS,
343 SC520_PCI_MEMORY_SIZE,
344 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
345
346
347 pci_set_region(hose->regions + 1,
348 SC520_PCI_MEM_BUS,
349 SC520_PCI_MEM_PHYS,
350 SC520_PCI_MEM_SIZE,
351 PCI_REGION_MEM);
352
353
354 pci_set_region(hose->regions + 2,
355 SC520_ISA_MEM_BUS,
356 SC520_ISA_MEM_PHYS,
357 SC520_ISA_MEM_SIZE,
358 PCI_REGION_MEM);
359
360
361 pci_set_region(hose->regions + 3,
362 SC520_PCI_IO_BUS,
363 SC520_PCI_IO_PHYS,
364 SC520_PCI_IO_SIZE,
365 PCI_REGION_IO);
366
367
368 pci_set_region(hose->regions + 4,
369 SC520_ISA_IO_BUS,
370 SC520_ISA_IO_PHYS,
371 SC520_ISA_IO_SIZE,
372 PCI_REGION_IO);
373
374 hose->region_count = 5;
375
376 pci_setup_type1(hose,
377 SC520_REG_ADDR,
378 SC520_REG_DATA);
379
380 pci_register_hose(hose);
381
382 hose->last_busno = pci_hose_scan(hose);
383
384
385 pci_write_config_word(0, PCI_COMMAND,
386 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
387
388}
389
390
391#endif
392
393#ifdef CONFIG_SYS_TIMER_SC520
394
395
396void reset_timer(void)
397{
398 write_mmcr_word(SC520_GPTMR0CNT, 0);
399 write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
400
401}
402
403ulong get_timer(ulong base)
404{
405
406 return read_mmcr_word(SC520_GPTMR0CNT) / 33;
407}
408
409void set_timer(ulong t)
410{
411
412 write_mmcr_word(SC520_GPTMR0CTL, 0x4001);
413 write_mmcr_word(SC520_GPTMR0CNT, t*33);
414 write_mmcr_word(SC520_GPTMR0CTL, 0x6001);
415}
416
417
418void udelay(unsigned long usec)
419{
420 int m=0;
421 long u;
422
423 read_mmcr_word(SC520_SWTMRMILLI);
424 read_mmcr_word(SC520_SWTMRMICRO);
425
426#if 0
427
428 printf("udelay: %ld m.u %d.%d tm.tu %d.%d\n", usec, m, u, tm, tu);
429#endif
430 while (1) {
431
432 m += read_mmcr_word(SC520_SWTMRMILLI);
433 u = read_mmcr_word(SC520_SWTMRMICRO) + (m * 1000);
434
435 if (usec <= u) {
436 break;
437 }
438 }
439}
440
441#endif
442
443int ssi_set_interface(int freq, int lsb_first, int inv_clock, int inv_phase)
444{
445 u8 temp=0;
446
447 if (freq >= 8192) {
448 temp |= CTL_CLK_SEL_4;
449 } else if (freq >= 4096) {
450 temp |= CTL_CLK_SEL_8;
451 } else if (freq >= 2048) {
452 temp |= CTL_CLK_SEL_16;
453 } else if (freq >= 1024) {
454 temp |= CTL_CLK_SEL_32;
455 } else if (freq >= 512) {
456 temp |= CTL_CLK_SEL_64;
457 } else if (freq >= 256) {
458 temp |= CTL_CLK_SEL_128;
459 } else if (freq >= 128) {
460 temp |= CTL_CLK_SEL_256;
461 } else {
462 temp |= CTL_CLK_SEL_512;
463 }
464
465 if (!lsb_first) {
466 temp |= MSBF_ENB;
467 }
468
469 if (inv_clock) {
470 temp |= CLK_INV_ENB;
471 }
472
473 if (inv_phase) {
474 temp |= PHS_INV_ENB;
475 }
476
477 write_mmcr_byte(SC520_SSICTL, temp);
478
479 return 0;
480}
481
482u8 ssi_txrx_byte(u8 data)
483{
484 write_mmcr_byte(SC520_SSIXMIT, data);
485 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
486 write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV);
487 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
488 return read_mmcr_byte(SC520_SSIRCV);
489}
490
491
492void ssi_tx_byte(u8 data)
493{
494 write_mmcr_byte(SC520_SSIXMIT, data);
495 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
496 write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT);
497}
498
499u8 ssi_rx_byte(void)
500{
501 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
502 write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV);
503 while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
504 return read_mmcr_byte(SC520_SSIRCV);
505}
506
507#ifdef CONFIG_SYS_RESET_SC520
508void reset_cpu(ulong addr)
509{
510 printf("Resetting using SC520 MMCR\n");
511
512 write_mmcr_word(SC520_RESCFG, 0x0001);
513
514
515}
516#endif
517