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29#include <config.h>
30#include <common.h>
31#include <mpc86xx.h>
32#include <asm/mmu.h>
33#include <asm/fsl_law.h>
34#include "mp.h"
35
36void setup_bats(void);
37
38DECLARE_GLOBAL_DATA_PTR;
39
40
41
42
43
44
45
46
47void cpu_init_f(void)
48{
49 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
50 volatile ccsr_lbc_t *memctl = &immap->im_lbc;
51
52
53 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
54
55
56 memset ((void *) gd, 0, sizeof (gd_t));
57
58#ifdef CONFIG_FSL_LAW
59 init_laws();
60#endif
61
62 setup_bats();
63
64
65
66
67
68
69#if defined(CONFIG_SYS_OR0_REMAP)
70 memctl->or0 = CONFIG_SYS_OR0_REMAP;
71#endif
72#if defined(CONFIG_SYS_OR1_REMAP)
73 memctl->or1 = CONFIG_SYS_OR1_REMAP;
74#endif
75
76
77#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
78 memctl->br0 = CONFIG_SYS_BR0_PRELIM;
79 memctl->or0 = CONFIG_SYS_OR0_PRELIM;
80#endif
81
82#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
83 memctl->or1 = CONFIG_SYS_OR1_PRELIM;
84 memctl->br1 = CONFIG_SYS_BR1_PRELIM;
85#endif
86
87#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
88 memctl->or2 = CONFIG_SYS_OR2_PRELIM;
89 memctl->br2 = CONFIG_SYS_BR2_PRELIM;
90#endif
91
92#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
93 memctl->or3 = CONFIG_SYS_OR3_PRELIM;
94 memctl->br3 = CONFIG_SYS_BR3_PRELIM;
95#endif
96
97#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
98 memctl->or4 = CONFIG_SYS_OR4_PRELIM;
99 memctl->br4 = CONFIG_SYS_BR4_PRELIM;
100#endif
101
102#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
103 memctl->or5 = CONFIG_SYS_OR5_PRELIM;
104 memctl->br5 = CONFIG_SYS_BR5_PRELIM;
105#endif
106
107#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
108 memctl->or6 = CONFIG_SYS_OR6_PRELIM;
109 memctl->br6 = CONFIG_SYS_BR6_PRELIM;
110#endif
111
112#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
113 memctl->or7 = CONFIG_SYS_OR7_PRELIM;
114 memctl->br7 = CONFIG_SYS_BR7_PRELIM;
115#endif
116
117
118 set_hid0(get_hid0() | 0x4000000);
119
120
121 set_hid1(get_hid1() | 0x80000C00);
122}
123
124
125
126
127int cpu_init_r(void)
128{
129#if (CONFIG_NUM_CPUS > 1)
130 setup_mp();
131#endif
132 return 0;
133}
134
135
136void setup_bats(void)
137{
138 write_bat(DBAT0, CONFIG_SYS_DBAT0U, CONFIG_SYS_DBAT0L);
139 write_bat(IBAT0, CONFIG_SYS_IBAT0U, CONFIG_SYS_IBAT0L);
140 write_bat(DBAT1, CONFIG_SYS_DBAT1U, CONFIG_SYS_DBAT1L);
141 write_bat(IBAT1, CONFIG_SYS_IBAT1U, CONFIG_SYS_IBAT1L);
142 write_bat(DBAT2, CONFIG_SYS_DBAT2U, CONFIG_SYS_DBAT2L);
143 write_bat(IBAT2, CONFIG_SYS_IBAT2U, CONFIG_SYS_IBAT2L);
144 write_bat(DBAT3, CONFIG_SYS_DBAT3U, CONFIG_SYS_DBAT3L);
145 write_bat(IBAT3, CONFIG_SYS_IBAT3U, CONFIG_SYS_IBAT3L);
146 write_bat(DBAT4, CONFIG_SYS_DBAT4U, CONFIG_SYS_DBAT4L);
147 write_bat(IBAT4, CONFIG_SYS_IBAT4U, CONFIG_SYS_IBAT4L);
148 write_bat(DBAT5, CONFIG_SYS_DBAT5U, CONFIG_SYS_DBAT5L);
149 write_bat(IBAT5, CONFIG_SYS_IBAT5U, CONFIG_SYS_IBAT5L);
150 write_bat(DBAT6, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
151 write_bat(IBAT6, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
152 write_bat(DBAT7, CONFIG_SYS_DBAT7U, CONFIG_SYS_DBAT7L);
153 write_bat(IBAT7, CONFIG_SYS_IBAT7U, CONFIG_SYS_IBAT7L);
154
155 return;
156}
157
158#ifdef CONFIG_ADDR_MAP
159
160void init_addr_map(void)
161{
162 int i;
163 ppc_bat_t bat = DBAT0;
164 phys_size_t size;
165 unsigned long upper, lower;
166
167 for (i = 0; i < CONFIG_SYS_NUM_ADDR_MAP; i++, bat++) {
168 if (read_bat(bat, &upper, &lower) != -1) {
169 if (!BATU_VALID(upper))
170 size = 0;
171 else
172 size = BATU_SIZE(upper);
173 addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
174 size, i);
175 }
176#ifdef CONFIG_HIGH_BATS
177
178 if (bat == DBAT3)
179 bat = DBAT4 - 1;
180#endif
181 }
182}
183#endif
184