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33#ifndef _E1000_HW_H_
34#define _E1000_HW_H_
35
36#include <common.h>
37#include <malloc.h>
38#include <net.h>
39#include <netdev.h>
40#include <asm/io.h>
41#include <pci.h>
42
43#define E1000_ERR(args...) printf("e1000: " args)
44
45#ifdef E1000_DEBUG
46#define E1000_DBG(args...) printf("e1000: " args)
47#define DEBUGOUT(fmt,args...) printf(fmt ,##args)
48#define DEBUGFUNC() printf("%s\n", __FUNCTION__);
49#else
50#define E1000_DBG(args...)
51#define DEBUGFUNC()
52#define DEBUGOUT(fmt,args...)
53#endif
54
55
56struct e1000_hw;
57struct e1000_hw_stats;
58
59typedef enum {
60 FALSE = 0,
61 TRUE = 1
62} boolean_t;
63
64
65
66typedef enum {
67 e1000_undefined = 0,
68 e1000_82542_rev2_0,
69 e1000_82542_rev2_1,
70 e1000_82543,
71 e1000_82544,
72 e1000_82540,
73 e1000_82545,
74 e1000_82546,
75 e1000_82541,
76 e1000_82541_rev_2,
77 e1000_num_macs
78} e1000_mac_type;
79
80
81typedef enum {
82 e1000_media_type_copper = 0,
83 e1000_media_type_fiber = 1,
84 e1000_num_media_types
85} e1000_media_type;
86
87typedef enum {
88 e1000_10_half = 0,
89 e1000_10_full = 1,
90 e1000_100_half = 2,
91 e1000_100_full = 3
92} e1000_speed_duplex_type;
93
94typedef enum {
95 e1000_lan_a = 0,
96 e1000_lan_b = 1
97} e1000_lan_loc;
98
99
100typedef enum {
101 e1000_fc_none = 0,
102 e1000_fc_rx_pause = 1,
103 e1000_fc_tx_pause = 2,
104 e1000_fc_full = 3,
105 e1000_fc_default = 0xFF
106} e1000_fc_type;
107
108
109typedef enum {
110 e1000_bus_type_unknown = 0,
111 e1000_bus_type_pci,
112 e1000_bus_type_pcix
113} e1000_bus_type;
114
115
116typedef enum {
117 e1000_bus_speed_unknown = 0,
118 e1000_bus_speed_33,
119 e1000_bus_speed_66,
120 e1000_bus_speed_100,
121 e1000_bus_speed_133,
122 e1000_bus_speed_reserved
123} e1000_bus_speed;
124
125
126typedef enum {
127 e1000_bus_width_unknown = 0,
128 e1000_bus_width_32,
129 e1000_bus_width_64
130} e1000_bus_width;
131
132
133typedef enum {
134 e1000_cable_length_50 = 0,
135 e1000_cable_length_50_80,
136 e1000_cable_length_80_110,
137 e1000_cable_length_110_140,
138 e1000_cable_length_140,
139 e1000_cable_length_undefined = 0xFF
140} e1000_cable_length;
141
142typedef enum {
143 e1000_10bt_ext_dist_enable_normal = 0,
144 e1000_10bt_ext_dist_enable_lower,
145 e1000_10bt_ext_dist_enable_undefined = 0xFF
146} e1000_10bt_ext_dist_enable;
147
148typedef enum {
149 e1000_rev_polarity_normal = 0,
150 e1000_rev_polarity_reversed,
151 e1000_rev_polarity_undefined = 0xFF
152} e1000_rev_polarity;
153
154typedef enum {
155 e1000_polarity_reversal_enabled = 0,
156 e1000_polarity_reversal_disabled,
157 e1000_polarity_reversal_undefined = 0xFF
158} e1000_polarity_reversal;
159
160typedef enum {
161 e1000_auto_x_mode_manual_mdi = 0,
162 e1000_auto_x_mode_manual_mdix,
163 e1000_auto_x_mode_auto1,
164 e1000_auto_x_mode_auto2,
165 e1000_auto_x_mode_undefined = 0xFF
166} e1000_auto_x_mode;
167
168typedef enum {
169 e1000_1000t_rx_status_not_ok = 0,
170 e1000_1000t_rx_status_ok,
171 e1000_1000t_rx_status_undefined = 0xFF
172} e1000_1000t_rx_status;
173
174typedef enum {
175 e1000_phy_m88 = 0,
176 e1000_phy_igp,
177 e1000_phy_igp_2,
178 e1000_phy_undefined = 0xFF
179} e1000_phy_type;
180
181struct e1000_phy_info {
182 e1000_cable_length cable_length;
183 e1000_10bt_ext_dist_enable extended_10bt_distance;
184 e1000_rev_polarity cable_polarity;
185 e1000_polarity_reversal polarity_correction;
186 e1000_auto_x_mode mdix_mode;
187 e1000_1000t_rx_status local_rx;
188 e1000_1000t_rx_status remote_rx;
189};
190
191struct e1000_phy_stats {
192 uint32_t idle_errors;
193 uint32_t receive_errors;
194};
195
196
197#define E1000_SUCCESS 0
198#define E1000_ERR_EEPROM 1
199#define E1000_ERR_PHY 2
200#define E1000_ERR_CONFIG 3
201#define E1000_ERR_PARAM 4
202#define E1000_ERR_MAC_TYPE 5
203#define E1000_ERR_PHY_TYPE 6
204#define E1000_ERR_NOLINK 7
205#define E1000_ERR_TIMEOUT 8
206#define E1000_ERR_RESET 9
207#define E1000_ERR_MASTER_REQUESTS_PENDING 10
208#define E1000_ERR_HOST_INTERFACE_COMMAND 11
209#define E1000_BLK_PHY_RESET 12
210
211
212#define E1000_DEV_ID_82542 0x1000
213#define E1000_DEV_ID_82543GC_FIBER 0x1001
214#define E1000_DEV_ID_82543GC_COPPER 0x1004
215#define E1000_DEV_ID_82544EI_COPPER 0x1008
216#define E1000_DEV_ID_82544EI_FIBER 0x1009
217#define E1000_DEV_ID_82544GC_COPPER 0x100C
218#define E1000_DEV_ID_82544GC_LOM 0x100D
219#define E1000_DEV_ID_82540EM 0x100E
220#define E1000_DEV_ID_82540EM_LOM 0x1015
221#define E1000_DEV_ID_82545GM_COPPER 0x1026
222#define E1000_DEV_ID_82545EM_COPPER 0x100F
223#define E1000_DEV_ID_82545EM_FIBER 0x1011
224#define E1000_DEV_ID_82546EB_COPPER 0x1010
225#define E1000_DEV_ID_82546EB_FIBER 0x1012
226#define E1000_DEV_ID_82541ER 0x1078
227#define E1000_DEV_ID_82541GI_LF 0x107C
228#define NUM_DEV_IDS 16
229
230#define NODE_ADDRESS_SIZE 6
231#define ETH_LENGTH_OF_ADDRESS 6
232
233
234#define MAC_DECODE_SIZE (128 * 1024)
235
236#define E1000_82542_2_0_REV_ID 2
237#define E1000_82542_2_1_REV_ID 3
238
239#define SPEED_10 10
240#define SPEED_100 100
241#define SPEED_1000 1000
242#define HALF_DUPLEX 1
243#define FULL_DUPLEX 2
244
245
246#define ENET_HEADER_SIZE 14
247#define MAXIMUM_ETHERNET_FRAME_SIZE 1518
248#define MINIMUM_ETHERNET_FRAME_SIZE 64
249#define ETHERNET_FCS_SIZE 4
250#define MAXIMUM_ETHERNET_PACKET_SIZE \
251 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
252#define MINIMUM_ETHERNET_PACKET_SIZE \
253 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
254#define CRC_LENGTH ETHERNET_FCS_SIZE
255#define MAX_JUMBO_FRAME_SIZE 0x3F00
256
257
258#define VLAN_TAG_SIZE 4
259
260
261#define ETHERNET_IEEE_VLAN_TYPE 0x8100
262#define ETHERNET_IP_TYPE 0x0800
263#define ETHERNET_ARP_TYPE 0x0806
264
265
266#define IP_PROTOCOL_TCP 6
267#define IP_PROTOCOL_UDP 0x11
268
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273
274#define POLL_IMS_ENABLE_MASK ( \
275 E1000_IMS_RXDMT0 | \
276 E1000_IMS_RXSEQ)
277
278
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284
285
286#define IMS_ENABLE_MASK ( \
287 E1000_IMS_RXT0 | \
288 E1000_IMS_TXDW | \
289 E1000_IMS_RXDMT0 | \
290 E1000_IMS_RXSEQ | \
291 E1000_IMS_LSC)
292
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296
297
298#define E1000_RAR_ENTRIES 16
299
300#define MIN_NUMBER_OF_DESCRIPTORS 8
301#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
302
303
304struct e1000_rx_desc {
305 uint64_t buffer_addr;
306 uint16_t length;
307 uint16_t csum;
308 uint8_t status;
309 uint8_t errors;
310 uint16_t special;
311};
312
313
314#define E1000_RXD_STAT_DD 0x01
315#define E1000_RXD_STAT_EOP 0x02
316#define E1000_RXD_STAT_IXSM 0x04
317#define E1000_RXD_STAT_VP 0x08
318#define E1000_RXD_STAT_TCPCS 0x20
319#define E1000_RXD_STAT_IPCS 0x40
320#define E1000_RXD_STAT_PIF 0x80
321#define E1000_RXD_ERR_CE 0x01
322#define E1000_RXD_ERR_SE 0x02
323#define E1000_RXD_ERR_SEQ 0x04
324#define E1000_RXD_ERR_CXE 0x10
325#define E1000_RXD_ERR_TCPE 0x20
326#define E1000_RXD_ERR_IPE 0x40
327#define E1000_RXD_ERR_RXE 0x80
328#define E1000_RXD_SPC_VLAN_MASK 0x0FFF
329#define E1000_RXD_SPC_PRI_MASK 0xE000
330#define E1000_RXD_SPC_PRI_SHIFT 0x000D
331#define E1000_RXD_SPC_CFI_MASK 0x1000
332#define E1000_RXD_SPC_CFI_SHIFT 0x000C
333
334
335#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
336 E1000_RXD_ERR_CE | \
337 E1000_RXD_ERR_SE | \
338 E1000_RXD_ERR_SEQ | \
339 E1000_RXD_ERR_CXE | \
340 E1000_RXD_ERR_RXE)
341
342
343struct e1000_tx_desc {
344 uint64_t buffer_addr;
345 union {
346 uint32_t data;
347 struct {
348 uint16_t length;
349 uint8_t cso;
350 uint8_t cmd;
351 } flags;
352 } lower;
353 union {
354 uint32_t data;
355 struct {
356 uint8_t status;
357 uint8_t css;
358 uint16_t special;
359 } fields;
360 } upper;
361};
362
363
364#define E1000_TXD_DTYP_D 0x00100000
365#define E1000_TXD_DTYP_C 0x00000000
366#define E1000_TXD_POPTS_IXSM 0x01
367#define E1000_TXD_POPTS_TXSM 0x02
368#define E1000_TXD_CMD_EOP 0x01000000
369#define E1000_TXD_CMD_IFCS 0x02000000
370#define E1000_TXD_CMD_IC 0x04000000
371#define E1000_TXD_CMD_RS 0x08000000
372#define E1000_TXD_CMD_RPS 0x10000000
373#define E1000_TXD_CMD_DEXT 0x20000000
374#define E1000_TXD_CMD_VLE 0x40000000
375#define E1000_TXD_CMD_IDE 0x80000000
376#define E1000_TXD_STAT_DD 0x00000001
377#define E1000_TXD_STAT_EC 0x00000002
378#define E1000_TXD_STAT_LC 0x00000004
379#define E1000_TXD_STAT_TU 0x00000008
380#define E1000_TXD_CMD_TCP 0x01000000
381#define E1000_TXD_CMD_IP 0x02000000
382#define E1000_TXD_CMD_TSE 0x04000000
383#define E1000_TXD_STAT_TC 0x00000004
384
385
386struct e1000_context_desc {
387 union {
388 uint32_t ip_config;
389 struct {
390 uint8_t ipcss;
391 uint8_t ipcso;
392 uint16_t ipcse;
393 } ip_fields;
394 } lower_setup;
395 union {
396 uint32_t tcp_config;
397 struct {
398 uint8_t tucss;
399 uint8_t tucso;
400 uint16_t tucse;
401 } tcp_fields;
402 } upper_setup;
403 uint32_t cmd_and_length;
404 union {
405 uint32_t data;
406 struct {
407 uint8_t status;
408 uint8_t hdr_len;
409 uint16_t mss;
410 } fields;
411 } tcp_seg_setup;
412};
413
414
415struct e1000_data_desc {
416 uint64_t buffer_addr;
417 union {
418 uint32_t data;
419 struct {
420 uint16_t length;
421 uint8_t typ_len_ext;
422 uint8_t cmd;
423 } flags;
424 } lower;
425 union {
426 uint32_t data;
427 struct {
428 uint8_t status;
429 uint8_t popts;
430 uint16_t special;
431 } fields;
432 } upper;
433};
434
435
436#define E1000_NUM_UNICAST 16
437#define E1000_MC_TBL_SIZE 128
438#define E1000_VLAN_FILTER_TBL_SIZE 128
439
440
441struct e1000_rar {
442 volatile uint32_t low;
443 volatile uint32_t high;
444};
445
446
447#define E1000_NUM_MTA_REGISTERS 128
448
449
450struct e1000_ipv4_at_entry {
451 volatile uint32_t ipv4_addr;
452 volatile uint32_t reserved;
453};
454
455
456#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
457#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
458#define E1000_IP6AT_SIZE 1
459
460
461struct e1000_ipv6_at_entry {
462 volatile uint8_t ipv6_addr[16];
463};
464
465
466struct e1000_fflt_entry {
467 volatile uint32_t length;
468 volatile uint32_t reserved;
469};
470
471
472struct e1000_ffmt_entry {
473 volatile uint32_t mask;
474 volatile uint32_t reserved;
475};
476
477
478struct e1000_ffvt_entry {
479 volatile uint32_t value;
480 volatile uint32_t reserved;
481};
482
483
484#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
485
486
487#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
488
489#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
490#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
491#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
492
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504
505#define E1000_CTRL 0x00000
506#define E1000_STATUS 0x00008
507#define E1000_EECD 0x00010
508#define E1000_EERD 0x00014
509#define E1000_CTRL_EXT 0x00018
510#define E1000_MDIC 0x00020
511#define E1000_FCAL 0x00028
512#define E1000_FCAH 0x0002C
513#define E1000_FCT 0x00030
514#define E1000_VET 0x00038
515#define E1000_ICR 0x000C0
516#define E1000_ITR 0x000C4
517#define E1000_ICS 0x000C8
518#define E1000_IMS 0x000D0
519#define E1000_IMC 0x000D8
520#define E1000_RCTL 0x00100
521#define E1000_FCTTV 0x00170
522#define E1000_TXCW 0x00178
523#define E1000_RXCW 0x00180
524#define E1000_TCTL 0x00400
525#define E1000_TIPG 0x00410
526#define E1000_TBT 0x00448
527#define E1000_AIT 0x00458
528#define E1000_LEDCTL 0x00E00
529#define E1000_PBA 0x01000
530#define E1000_FCRTL 0x02160
531#define E1000_FCRTH 0x02168
532#define E1000_RDBAL 0x02800
533#define E1000_RDBAH 0x02804
534#define E1000_RDLEN 0x02808
535#define E1000_RDH 0x02810
536#define E1000_RDT 0x02818
537#define E1000_RDTR 0x02820
538#define E1000_RXDCTL 0x02828
539#define E1000_RADV 0x0282C
540#define E1000_RSRPD 0x02C00
541#define E1000_TXDMAC 0x03000
542#define E1000_TDBAL 0x03800
543#define E1000_TDBAH 0x03804
544#define E1000_TDLEN 0x03808
545#define E1000_TDH 0x03810
546#define E1000_TDT 0x03818
547#define E1000_TIDV 0x03820
548#define E1000_TXDCTL 0x03828
549#define E1000_TADV 0x0382C
550#define E1000_TSPMT 0x03830
551#define E1000_CRCERRS 0x04000
552#define E1000_ALGNERRC 0x04004
553#define E1000_SYMERRS 0x04008
554#define E1000_RXERRC 0x0400C
555#define E1000_MPC 0x04010
556#define E1000_SCC 0x04014
557#define E1000_ECOL 0x04018
558#define E1000_MCC 0x0401C
559#define E1000_LATECOL 0x04020
560#define E1000_COLC 0x04028
561#define E1000_DC 0x04030
562#define E1000_TNCRS 0x04034
563#define E1000_SEC 0x04038
564#define E1000_CEXTERR 0x0403C
565#define E1000_RLEC 0x04040
566#define E1000_XONRXC 0x04048
567#define E1000_XONTXC 0x0404C
568#define E1000_XOFFRXC 0x04050
569#define E1000_XOFFTXC 0x04054
570#define E1000_FCRUC 0x04058
571#define E1000_PRC64 0x0405C
572#define E1000_PRC127 0x04060
573#define E1000_PRC255 0x04064
574#define E1000_PRC511 0x04068
575#define E1000_PRC1023 0x0406C
576#define E1000_PRC1522 0x04070
577#define E1000_GPRC 0x04074
578#define E1000_BPRC 0x04078
579#define E1000_MPRC 0x0407C
580#define E1000_GPTC 0x04080
581#define E1000_GORCL 0x04088
582#define E1000_GORCH 0x0408C
583#define E1000_GOTCL 0x04090
584#define E1000_GOTCH 0x04094
585#define E1000_RNBC 0x040A0
586#define E1000_RUC 0x040A4
587#define E1000_RFC 0x040A8
588#define E1000_ROC 0x040AC
589#define E1000_RJC 0x040B0
590#define E1000_MGTPRC 0x040B4
591#define E1000_MGTPDC 0x040B8
592#define E1000_MGTPTC 0x040BC
593#define E1000_TORL 0x040C0
594#define E1000_TORH 0x040C4
595#define E1000_TOTL 0x040C8
596#define E1000_TOTH 0x040CC
597#define E1000_TPR 0x040D0
598#define E1000_TPT 0x040D4
599#define E1000_PTC64 0x040D8
600#define E1000_PTC127 0x040DC
601#define E1000_PTC255 0x040E0
602#define E1000_PTC511 0x040E4
603#define E1000_PTC1023 0x040E8
604#define E1000_PTC1522 0x040EC
605#define E1000_MPTC 0x040F0
606#define E1000_BPTC 0x040F4
607#define E1000_TSCTC 0x040F8
608#define E1000_TSCTFC 0x040FC
609#define E1000_RXCSUM 0x05000
610#define E1000_MTA 0x05200
611#define E1000_RA 0x05400
612#define E1000_VFTA 0x05600
613#define E1000_WUC 0x05800
614#define E1000_WUFC 0x05808
615#define E1000_WUS 0x05810
616#define E1000_MANC 0x05820
617#define E1000_IPAV 0x05838
618#define E1000_IP4AT 0x05840
619#define E1000_IP6AT 0x05880
620#define E1000_WUPL 0x05900
621#define E1000_WUPM 0x05A00
622#define E1000_FFLT 0x05F00
623#define E1000_FFMT 0x09000
624#define E1000_FFVT 0x09800
625
626
627
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629
630
631
632#define E1000_82542_CTRL E1000_CTRL
633#define E1000_82542_STATUS E1000_STATUS
634#define E1000_82542_EECD E1000_EECD
635#define E1000_82542_EERD E1000_EERD
636#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
637#define E1000_82542_MDIC E1000_MDIC
638#define E1000_82542_FCAL E1000_FCAL
639#define E1000_82542_FCAH E1000_FCAH
640#define E1000_82542_FCT E1000_FCT
641#define E1000_82542_VET E1000_VET
642#define E1000_82542_RA 0x00040
643#define E1000_82542_ICR E1000_ICR
644#define E1000_82542_ITR E1000_ITR
645#define E1000_82542_ICS E1000_ICS
646#define E1000_82542_IMS E1000_IMS
647#define E1000_82542_IMC E1000_IMC
648#define E1000_82542_RCTL E1000_RCTL
649#define E1000_82542_RDTR 0x00108
650#define E1000_82542_RDBAL 0x00110
651#define E1000_82542_RDBAH 0x00114
652#define E1000_82542_RDLEN 0x00118
653#define E1000_82542_RDH 0x00120
654#define E1000_82542_RDT 0x00128
655#define E1000_82542_FCRTH 0x00160
656#define E1000_82542_FCRTL 0x00168
657#define E1000_82542_FCTTV E1000_FCTTV
658#define E1000_82542_TXCW E1000_TXCW
659#define E1000_82542_RXCW E1000_RXCW
660#define E1000_82542_MTA 0x00200
661#define E1000_82542_TCTL E1000_TCTL
662#define E1000_82542_TIPG E1000_TIPG
663#define E1000_82542_TDBAL 0x00420
664#define E1000_82542_TDBAH 0x00424
665#define E1000_82542_TDLEN 0x00428
666#define E1000_82542_TDH 0x00430
667#define E1000_82542_TDT 0x00438
668#define E1000_82542_TIDV 0x00440
669#define E1000_82542_TBT E1000_TBT
670#define E1000_82542_AIT E1000_AIT
671#define E1000_82542_VFTA 0x00600
672#define E1000_82542_LEDCTL E1000_LEDCTL
673#define E1000_82542_PBA E1000_PBA
674#define E1000_82542_RXDCTL E1000_RXDCTL
675#define E1000_82542_RADV E1000_RADV
676#define E1000_82542_RSRPD E1000_RSRPD
677#define E1000_82542_TXDMAC E1000_TXDMAC
678#define E1000_82542_TXDCTL E1000_TXDCTL
679#define E1000_82542_TADV E1000_TADV
680#define E1000_82542_TSPMT E1000_TSPMT
681#define E1000_82542_CRCERRS E1000_CRCERRS
682#define E1000_82542_ALGNERRC E1000_ALGNERRC
683#define E1000_82542_SYMERRS E1000_SYMERRS
684#define E1000_82542_RXERRC E1000_RXERRC
685#define E1000_82542_MPC E1000_MPC
686#define E1000_82542_SCC E1000_SCC
687#define E1000_82542_ECOL E1000_ECOL
688#define E1000_82542_MCC E1000_MCC
689#define E1000_82542_LATECOL E1000_LATECOL
690#define E1000_82542_COLC E1000_COLC
691#define E1000_82542_DC E1000_DC
692#define E1000_82542_TNCRS E1000_TNCRS
693#define E1000_82542_SEC E1000_SEC
694#define E1000_82542_CEXTERR E1000_CEXTERR
695#define E1000_82542_RLEC E1000_RLEC
696#define E1000_82542_XONRXC E1000_XONRXC
697#define E1000_82542_XONTXC E1000_XONTXC
698#define E1000_82542_XOFFRXC E1000_XOFFRXC
699#define E1000_82542_XOFFTXC E1000_XOFFTXC
700#define E1000_82542_FCRUC E1000_FCRUC
701#define E1000_82542_PRC64 E1000_PRC64
702#define E1000_82542_PRC127 E1000_PRC127
703#define E1000_82542_PRC255 E1000_PRC255
704#define E1000_82542_PRC511 E1000_PRC511
705#define E1000_82542_PRC1023 E1000_PRC1023
706#define E1000_82542_PRC1522 E1000_PRC1522
707#define E1000_82542_GPRC E1000_GPRC
708#define E1000_82542_BPRC E1000_BPRC
709#define E1000_82542_MPRC E1000_MPRC
710#define E1000_82542_GPTC E1000_GPTC
711#define E1000_82542_GORCL E1000_GORCL
712#define E1000_82542_GORCH E1000_GORCH
713#define E1000_82542_GOTCL E1000_GOTCL
714#define E1000_82542_GOTCH E1000_GOTCH
715#define E1000_82542_RNBC E1000_RNBC
716#define E1000_82542_RUC E1000_RUC
717#define E1000_82542_RFC E1000_RFC
718#define E1000_82542_ROC E1000_ROC
719#define E1000_82542_RJC E1000_RJC
720#define E1000_82542_MGTPRC E1000_MGTPRC
721#define E1000_82542_MGTPDC E1000_MGTPDC
722#define E1000_82542_MGTPTC E1000_MGTPTC
723#define E1000_82542_TORL E1000_TORL
724#define E1000_82542_TORH E1000_TORH
725#define E1000_82542_TOTL E1000_TOTL
726#define E1000_82542_TOTH E1000_TOTH
727#define E1000_82542_TPR E1000_TPR
728#define E1000_82542_TPT E1000_TPT
729#define E1000_82542_PTC64 E1000_PTC64
730#define E1000_82542_PTC127 E1000_PTC127
731#define E1000_82542_PTC255 E1000_PTC255
732#define E1000_82542_PTC511 E1000_PTC511
733#define E1000_82542_PTC1023 E1000_PTC1023
734#define E1000_82542_PTC1522 E1000_PTC1522
735#define E1000_82542_MPTC E1000_MPTC
736#define E1000_82542_BPTC E1000_BPTC
737#define E1000_82542_TSCTC E1000_TSCTC
738#define E1000_82542_TSCTFC E1000_TSCTFC
739#define E1000_82542_RXCSUM E1000_RXCSUM
740#define E1000_82542_WUC E1000_WUC
741#define E1000_82542_WUFC E1000_WUFC
742#define E1000_82542_WUS E1000_WUS
743#define E1000_82542_MANC E1000_MANC
744#define E1000_82542_IPAV E1000_IPAV
745#define E1000_82542_IP4AT E1000_IP4AT
746#define E1000_82542_IP6AT E1000_IP6AT
747#define E1000_82542_WUPL E1000_WUPL
748#define E1000_82542_WUPM E1000_WUPM
749#define E1000_82542_FFLT E1000_FFLT
750#define E1000_82542_FFMT E1000_FFMT
751#define E1000_82542_FFVT E1000_FFVT
752
753
754struct e1000_hw_stats {
755 uint64_t crcerrs;
756 uint64_t algnerrc;
757 uint64_t symerrs;
758 uint64_t rxerrc;
759 uint64_t mpc;
760 uint64_t scc;
761 uint64_t ecol;
762 uint64_t mcc;
763 uint64_t latecol;
764 uint64_t colc;
765 uint64_t dc;
766 uint64_t tncrs;
767 uint64_t sec;
768 uint64_t cexterr;
769 uint64_t rlec;
770 uint64_t xonrxc;
771 uint64_t xontxc;
772 uint64_t xoffrxc;
773 uint64_t xofftxc;
774 uint64_t fcruc;
775 uint64_t prc64;
776 uint64_t prc127;
777 uint64_t prc255;
778 uint64_t prc511;
779 uint64_t prc1023;
780 uint64_t prc1522;
781 uint64_t gprc;
782 uint64_t bprc;
783 uint64_t mprc;
784 uint64_t gptc;
785 uint64_t gorcl;
786 uint64_t gorch;
787 uint64_t gotcl;
788 uint64_t gotch;
789 uint64_t rnbc;
790 uint64_t ruc;
791 uint64_t rfc;
792 uint64_t roc;
793 uint64_t rjc;
794 uint64_t mgprc;
795 uint64_t mgpdc;
796 uint64_t mgptc;
797 uint64_t torl;
798 uint64_t torh;
799 uint64_t totl;
800 uint64_t toth;
801 uint64_t tpr;
802 uint64_t tpt;
803 uint64_t ptc64;
804 uint64_t ptc127;
805 uint64_t ptc255;
806 uint64_t ptc511;
807 uint64_t ptc1023;
808 uint64_t ptc1522;
809 uint64_t mptc;
810 uint64_t bptc;
811 uint64_t tsctc;
812 uint64_t tsctfc;
813};
814
815
816struct e1000_hw {
817 pci_dev_t pdev;
818 uint8_t *hw_addr;
819 e1000_mac_type mac_type;
820 e1000_phy_type phy_type;
821 uint32_t phy_init_script;
822 e1000_media_type media_type;
823 e1000_lan_loc lan_loc;
824 e1000_fc_type fc;
825#if 0
826 e1000_bus_speed bus_speed;
827 e1000_bus_width bus_width;
828 e1000_bus_type bus_type;
829 uint32_t io_base;
830#endif
831 uint32_t phy_id;
832 uint32_t phy_addr;
833 uint32_t original_fc;
834 uint32_t txcw;
835 uint32_t autoneg_failed;
836#if 0
837 uint32_t max_frame_size;
838 uint32_t min_frame_size;
839 uint32_t mc_filter_type;
840 uint32_t num_mc_addrs;
841 uint32_t collision_delta;
842 uint32_t tx_packet_delta;
843 uint32_t ledctl_default;
844 uint32_t ledctl_mode1;
845 uint32_t ledctl_mode2;
846#endif
847 uint16_t autoneg_advertised;
848 uint16_t pci_cmd_word;
849 uint16_t fc_high_water;
850 uint16_t fc_low_water;
851 uint16_t fc_pause_time;
852#if 0
853 uint16_t current_ifs_val;
854 uint16_t ifs_min_val;
855 uint16_t ifs_max_val;
856 uint16_t ifs_step_size;
857 uint16_t ifs_ratio;
858#endif
859 uint16_t device_id;
860 uint16_t vendor_id;
861 uint16_t subsystem_id;
862 uint16_t subsystem_vendor_id;
863 uint8_t revision_id;
864#if 0
865 uint8_t autoneg;
866 uint8_t mdix;
867 uint8_t forced_speed_duplex;
868 uint8_t wait_autoneg_complete;
869 uint8_t dma_fairness;
870#endif
871#if 0
872 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
873 boolean_t disable_polarity_correction;
874#endif
875 boolean_t get_link_status;
876 boolean_t tbi_compatibility_en;
877 boolean_t tbi_compatibility_on;
878 boolean_t fc_send_xon;
879 boolean_t report_tx_early;
880#if 0
881 boolean_t adaptive_ifs;
882 boolean_t ifs_params_forced;
883 boolean_t in_ifs_mode;
884#endif
885};
886
887#define E1000_EEPROM_SWDPIN0 0x0001
888#define E1000_EEPROM_LED_LOGIC 0x0020
889
890
891
892#define E1000_CTRL_FD 0x00000001
893#define E1000_CTRL_BEM 0x00000002
894#define E1000_CTRL_PRIOR 0x00000004
895#define E1000_CTRL_LRST 0x00000008
896#define E1000_CTRL_TME 0x00000010
897#define E1000_CTRL_SLE 0x00000020
898#define E1000_CTRL_ASDE 0x00000020
899#define E1000_CTRL_SLU 0x00000040
900#define E1000_CTRL_ILOS 0x00000080
901#define E1000_CTRL_SPD_SEL 0x00000300
902#define E1000_CTRL_SPD_10 0x00000000
903#define E1000_CTRL_SPD_100 0x00000100
904#define E1000_CTRL_SPD_1000 0x00000200
905#define E1000_CTRL_BEM32 0x00000400
906#define E1000_CTRL_FRCSPD 0x00000800
907#define E1000_CTRL_FRCDPX 0x00001000
908#define E1000_CTRL_SWDPIN0 0x00040000
909#define E1000_CTRL_SWDPIN1 0x00080000
910#define E1000_CTRL_SWDPIN2 0x00100000
911#define E1000_CTRL_SWDPIN3 0x00200000
912#define E1000_CTRL_SWDPIO0 0x00400000
913#define E1000_CTRL_SWDPIO1 0x00800000
914#define E1000_CTRL_SWDPIO2 0x01000000
915#define E1000_CTRL_SWDPIO3 0x02000000
916#define E1000_CTRL_RST 0x04000000
917#define E1000_CTRL_RFCE 0x08000000
918#define E1000_CTRL_TFCE 0x10000000
919#define E1000_CTRL_RTE 0x20000000
920#define E1000_CTRL_VME 0x40000000
921#define E1000_CTRL_PHY_RST 0x80000000
922
923
924#define E1000_STATUS_FD 0x00000001
925#define E1000_STATUS_LU 0x00000002
926#define E1000_STATUS_FUNC_MASK 0x0000000C
927#define E1000_STATUS_FUNC_0 0x00000000
928#define E1000_STATUS_FUNC_1 0x00000004
929#define E1000_STATUS_TXOFF 0x00000010
930#define E1000_STATUS_TBIMODE 0x00000020
931#define E1000_STATUS_SPEED_MASK 0x000000C0
932#define E1000_STATUS_SPEED_10 0x00000000
933#define E1000_STATUS_SPEED_100 0x00000040
934#define E1000_STATUS_SPEED_1000 0x00000080
935#define E1000_STATUS_ASDV 0x00000300
936#define E1000_STATUS_MTXCKOK 0x00000400
937#define E1000_STATUS_PCI66 0x00000800
938#define E1000_STATUS_BUS64 0x00001000
939#define E1000_STATUS_PCIX_MODE 0x00002000
940#define E1000_STATUS_PCIX_SPEED 0x0000C000
941
942
943#define E1000_STATUS_PCIX_SPEED_66 0x00000000
944#define E1000_STATUS_PCIX_SPEED_100 0x00004000
945#define E1000_STATUS_PCIX_SPEED_133 0x00008000
946
947
948#define E1000_EECD_SK 0x00000001
949#define E1000_EECD_CS 0x00000002
950#define E1000_EECD_DI 0x00000004
951#define E1000_EECD_DO 0x00000008
952#define E1000_EECD_FWE_MASK 0x00000030
953#define E1000_EECD_FWE_DIS 0x00000010
954#define E1000_EECD_FWE_EN 0x00000020
955#define E1000_EECD_FWE_SHIFT 4
956#define E1000_EECD_SIZE 0x00000200
957#define E1000_EECD_REQ 0x00000040
958#define E1000_EECD_GNT 0x00000080
959#define E1000_EECD_PRES 0x00000100
960
961
962#define E1000_EERD_START 0x00000001
963#define E1000_EERD_DONE 0x00000010
964#define E1000_EERD_ADDR_SHIFT 8
965#define E1000_EERD_ADDR_MASK 0x0000FF00
966#define E1000_EERD_DATA_SHIFT 16
967#define E1000_EERD_DATA_MASK 0xFFFF0000
968
969
970#define E1000_CTRL_EXT_GPI0_EN 0x00000001
971#define E1000_CTRL_EXT_GPI1_EN 0x00000002
972#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
973#define E1000_CTRL_EXT_GPI2_EN 0x00000004
974#define E1000_CTRL_EXT_GPI3_EN 0x00000008
975#define E1000_CTRL_EXT_SDP4_DATA 0x00000010
976#define E1000_CTRL_EXT_SDP5_DATA 0x00000020
977#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
978#define E1000_CTRL_EXT_SDP6_DATA 0x00000040
979#define E1000_CTRL_EXT_SWDPIN6 0x00000040
980#define E1000_CTRL_EXT_SDP7_DATA 0x00000080
981#define E1000_CTRL_EXT_SWDPIN7 0x00000080
982#define E1000_CTRL_EXT_SDP4_DIR 0x00000100
983#define E1000_CTRL_EXT_SDP5_DIR 0x00000200
984#define E1000_CTRL_EXT_SDP6_DIR 0x00000400
985#define E1000_CTRL_EXT_SWDPIO6 0x00000400
986#define E1000_CTRL_EXT_SDP7_DIR 0x00000800
987#define E1000_CTRL_EXT_SWDPIO7 0x00000800
988#define E1000_CTRL_EXT_ASDCHK 0x00001000
989#define E1000_CTRL_EXT_EE_RST 0x00002000
990#define E1000_CTRL_EXT_IPS 0x00004000
991#define E1000_CTRL_EXT_SPD_BYPS 0x00008000
992#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
993#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
994#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
995#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
996#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
997#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
998#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
999#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
1000
1001
1002#define E1000_MDIC_DATA_MASK 0x0000FFFF
1003#define E1000_MDIC_REG_MASK 0x001F0000
1004#define E1000_MDIC_REG_SHIFT 16
1005#define E1000_MDIC_PHY_MASK 0x03E00000
1006#define E1000_MDIC_PHY_SHIFT 21
1007#define E1000_MDIC_OP_WRITE 0x04000000
1008#define E1000_MDIC_OP_READ 0x08000000
1009#define E1000_MDIC_READY 0x10000000
1010#define E1000_MDIC_INT_EN 0x20000000
1011#define E1000_MDIC_ERROR 0x40000000
1012
1013
1014#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
1015#define E1000_LEDCTL_LED0_MODE_SHIFT 0
1016#define E1000_LEDCTL_LED0_IVRT 0x00000040
1017#define E1000_LEDCTL_LED0_BLINK 0x00000080
1018#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
1019#define E1000_LEDCTL_LED1_MODE_SHIFT 8
1020#define E1000_LEDCTL_LED1_IVRT 0x00004000
1021#define E1000_LEDCTL_LED1_BLINK 0x00008000
1022#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
1023#define E1000_LEDCTL_LED2_MODE_SHIFT 16
1024#define E1000_LEDCTL_LED2_IVRT 0x00400000
1025#define E1000_LEDCTL_LED2_BLINK 0x00800000
1026#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
1027#define E1000_LEDCTL_LED3_MODE_SHIFT 24
1028#define E1000_LEDCTL_LED3_IVRT 0x40000000
1029#define E1000_LEDCTL_LED3_BLINK 0x80000000
1030
1031#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
1032#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
1033#define E1000_LEDCTL_MODE_LINK_UP 0x2
1034#define E1000_LEDCTL_MODE_ACTIVITY 0x3
1035#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
1036#define E1000_LEDCTL_MODE_LINK_10 0x5
1037#define E1000_LEDCTL_MODE_LINK_100 0x6
1038#define E1000_LEDCTL_MODE_LINK_1000 0x7
1039#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
1040#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
1041#define E1000_LEDCTL_MODE_COLLISION 0xA
1042#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
1043#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
1044#define E1000_LEDCTL_MODE_PAUSED 0xD
1045#define E1000_LEDCTL_MODE_LED_ON 0xE
1046#define E1000_LEDCTL_MODE_LED_OFF 0xF
1047
1048
1049#define E1000_RAH_AV 0x80000000
1050
1051
1052#define E1000_ICR_TXDW 0x00000001
1053#define E1000_ICR_TXQE 0x00000002
1054#define E1000_ICR_LSC 0x00000004
1055#define E1000_ICR_RXSEQ 0x00000008
1056#define E1000_ICR_RXDMT0 0x00000010
1057#define E1000_ICR_RXO 0x00000040
1058#define E1000_ICR_RXT0 0x00000080
1059#define E1000_ICR_MDAC 0x00000200
1060#define E1000_ICR_RXCFG 0x00000400
1061#define E1000_ICR_GPI_EN0 0x00000800
1062#define E1000_ICR_GPI_EN1 0x00001000
1063#define E1000_ICR_GPI_EN2 0x00002000
1064#define E1000_ICR_GPI_EN3 0x00004000
1065#define E1000_ICR_TXD_LOW 0x00008000
1066#define E1000_ICR_SRPD 0x00010000
1067
1068
1069#define E1000_ICS_TXDW E1000_ICR_TXDW
1070#define E1000_ICS_TXQE E1000_ICR_TXQE
1071#define E1000_ICS_LSC E1000_ICR_LSC
1072#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ
1073#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0
1074#define E1000_ICS_RXO E1000_ICR_RXO
1075#define E1000_ICS_RXT0 E1000_ICR_RXT0
1076#define E1000_ICS_MDAC E1000_ICR_MDAC
1077#define E1000_ICS_RXCFG E1000_ICR_RXCFG
1078#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0
1079#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1
1080#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2
1081#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3
1082#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
1083#define E1000_ICS_SRPD E1000_ICR_SRPD
1084
1085
1086#define E1000_IMS_TXDW E1000_ICR_TXDW
1087#define E1000_IMS_TXQE E1000_ICR_TXQE
1088#define E1000_IMS_LSC E1000_ICR_LSC
1089#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ
1090#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0
1091#define E1000_IMS_RXO E1000_ICR_RXO
1092#define E1000_IMS_RXT0 E1000_ICR_RXT0
1093#define E1000_IMS_MDAC E1000_ICR_MDAC
1094#define E1000_IMS_RXCFG E1000_ICR_RXCFG
1095#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0
1096#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1
1097#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2
1098#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3
1099#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
1100#define E1000_IMS_SRPD E1000_ICR_SRPD
1101
1102
1103#define E1000_IMC_TXDW E1000_ICR_TXDW
1104#define E1000_IMC_TXQE E1000_ICR_TXQE
1105#define E1000_IMC_LSC E1000_ICR_LSC
1106#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ
1107#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0
1108#define E1000_IMC_RXO E1000_ICR_RXO
1109#define E1000_IMC_RXT0 E1000_ICR_RXT0
1110#define E1000_IMC_MDAC E1000_ICR_MDAC
1111#define E1000_IMC_RXCFG E1000_ICR_RXCFG
1112#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0
1113#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1
1114#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2
1115#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3
1116#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
1117#define E1000_IMC_SRPD E1000_ICR_SRPD
1118
1119
1120#define E1000_RCTL_RST 0x00000001
1121#define E1000_RCTL_EN 0x00000002
1122#define E1000_RCTL_SBP 0x00000004
1123#define E1000_RCTL_UPE 0x00000008
1124#define E1000_RCTL_MPE 0x00000010
1125#define E1000_RCTL_LPE 0x00000020
1126#define E1000_RCTL_LBM_NO 0x00000000
1127#define E1000_RCTL_LBM_MAC 0x00000040
1128#define E1000_RCTL_LBM_SLP 0x00000080
1129#define E1000_RCTL_LBM_TCVR 0x000000C0
1130#define E1000_RCTL_RDMTS_HALF 0x00000000
1131#define E1000_RCTL_RDMTS_QUAT 0x00000100
1132#define E1000_RCTL_RDMTS_EIGTH 0x00000200
1133#define E1000_RCTL_MO_SHIFT 12
1134#define E1000_RCTL_MO_0 0x00000000
1135#define E1000_RCTL_MO_1 0x00001000
1136#define E1000_RCTL_MO_2 0x00002000
1137#define E1000_RCTL_MO_3 0x00003000
1138#define E1000_RCTL_MDR 0x00004000
1139#define E1000_RCTL_BAM 0x00008000
1140
1141#define E1000_RCTL_SZ_2048 0x00000000
1142#define E1000_RCTL_SZ_1024 0x00010000
1143#define E1000_RCTL_SZ_512 0x00020000
1144#define E1000_RCTL_SZ_256 0x00030000
1145
1146#define E1000_RCTL_SZ_16384 0x00010000
1147#define E1000_RCTL_SZ_8192 0x00020000
1148#define E1000_RCTL_SZ_4096 0x00030000
1149#define E1000_RCTL_VFE 0x00040000
1150#define E1000_RCTL_CFIEN 0x00080000
1151#define E1000_RCTL_CFI 0x00100000
1152#define E1000_RCTL_DPF 0x00400000
1153#define E1000_RCTL_PMCF 0x00800000
1154#define E1000_RCTL_BSEX 0x02000000
1155
1156
1157#define E1000_RDT_DELAY 0x0000ffff
1158#define E1000_RDT_FPDB 0x80000000
1159#define E1000_RDLEN_LEN 0x0007ff80
1160#define E1000_RDH_RDH 0x0000ffff
1161#define E1000_RDT_RDT 0x0000ffff
1162
1163
1164#define E1000_FCRTH_RTH 0x0000FFF8
1165#define E1000_FCRTH_XFCE 0x80000000
1166#define E1000_FCRTL_RTL 0x0000FFF8
1167#define E1000_FCRTL_XONE 0x80000000
1168
1169
1170#define E1000_RXDCTL_PTHRESH 0x0000003F
1171#define E1000_RXDCTL_HTHRESH 0x00003F00
1172#define E1000_RXDCTL_WTHRESH 0x003F0000
1173#define E1000_RXDCTL_GRAN 0x01000000
1174
1175
1176#define E1000_TXDCTL_PTHRESH 0x000000FF
1177#define E1000_TXDCTL_HTHRESH 0x0000FF00
1178#define E1000_TXDCTL_WTHRESH 0x00FF0000
1179#define E1000_TXDCTL_GRAN 0x01000000
1180#define E1000_TXDCTL_LWTHRESH 0xFE000000
1181#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000
1182
1183
1184#define E1000_TXCW_FD 0x00000020
1185#define E1000_TXCW_HD 0x00000040
1186#define E1000_TXCW_PAUSE 0x00000080
1187#define E1000_TXCW_ASM_DIR 0x00000100
1188#define E1000_TXCW_PAUSE_MASK 0x00000180
1189#define E1000_TXCW_RF 0x00003000
1190#define E1000_TXCW_NP 0x00008000
1191#define E1000_TXCW_CW 0x0000ffff
1192#define E1000_TXCW_TXC 0x40000000
1193#define E1000_TXCW_ANE 0x80000000
1194
1195
1196#define E1000_RXCW_CW 0x0000ffff
1197#define E1000_RXCW_NC 0x04000000
1198#define E1000_RXCW_IV 0x08000000
1199#define E1000_RXCW_CC 0x10000000
1200#define E1000_RXCW_C 0x20000000
1201#define E1000_RXCW_SYNCH 0x40000000
1202#define E1000_RXCW_ANC 0x80000000
1203
1204
1205#define E1000_TCTL_RST 0x00000001
1206#define E1000_TCTL_EN 0x00000002
1207#define E1000_TCTL_BCE 0x00000004
1208#define E1000_TCTL_PSP 0x00000008
1209#define E1000_TCTL_CT 0x00000ff0
1210#define E1000_TCTL_COLD 0x003ff000
1211#define E1000_TCTL_SWXOFF 0x00400000
1212#define E1000_TCTL_PBE 0x00800000
1213#define E1000_TCTL_RTLC 0x01000000
1214#define E1000_TCTL_NRTU 0x02000000
1215
1216
1217#define E1000_RXCSUM_PCSS_MASK 0x000000FF
1218#define E1000_RXCSUM_IPOFL 0x00000100
1219#define E1000_RXCSUM_TUOFL 0x00000200
1220#define E1000_RXCSUM_IPV6OFL 0x00000400
1221
1222
1223
1224#define E1000_WUC_APME 0x00000001
1225#define E1000_WUC_PME_EN 0x00000002
1226#define E1000_WUC_PME_STATUS 0x00000004
1227#define E1000_WUC_APMPME 0x00000008
1228
1229
1230#define E1000_WUFC_LNKC 0x00000001
1231#define E1000_WUFC_MAG 0x00000002
1232#define E1000_WUFC_EX 0x00000004
1233#define E1000_WUFC_MC 0x00000008
1234#define E1000_WUFC_BC 0x00000010
1235#define E1000_WUFC_ARP 0x00000020
1236#define E1000_WUFC_IPV4 0x00000040
1237#define E1000_WUFC_IPV6 0x00000080
1238#define E1000_WUFC_FLX0 0x00010000
1239#define E1000_WUFC_FLX1 0x00020000
1240#define E1000_WUFC_FLX2 0x00040000
1241#define E1000_WUFC_FLX3 0x00080000
1242#define E1000_WUFC_ALL_FILTERS 0x000F00FF
1243#define E1000_WUFC_FLX_OFFSET 16
1244#define E1000_WUFC_FLX_FILTERS 0x000F0000
1245
1246
1247#define E1000_WUS_LNKC 0x00000001
1248#define E1000_WUS_MAG 0x00000002
1249#define E1000_WUS_EX 0x00000004
1250#define E1000_WUS_MC 0x00000008
1251#define E1000_WUS_BC 0x00000010
1252#define E1000_WUS_ARP 0x00000020
1253#define E1000_WUS_IPV4 0x00000040
1254#define E1000_WUS_IPV6 0x00000080
1255#define E1000_WUS_FLX0 0x00010000
1256#define E1000_WUS_FLX1 0x00020000
1257#define E1000_WUS_FLX2 0x00040000
1258#define E1000_WUS_FLX3 0x00080000
1259#define E1000_WUS_FLX_FILTERS 0x000F0000
1260
1261
1262#define E1000_MANC_SMBUS_EN 0x00000001
1263#define E1000_MANC_ASF_EN 0x00000002
1264#define E1000_MANC_R_ON_FORCE 0x00000004
1265#define E1000_MANC_RMCP_EN 0x00000100
1266#define E1000_MANC_0298_EN 0x00000200
1267#define E1000_MANC_IPV4_EN 0x00000400
1268#define E1000_MANC_IPV6_EN 0x00000800
1269#define E1000_MANC_SNAP_EN 0x00001000
1270#define E1000_MANC_ARP_EN 0x00002000
1271#define E1000_MANC_NEIGHBOR_EN 0x00004000
1272
1273#define E1000_MANC_TCO_RESET 0x00010000
1274#define E1000_MANC_RCV_TCO_EN 0x00020000
1275#define E1000_MANC_REPORT_STATUS 0x00040000
1276#define E1000_MANC_SMB_REQ 0x01000000
1277#define E1000_MANC_SMB_GNT 0x02000000
1278#define E1000_MANC_SMB_CLK_IN 0x04000000
1279#define E1000_MANC_SMB_DATA_IN 0x08000000
1280#define E1000_MANC_SMB_DATA_OUT 0x10000000
1281#define E1000_MANC_SMB_CLK_OUT 0x20000000
1282
1283#define E1000_MANC_SMB_DATA_OUT_SHIFT 28
1284#define E1000_MANC_SMB_CLK_OUT_SHIFT 29
1285
1286
1287#define E1000_WUPL_LENGTH_MASK 0x0FFF
1288
1289#define E1000_MDALIGN 4096
1290
1291
1292#define EEPROM_READ_OPCODE 0x6
1293#define EEPROM_WRITE_OPCODE 0x5
1294#define EEPROM_ERASE_OPCODE 0x7
1295#define EEPROM_EWEN_OPCODE 0x13
1296#define EEPROM_EWDS_OPCODE 0x10
1297
1298
1299#define EEPROM_COMPAT 0x0003
1300#define EEPROM_ID_LED_SETTINGS 0x0004
1301#define EEPROM_INIT_CONTROL1_REG 0x000A
1302#define EEPROM_INIT_CONTROL2_REG 0x000F
1303#define EEPROM_FLASH_VERSION 0x0032
1304#define EEPROM_CHECKSUM_REG 0x003F
1305
1306
1307#define ID_LED_RESERVED_0000 0x0000
1308#define ID_LED_RESERVED_FFFF 0xFFFF
1309#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
1310 (ID_LED_OFF1_OFF2 << 8) | \
1311 (ID_LED_DEF1_DEF2 << 4) | \
1312 (ID_LED_DEF1_DEF2))
1313#define ID_LED_DEF1_DEF2 0x1
1314#define ID_LED_DEF1_ON2 0x2
1315#define ID_LED_DEF1_OFF2 0x3
1316#define ID_LED_ON1_DEF2 0x4
1317#define ID_LED_ON1_ON2 0x5
1318#define ID_LED_ON1_OFF2 0x6
1319#define ID_LED_OFF1_DEF2 0x7
1320#define ID_LED_OFF1_ON2 0x8
1321#define ID_LED_OFF1_OFF2 0x9
1322
1323
1324#define EEPROM_COMPAT_SERVER 0x0400
1325#define EEPROM_COMPAT_CLIENT 0x0200
1326
1327
1328#define EEPROM_WORD0A_ILOS 0x0010
1329#define EEPROM_WORD0A_SWDPIO 0x01E0
1330#define EEPROM_WORD0A_LRST 0x0200
1331#define EEPROM_WORD0A_FD 0x0400
1332#define EEPROM_WORD0A_66MHZ 0x0800
1333
1334
1335#define EEPROM_WORD0F_PAUSE_MASK 0x3000
1336#define EEPROM_WORD0F_PAUSE 0x1000
1337#define EEPROM_WORD0F_ASM_DIR 0x2000
1338#define EEPROM_WORD0F_ANE 0x0800
1339#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
1340
1341
1342#define EEPROM_SUM 0xBABA
1343
1344
1345#define EEPROM_NODE_ADDRESS_BYTE_0 0
1346#define EEPROM_PBA_BYTE_1 8
1347
1348
1349#define PBA_SIZE 4
1350
1351
1352#define E1000_COLLISION_THRESHOLD 16
1353#define E1000_CT_SHIFT 4
1354#define E1000_COLLISION_DISTANCE 64
1355#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
1356#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
1357#define E1000_GB_HDX_COLLISION_DISTANCE 512
1358#define E1000_COLD_SHIFT 12
1359
1360
1361#define REQ_TX_DESCRIPTOR_MULTIPLE 8
1362#define REQ_RX_DESCRIPTOR_MULTIPLE 8
1363
1364
1365#define DEFAULT_82542_TIPG_IPGT 10
1366#define DEFAULT_82543_TIPG_IPGT_FIBER 9
1367#define DEFAULT_82543_TIPG_IPGT_COPPER 8
1368
1369#define E1000_TIPG_IPGT_MASK 0x000003FF
1370#define E1000_TIPG_IPGR1_MASK 0x000FFC00
1371#define E1000_TIPG_IPGR2_MASK 0x3FF00000
1372
1373#define DEFAULT_82542_TIPG_IPGR1 2
1374#define DEFAULT_82543_TIPG_IPGR1 8
1375#define E1000_TIPG_IPGR1_SHIFT 10
1376
1377#define DEFAULT_82542_TIPG_IPGR2 10
1378#define DEFAULT_82543_TIPG_IPGR2 6
1379#define E1000_TIPG_IPGR2_SHIFT 20
1380
1381#define E1000_TXDMAC_DPP 0x00000001
1382
1383
1384#define TX_THRESHOLD_START 8
1385#define TX_THRESHOLD_INCREMENT 10
1386#define TX_THRESHOLD_DECREMENT 1
1387#define TX_THRESHOLD_STOP 190
1388#define TX_THRESHOLD_DISABLE 0
1389#define TX_THRESHOLD_TIMER_MS 10000
1390#define MIN_NUM_XMITS 1000
1391#define IFS_MAX 80
1392#define IFS_STEP 10
1393#define IFS_MIN 40
1394#define IFS_RATIO 4
1395
1396
1397#define E1000_PBA_16K 0x0010
1398#define E1000_PBA_24K 0x0018
1399#define E1000_PBA_40K 0x0028
1400#define E1000_PBA_48K 0x0030
1401
1402
1403#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
1404#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
1405#define FLOW_CONTROL_TYPE 0x8808
1406
1407
1408#define FC_DEFAULT_HI_THRESH (0x8000)
1409#define FC_DEFAULT_LO_THRESH (0x4000)
1410#define FC_DEFAULT_TX_TIMER (0x100)
1411
1412
1413#define E1000_FC_HIGH_THRESH 0xA9C8
1414
1415#define E1000_FC_LOW_THRESH 0xA9C0
1416
1417#define E1000_FC_PAUSE_TIME 0x0680
1418
1419
1420#define PCIX_COMMAND_REGISTER 0xE6
1421#define PCIX_STATUS_REGISTER_LO 0xE8
1422#define PCIX_STATUS_REGISTER_HI 0xEA
1423
1424#define PCIX_COMMAND_MMRBC_MASK 0x000C
1425#define PCIX_COMMAND_MMRBC_SHIFT 0x2
1426#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
1427#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
1428#define PCIX_STATUS_HI_MMRBC_4K 0x3
1429#define PCIX_STATUS_HI_MMRBC_2K 0x2
1430
1431
1432
1433
1434
1435#define PAUSE_SHIFT 5
1436
1437
1438
1439
1440
1441#define SWDPIO_SHIFT 17
1442
1443
1444
1445
1446
1447
1448#define SWDPIO__EXT_SHIFT 4
1449
1450
1451
1452
1453
1454#define ILOS_SHIFT 3
1455
1456#define RECEIVE_BUFFER_ALIGN_SIZE (256)
1457
1458
1459#define LINK_UP_TIMEOUT 500
1460
1461#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
1462
1463
1464#define CARRIER_EXTENSION 0x0F
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
1494 ((adapter)->tbi_compatibility_on && \
1495 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
1496 ((last_byte) == CARRIER_EXTENSION) && \
1497 (((status) & E1000_RXD_STAT_VP) ? \
1498 (((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
1499 ((length) <= ((adapter)->max_frame_size + 1))) : \
1500 (((length) > (adapter)->min_frame_size) && \
1501 ((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
1502
1503
1504
1505
1506
1507
1508#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
1509#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
1510#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
1511#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
1512#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
1513#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
1514#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
1515#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
1516
1517
1518
1519#define PHY_CTRL 0x00
1520#define PHY_STATUS 0x01
1521#define PHY_ID1 0x02
1522#define PHY_ID2 0x03
1523#define PHY_AUTONEG_ADV 0x04
1524#define PHY_LP_ABILITY 0x05
1525#define PHY_AUTONEG_EXP 0x06
1526#define PHY_NEXT_PAGE_TX 0x07
1527#define PHY_LP_NEXT_PAGE 0x08
1528#define PHY_1000T_CTRL 0x09
1529#define PHY_1000T_STATUS 0x0A
1530#define PHY_EXT_STATUS 0x0F
1531
1532
1533#define M88E1000_PHY_SPEC_CTRL 0x10
1534#define M88E1000_PHY_SPEC_STATUS 0x11
1535#define M88E1000_INT_ENABLE 0x12
1536#define M88E1000_INT_STATUS 0x13
1537#define M88E1000_EXT_PHY_SPEC_CTRL 0x14
1538#define M88E1000_RX_ERR_CNTR 0x15
1539
1540#define MAX_PHY_REG_ADDRESS 0x1F
1541
1542
1543#define IGP01E1000_IEEE_REGS_PAGE 0x0000
1544#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
1545#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
1546
1547
1548#define IGP01E1000_PHY_PORT_CONFIG 0x10
1549#define IGP01E1000_PHY_PORT_STATUS 0x11
1550#define IGP01E1000_PHY_PORT_CTRL 0x12
1551#define IGP01E1000_PHY_LINK_HEALTH 0x13
1552#define IGP01E1000_GMII_FIFO 0x14
1553#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15
1554#define IGP02E1000_PHY_POWER_MGMT 0x19
1555#define IGP01E1000_PHY_PAGE_SELECT 0x1F
1556
1557
1558#define MII_CR_SPEED_SELECT_MSB 0x0040
1559#define MII_CR_COLL_TEST_ENABLE 0x0080
1560#define MII_CR_FULL_DUPLEX 0x0100
1561#define MII_CR_RESTART_AUTO_NEG 0x0200
1562#define MII_CR_ISOLATE 0x0400
1563#define MII_CR_POWER_DOWN 0x0800
1564#define MII_CR_AUTO_NEG_EN 0x1000
1565#define MII_CR_SPEED_SELECT_LSB 0x2000
1566#define MII_CR_LOOPBACK 0x4000
1567#define MII_CR_RESET 0x8000
1568
1569
1570#define MII_SR_EXTENDED_CAPS 0x0001
1571#define MII_SR_JABBER_DETECT 0x0002
1572#define MII_SR_LINK_STATUS 0x0004
1573#define MII_SR_AUTONEG_CAPS 0x0008
1574#define MII_SR_REMOTE_FAULT 0x0010
1575#define MII_SR_AUTONEG_COMPLETE 0x0020
1576#define MII_SR_PREAMBLE_SUPPRESS 0x0040
1577#define MII_SR_EXTENDED_STATUS 0x0100
1578#define MII_SR_100T2_HD_CAPS 0x0200
1579#define MII_SR_100T2_FD_CAPS 0x0400
1580#define MII_SR_10T_HD_CAPS 0x0800
1581#define MII_SR_10T_FD_CAPS 0x1000
1582#define MII_SR_100X_HD_CAPS 0x2000
1583#define MII_SR_100X_FD_CAPS 0x4000
1584#define MII_SR_100T4_CAPS 0x8000
1585
1586
1587#define NWAY_AR_SELECTOR_FIELD 0x0001
1588#define NWAY_AR_10T_HD_CAPS 0x0020
1589#define NWAY_AR_10T_FD_CAPS 0x0040
1590#define NWAY_AR_100TX_HD_CAPS 0x0080
1591#define NWAY_AR_100TX_FD_CAPS 0x0100
1592#define NWAY_AR_100T4_CAPS 0x0200
1593#define NWAY_AR_PAUSE 0x0400
1594#define NWAY_AR_ASM_DIR 0x0800
1595#define NWAY_AR_REMOTE_FAULT 0x2000
1596#define NWAY_AR_NEXT_PAGE 0x8000
1597
1598
1599#define NWAY_LPAR_SELECTOR_FIELD 0x0000
1600#define NWAY_LPAR_10T_HD_CAPS 0x0020
1601#define NWAY_LPAR_10T_FD_CAPS 0x0040
1602#define NWAY_LPAR_100TX_HD_CAPS 0x0080
1603#define NWAY_LPAR_100TX_FD_CAPS 0x0100
1604#define NWAY_LPAR_100T4_CAPS 0x0200
1605#define NWAY_LPAR_PAUSE 0x0400
1606#define NWAY_LPAR_ASM_DIR 0x0800
1607#define NWAY_LPAR_REMOTE_FAULT 0x2000
1608#define NWAY_LPAR_ACKNOWLEDGE 0x4000
1609#define NWAY_LPAR_NEXT_PAGE 0x8000
1610
1611
1612#define NWAY_ER_LP_NWAY_CAPS 0x0001
1613#define NWAY_ER_PAGE_RXD 0x0002
1614#define NWAY_ER_NEXT_PAGE_CAPS 0x0004
1615#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008
1616#define NWAY_ER_PAR_DETECT_FAULT 0x0100
1617
1618
1619#define NPTX_MSG_CODE_FIELD 0x0001
1620#define NPTX_TOGGLE 0x0800
1621
1622
1623#define NPTX_ACKNOWLDGE2 0x1000
1624
1625
1626#define NPTX_MSG_PAGE 0x2000
1627#define NPTX_NEXT_PAGE 0x8000
1628
1629
1630
1631
1632#define LP_RNPR_MSG_CODE_FIELD 0x0001
1633#define LP_RNPR_TOGGLE 0x0800
1634
1635
1636#define LP_RNPR_ACKNOWLDGE2 0x1000
1637
1638
1639#define LP_RNPR_MSG_PAGE 0x2000
1640#define LP_RNPR_ACKNOWLDGE 0x4000
1641#define LP_RNPR_NEXT_PAGE 0x8000
1642
1643
1644
1645
1646#define CR_1000T_ASYM_PAUSE 0x0080
1647#define CR_1000T_HD_CAPS 0x0100
1648#define CR_1000T_FD_CAPS 0x0200
1649#define CR_1000T_REPEATER_DTE 0x0400
1650
1651#define CR_1000T_MS_VALUE 0x0800
1652
1653#define CR_1000T_MS_ENABLE 0x1000
1654
1655#define CR_1000T_TEST_MODE_NORMAL 0x0000
1656#define CR_1000T_TEST_MODE_1 0x2000
1657#define CR_1000T_TEST_MODE_2 0x4000
1658#define CR_1000T_TEST_MODE_3 0x6000
1659#define CR_1000T_TEST_MODE_4 0x8000
1660
1661
1662#define SR_1000T_IDLE_ERROR_CNT 0x00FF
1663#define SR_1000T_ASYM_PAUSE_DIR 0x0100
1664#define SR_1000T_LP_HD_CAPS 0x0400
1665#define SR_1000T_LP_FD_CAPS 0x0800
1666#define SR_1000T_REMOTE_RX_STATUS 0x1000
1667#define SR_1000T_LOCAL_RX_STATUS 0x2000
1668#define SR_1000T_MS_CONFIG_RES 0x4000
1669#define SR_1000T_MS_CONFIG_FAULT 0x8000
1670#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
1671#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
1672
1673
1674#define IEEE_ESR_1000T_HD_CAPS 0x1000
1675#define IEEE_ESR_1000T_FD_CAPS 0x2000
1676#define IEEE_ESR_1000X_HD_CAPS 0x4000
1677#define IEEE_ESR_1000X_FD_CAPS 0x8000
1678
1679#define PHY_TX_POLARITY_MASK 0x0100
1680#define PHY_TX_NORMAL_POLARITY 0
1681
1682#define AUTO_POLARITY_DISABLE 0x0010
1683
1684
1685
1686#define M88E1000_PSCR_JABBER_DISABLE 0x0001
1687#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002
1688#define M88E1000_PSCR_SQE_TEST 0x0004
1689#define M88E1000_PSCR_CLK125_DISABLE 0x0010
1690
1691
1692#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000
1693
1694#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020
1695#define M88E1000_PSCR_AUTO_X_1000T 0x0040
1696
1697
1698
1699#define M88E1000_PSCR_AUTO_X_MODE 0x0060
1700
1701
1702#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
1703
1704
1705
1706#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
1707
1708
1709#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200
1710#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400
1711#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800
1712
1713#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
1714#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
1715#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
1716
1717
1718#define M88E1000_PSSR_JABBER 0x0001
1719#define M88E1000_PSSR_REV_POLARITY 0x0002
1720#define M88E1000_PSSR_MDIX 0x0040
1721#define M88E1000_PSSR_CABLE_LENGTH 0x0380
1722
1723#define M88E1000_PSSR_LINK 0x0400
1724#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800
1725#define M88E1000_PSSR_PAGE_RCVD 0x1000
1726#define M88E1000_PSSR_DPLX 0x2000
1727#define M88E1000_PSSR_SPEED 0xC000
1728#define M88E1000_PSSR_10MBS 0x0000
1729#define M88E1000_PSSR_100MBS 0x4000
1730#define M88E1000_PSSR_1000MBS 0x8000
1731
1732#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
1733#define M88E1000_PSSR_MDIX_SHIFT 6
1734#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
1735
1736
1737#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000
1738#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000
1739
1740
1741
1742
1743
1744
1745#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
1746#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
1747#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
1748#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
1749#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
1750
1751
1752#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
1753#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
1754#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
1755#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
1756#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
1757#define M88E1000_EPSCR_TX_CLK_2_5 0x0060
1758#define M88E1000_EPSCR_TX_CLK_25 0x0070
1759#define M88E1000_EPSCR_TX_CLK_0 0x0000
1760
1761
1762#define M88E1000_E_PHY_ID 0x01410C50
1763#define M88E1000_I_PHY_ID 0x01410C30
1764#define M88E1011_I_PHY_ID 0x01410C20
1765#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
1766#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
1767#define IGP01E1000_I_PHY_ID 0x02A80380
1768
1769
1770#define PHY_PREAMBLE 0xFFFFFFFF
1771#define PHY_SOF 0x01
1772#define PHY_OP_READ 0x02
1773#define PHY_OP_WRITE 0x01
1774#define PHY_TURNAROUND 0x02
1775#define PHY_PREAMBLE_SIZE 32
1776#define MII_CR_SPEED_1000 0x0040
1777#define MII_CR_SPEED_100 0x2000
1778#define MII_CR_SPEED_10 0x0000
1779#define E1000_PHY_ADDRESS 0x01
1780#define PHY_AUTO_NEG_TIME 45
1781#define PHY_FORCE_TIME 20
1782#define PHY_REVISION_MASK 0xFFFFFFF0
1783#define DEVICE_SPEED_MASK 0x00000300
1784#define REG4_SPEED_MASK 0x01E0
1785#define REG9_SPEED_MASK 0x0300
1786#define ADVERTISE_10_HALF 0x0001
1787#define ADVERTISE_10_FULL 0x0002
1788#define ADVERTISE_100_HALF 0x0004
1789#define ADVERTISE_100_FULL 0x0008
1790#define ADVERTISE_1000_HALF 0x0010
1791#define ADVERTISE_1000_FULL 0x0020
1792#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F
1793
1794#endif
1795