1/* 2 * (C) Copyright 2003 - 2007 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * Derived from the MPC8xx driver's header file. 6 */ 7 8#ifndef __MPC512X_FEC_H 9#define __MPC512X_FEC_H 10 11#include <common.h> 12#include <mpc512x.h> 13 14typedef unsigned long uint32; 15typedef unsigned short uint16; 16typedef unsigned char uint8; 17 18typedef struct ethernet_register_set { 19 20/* [10:2]addr = 00 */ 21 22/* Control and status Registers (offset 000-1FF) */ 23 24 volatile uint32 fec_id; /* MBAR_ETH + 0x000 */ 25 volatile uint32 ievent; /* MBAR_ETH + 0x004 */ 26 volatile uint32 imask; /* MBAR_ETH + 0x008 */ 27 28 volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */ 29 volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */ 30 volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */ 31 32 volatile uint32 RES1[3]; /* MBAR_ETH + 0x018-020 */ 33 volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */ 34 35 volatile uint32 RES2[6]; /* MBAR_ETH + 0x028-03C */ 36 volatile uint32 mii_data; /* MBAR_ETH + 0x040 */ 37 volatile uint32 mii_speed; /* MBAR_ETH + 0x044 */ 38 39 volatile uint32 RES3[7]; /* MBAR_ETH + 0x048-060 */ 40 volatile uint32 mib_control; /* MBAR_ETH + 0x064 */ 41 42 volatile uint32 RES4[7]; /* MBAR_ETH + 0x068-80 */ 43 volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */ 44 volatile uint32 r_hash; /* MBAR_ETH + 0x088 */ 45 46 volatile uint32 RES5[14]; /* MBAR_ETH + 0x08c-0C0 */ 47 volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */ 48 49 volatile uint32 RES6[7]; /* MBAR_ETH + 0x0C8-0E0 */ 50 volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */ 51 volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */ 52 volatile uint32 op_pause; /* MBAR_ETH + 0x0EC */ 53 54 volatile uint32 RES7[10]; /* MBAR_ETH + 0x0F0-114 */ 55 volatile uint32 iaddr1; /* MBAR_ETH + 0x118 */ 56 volatile uint32 iaddr2; /* MBAR_ETH + 0x11C */ 57 volatile uint32 gaddr1; /* MBAR_ETH + 0x120 */ 58 volatile uint32 gaddr2; /* MBAR_ETH + 0x124 */ 59 60 volatile uint32 RES8[6]; /* MBAR_ETH + 0x128-13C */ 61 volatile uint32 fifo_id; /* MBAR_ETH + 0x140 */ 62 volatile uint32 x_wmrk; /* MBAR_ETH + 0x144 */ 63 volatile uint32 RES9[1]; /* MBAR_ETH + 0x148 */ 64 volatile uint32 r_bound; /* MBAR_ETH + 0x14C */ 65 volatile uint32 r_fstart; /* MBAR_ETH + 0x150 */ 66 67 volatile uint32 RES10[11]; /* MBAR_ETH + 0x154-17C */ 68 volatile uint32 r_des_start; /* MBAR_ETH + 0x180 */ 69 volatile uint32 x_des_start; /* MBAR_ETH + 0x184 */ 70 volatile uint32 r_buff_size; /* MBAR_ETH + 0x188 */ 71 volatile uint32 RES11[26]; /* MBAR_ETH + 0x18C-1F0 */ 72 volatile uint32 dma_control; /* MBAR_ETH + 0x1F4 */ 73 volatile uint32 RES12[2]; /* MBAR_ETH + 0x1F8-1FC */ 74 75/* MIB COUNTERS (Offset 200-2FF) */ 76 77 volatile uint32 rmon_t_drop; /* MBAR_ETH + 0x200 */ 78 volatile uint32 rmon_t_packets; /* MBAR_ETH + 0x204 */ 79 volatile uint32 rmon_t_bc_pkt; /* MBAR_ETH + 0x208 */ 80 volatile uint32 rmon_t_mc_pkt; /* MBAR_ETH + 0x20C */ 81 volatile uint32 rmon_t_crc_align; /* MBAR_ETH + 0x210 */ 82 volatile uint32 rmon_t_undersize; /* MBAR_ETH + 0x214 */ 83 volatile uint32 rmon_t_oversize; /* MBAR_ETH + 0x218 */ 84 volatile uint32 rmon_t_frag; /* MBAR_ETH + 0x21C */ 85 volatile uint32 rmon_t_jab; /* MBAR_ETH + 0x220 */ 86 volatile uint32 rmon_t_col; /* MBAR_ETH + 0x224 */ 87 volatile uint32 rmon_t_p64; /* MBAR_ETH + 0x228 */ 88 volatile uint32 rmon_t_p65to127; /* MBAR_ETH + 0x22C */ 89 volatile uint32 rmon_t_p128to255; /* MBAR_ETH + 0x230 */ 90 volatile uint32 rmon_t_p256to511; /* MBAR_ETH + 0x234 */ 91 volatile uint32 rmon_t_p512to1023; /* MBAR_ETH + 0x238 */ 92 volatile uint32 rmon_t_p1024to2047; /* MBAR_ETH + 0x23C */ 93 volatile uint32 rmon_t_p_gte2048; /* MBAR_ETH + 0x240 */ 94 volatile uint32 rmon_t_octets; /* MBAR_ETH + 0x244 */ 95 volatile uint32 ieee_t_drop; /* MBAR_ETH + 0x248 */ 96 volatile uint32 ieee_t_frame_ok; /* MBAR_ETH + 0x24C */ 97 volatile uint32 ieee_t_1col; /* MBAR_ETH + 0x250 */ 98 volatile uint32 ieee_t_mcol; /* MBAR_ETH + 0x254 */ 99 volatile uint32 ieee_t_def; /* MBAR_ETH + 0x258 */ 100 volatile uint32 ieee_t_lcol; /* MBAR_ETH + 0x25C */ 101 volatile uint32 ieee_t_excol; /* MBAR_ETH + 0x260 */ 102 volatile uint32 ieee_t_macerr; /* MBAR_ETH + 0x264 */ 103 volatile uint32 ieee_t_cserr; /* MBAR_ETH + 0x268 */ 104 volatile uint32 ieee_t_sqe; /* MBAR_ETH + 0x26C */ 105 volatile uint32 t_fdxfc; /* MBAR_ETH + 0x270 */ 106 volatile uint32 ieee_t_octets_ok; /* MBAR_ETH + 0x274 */ 107 108 volatile uint32 RES13[2]; /* MBAR_ETH + 0x278-27C */ 109 volatile uint32 rmon_r_drop; /* MBAR_ETH + 0x280 */ 110 volatile uint32 rmon_r_packets; /* MBAR_ETH + 0x284 */ 111 volatile uint32 rmon_r_bc_pkt; /* MBAR_ETH + 0x288 */ 112 volatile uint32 rmon_r_mc_pkt; /* MBAR_ETH + 0x28C */ 113 volatile uint32 rmon_r_crc_align; /* MBAR_ETH + 0x290 */ 114 volatile uint32 rmon_r_undersize; /* MBAR_ETH + 0x294 */ 115 volatile uint32 rmon_r_oversize; /* MBAR_ETH + 0x298 */ 116 volatile uint32 rmon_r_frag; /* MBAR_ETH + 0x29C */ 117 volatile uint32 rmon_r_jab; /* MBAR_ETH + 0x2A0 */ 118 119 volatile uint32 rmon_r_resvd_0; /* MBAR_ETH + 0x2A4 */ 120 121 volatile uint32 rmon_r_p64; /* MBAR_ETH + 0x2A8 */ 122 volatile uint32 rmon_r_p65to127; /* MBAR_ETH + 0x2AC */ 123 volatile uint32 rmon_r_p128to255; /* MBAR_ETH + 0x2B0 */ 124 volatile uint32 rmon_r_p256to511; /* MBAR_ETH + 0x2B4 */ 125 volatile uint32 rmon_r_p512to1023; /* MBAR_ETH + 0x2B8 */ 126 volatile uint32 rmon_r_p1024to2047; /* MBAR_ETH + 0x2BC */ 127 volatile uint32 rmon_r_p_gte2048; /* MBAR_ETH + 0x2C0 */ 128 volatile uint32 rmon_r_octets; /* MBAR_ETH + 0x2C4 */ 129 volatile uint32 ieee_r_drop; /* MBAR_ETH + 0x2C8 */ 130 volatile uint32 ieee_r_frame_ok; /* MBAR_ETH + 0x2CC */ 131 volatile uint32 ieee_r_crc; /* MBAR_ETH + 0x2D0 */ 132 volatile uint32 ieee_r_align; /* MBAR_ETH + 0x2D4 */ 133 volatile uint32 r_macerr; /* MBAR_ETH + 0x2D8 */ 134 volatile uint32 r_fdxfc; /* MBAR_ETH + 0x2DC */ 135 volatile uint32 ieee_r_octets_ok; /* MBAR_ETH + 0x2E0 */ 136 137 volatile uint32 RES14[6]; /* MBAR_ETH + 0x2E4-2FC */ 138 139 volatile uint32 RES15[64]; /* MBAR_ETH + 0x300-3FF */ 140} ethernet_regs; 141 142/* Receive & Transmit Buffer Descriptor definitions */ 143typedef struct BufferDescriptor { 144 uint16 status; 145 uint16 dataLength; 146 uint32 dataPointer; 147} FEC_RBD; 148 149typedef struct { 150 uint16 status; 151 uint16 dataLength; 152 uint32 dataPointer; 153} FEC_TBD; 154 155/* private structure */ 156typedef enum { 157 SEVENWIRE, /* 7-wire */ 158 MII10, /* MII 10Mbps */ 159 MII100 /* MII 100Mbps */ 160} xceiver_type; 161 162/* BD Numer definitions */ 163#define FEC_TBD_NUM 48 /* The user can adjust this value */ 164#define FEC_RBD_NUM 32 /* The user can adjust this value */ 165 166/* packet size limit */ 167#define FEC_MAX_FRAME_LEN 1522 /* recommended default value */ 168 169/* Buffer size must be evenly divisible by 16 */ 170#define FEC_BUFFER_SIZE ((FEC_MAX_FRAME_LEN + 0x10) & (~0xf)) 171 172typedef struct { 173 uint8 frame[FEC_BUFFER_SIZE]; 174} mpc512x_frame; 175 176typedef struct { 177 FEC_RBD rbd[FEC_RBD_NUM]; /* RBD ring */ 178 FEC_TBD tbd[FEC_TBD_NUM]; /* TBD ring */ 179 mpc512x_frame recv_frames[FEC_RBD_NUM]; /* receive buff */ 180} mpc512x_buff_descs; 181 182typedef struct { 183 ethernet_regs *eth; 184 xceiver_type xcv_type; /* transceiver type */ 185 mpc512x_buff_descs *bdBase; /* BD rings and recv buffer */ 186 uint16 rbdIndex; /* next receive BD to read */ 187 uint16 tbdIndex; /* next transmit BD to send */ 188 uint16 usedTbdIndex; /* next transmit BD to clean */ 189 uint16 cleanTbdNum; /* the number of available transmit BDs */ 190} mpc512x_fec_priv; 191 192/* RBD bits definitions */ 193#define FEC_RBD_EMPTY 0x8000 /* Buffer is empty */ 194#define FEC_RBD_WRAP 0x2000 /* Last BD in ring */ 195#define FEC_RBD_LAST 0x0800 /* Buffer is last in frame(useless) */ 196#define FEC_RBD_MISS 0x0100 /* Miss bit for prom mode */ 197#define FEC_RBD_BC 0x0080 /* The received frame is broadcast frame */ 198#define FEC_RBD_MC 0x0040 /* The received frame is multicast frame */ 199#define FEC_RBD_LG 0x0020 /* Frame length violation */ 200#define FEC_RBD_NO 0x0010 /* Nonoctet align frame */ 201#define FEC_RBD_SH 0x0008 /* Short frame */ 202#define FEC_RBD_CR 0x0004 /* CRC error */ 203#define FEC_RBD_OV 0x0002 /* Receive FIFO overrun */ 204#define FEC_RBD_TR 0x0001 /* Frame is truncated */ 205#define FEC_RBD_ERR (FEC_RBD_LG | FEC_RBD_NO | FEC_RBD_CR | \ 206 FEC_RBD_OV | FEC_RBD_TR) 207 208/* TBD bits definitions */ 209#define FEC_TBD_READY 0x8000 /* Buffer is ready */ 210#define FEC_TBD_WRAP 0x2000 /* Last BD in ring */ 211#define FEC_TBD_LAST 0x0800 /* Buffer is last in frame */ 212#define FEC_TBD_TC 0x0400 /* Transmit the CRC */ 213#define FEC_TBD_ABC 0x0200 /* Append bad CRC */ 214 215/* MII-related definitios */ 216#define FEC_MII_DATA_ST 0x40000000 /* Start of frame delimiter */ 217#define FEC_MII_DATA_OP_RD 0x20000000 /* Perform a read operation */ 218#define FEC_MII_DATA_OP_WR 0x10000000 /* Perform a write operation */ 219#define FEC_MII_DATA_PA_MSK 0x0f800000 /* PHY Address field mask */ 220#define FEC_MII_DATA_RA_MSK 0x007c0000 /* PHY Register field mask */ 221#define FEC_MII_DATA_TA 0x00020000 /* Turnaround */ 222#define FEC_MII_DATA_DATAMSK 0x0000ffff /* PHY data field */ 223 224#define FEC_MII_DATA_RA_SHIFT 18 /* MII Register address bits */ 225#define FEC_MII_DATA_PA_SHIFT 23 /* MII PHY address bits */ 226 227#endif /* __MPC512X_FEC_H */ 228