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26#include <common.h>
27#include <asm/processor.h>
28#include <asm/io.h>
29#include <pci.h>
30#include <asm/arch/ixp425.h>
31#include <asm/arch/ixp425pci.h>
32
33static void non_prefetch_read (unsigned int addr, unsigned int cmd,
34 unsigned int *data);
35static void non_prefetch_write (unsigned int addr, unsigned int cmd,
36 unsigned int data);
37static void configure_pins (void);
38static void sys_pci_gpio_clock_config (void);
39static void pci_bus_scan (void);
40static int pci_device_exists (unsigned int deviceNo);
41static void sys_pci_bar_info_get (unsigned int devnum, unsigned int bus,
42 unsigned int dev, unsigned int func);
43static void sys_pci_device_bars_write (void);
44static void calc_bars (PciBar * Bars[], unsigned int nBars,
45 unsigned int startAddr);
46
47#define PCI_MEMORY_BUS 0x00000000
48#define PCI_MEMORY_PHY 0x48000000
49#define PCI_MEMORY_SIZE 0x04000000
50
51#define PCI_MEM_BUS 0x40000000
52#define PCI_MEM_PHY 0x00000000
53#define PCI_MEM_SIZE 0x04000000
54
55#define PCI_IO_BUS 0x40000000
56#define PCI_IO_PHY 0x50000000
57#define PCI_IO_SIZE 0x10000000
58
59struct pci_controller hose;
60
61unsigned int nDevices;
62unsigned int nMBars;
63unsigned int nIOBars;
64PciBar *memBars[IXP425_PCI_MAX_BAR];
65PciBar *ioBars[IXP425_PCI_MAX_BAR];
66PciDevice devices[IXP425_PCI_MAX_FUNC_ON_BUS];
67
68int pci_read_config_dword (pci_dev_t dev, int where, unsigned int *val)
69{
70 unsigned int retval;
71 unsigned int addr;
72
73
74
75 addr = BIT ((31 - dev)) | (where & ~3);
76 non_prefetch_read (addr, NP_CMD_CONFIGREAD, &retval);
77
78 *val = retval;
79
80 return (OK);
81}
82
83int pci_read_config_word (pci_dev_t dev, int where, unsigned short *val)
84{
85 unsigned int n;
86 unsigned int retval;
87 unsigned int addr;
88 unsigned int byteEnables;
89
90 n = where % 4;
91
92
93 byteEnables =
94 (~(BIT (n) | BIT ((n + 1)))) &
95 IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
96 byteEnables = byteEnables << PCI_NP_CBE_BESL;
97
98
99 addr = BIT ((31 - dev)) | (where & ~3);
100 non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
101
102
103 *val = (retval >> (8 * n));
104
105 return (OK);
106}
107
108int pci_read_config_byte (pci_dev_t dev, int where, unsigned char *val)
109{
110 unsigned int retval;
111 unsigned int n;
112 unsigned int byteEnables;
113 unsigned int addr;
114
115 n = where % 4;
116
117
118 byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
119 byteEnables = byteEnables << PCI_NP_CBE_BESL;
120
121
122
123 addr = BIT ((31 - dev)) | (where & ~3);
124 non_prefetch_read (addr, byteEnables | NP_CMD_CONFIGREAD, &retval);
125
126 *val = (retval >> (8 * n));
127
128 return (OK);
129}
130
131int pci_write_config_byte (pci_dev_t dev, int where, unsigned char val)
132{
133 unsigned int addr;
134 unsigned int byteEnables;
135 unsigned int n;
136 unsigned int ldata;
137
138 n = where % 4;
139
140
141 byteEnables = (~BIT (n)) & IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
142 byteEnables = byteEnables << PCI_NP_CBE_BESL;
143 ldata = val << (8 * n);
144
145
146 addr = BIT ((31 - dev)) | (where & ~3);
147 non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
148
149 return (OK);
150}
151
152int pci_write_config_word (pci_dev_t dev, int where, unsigned short val)
153{
154 unsigned int addr;
155 unsigned int byteEnables;
156 unsigned int n;
157 unsigned int ldata;
158
159 n = where % 4;
160
161
162 byteEnables =
163 (~(BIT (n) | BIT ((n + 1)))) &
164 IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
165 byteEnables = byteEnables << PCI_NP_CBE_BESL;
166 ldata = val << (8 * n);
167
168
169 addr = BIT (31 - dev) | (where & ~3);
170 non_prefetch_write (addr, byteEnables | NP_CMD_CONFIGWRITE, ldata);
171
172 return (OK);
173}
174
175int pci_write_config_dword (pci_dev_t dev, int where, unsigned int val)
176{
177 unsigned int addr;
178
179
180
181 addr = BIT (31 - dev) | (where & ~3);
182 non_prefetch_write (addr, NP_CMD_CONFIGWRITE, val);
183
184 return (OK);
185}
186
187void non_prefetch_read (unsigned int addr,
188 unsigned int cmd, unsigned int *data)
189{
190 REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr);
191
192
193 REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd);
194
195
196 REG_READ (PCI_CSR_BASE, PCI_NP_RDATA_OFFSET, *data);
197
198 return;
199}
200
201void non_prefetch_write (unsigned int addr,
202 unsigned int cmd, unsigned int data)
203{
204
205 REG_WRITE (PCI_CSR_BASE, PCI_NP_AD_OFFSET, addr);
206
207 REG_WRITE (PCI_CSR_BASE, PCI_NP_CBE_OFFSET, cmd);
208
209 REG_WRITE (PCI_CSR_BASE, PCI_NP_WDATA_OFFSET, data);
210
211 return;
212}
213
214
215
216
217
218void crp_read (unsigned int offset, unsigned int *data)
219{
220 REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET, offset);
221 REG_READ (PCI_CSR_BASE, PCI_CRP_RDATA_OFFSET, *data);
222}
223
224void crp_write (unsigned int offset, unsigned int data)
225{
226
227 REG_WRITE (PCI_CSR_BASE, PCI_CRP_AD_CBE_OFFSET,
228 PCI_CRP_WRITE | offset);
229 REG_WRITE (PCI_CSR_BASE, PCI_CRP_WDATA_OFFSET, data);
230}
231
232
233void pci_ixp_init (struct pci_controller *hose)
234{
235 unsigned int regval;
236
237 hose->first_busno = 0;
238 hose->last_busno = 0x00;
239
240
241 pci_set_region (hose->regions + 0,
242 PCI_MEMORY_BUS,
243 PCI_MEMORY_PHY, PCI_MEMORY_SIZE, PCI_REGION_SYS_MEMORY);
244
245
246 pci_set_region (hose->regions + 1,
247 PCI_MEM_BUS,
248 PCI_MEM_PHY, PCI_MEM_SIZE, PCI_REGION_MEM);
249
250 pci_set_region (hose->regions + 2,
251 PCI_IO_BUS, PCI_IO_PHY, PCI_IO_SIZE, PCI_REGION_IO);
252
253 hose->region_count = 3;
254
255 pci_register_hose (hose);
256
257
258
259
260
261
262 REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
263 regval |= 1 << 2;
264 REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
265
266 configure_pins ();
267
268 READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval);
269 WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval & (~(1 << 13)));
270 udelay (533);
271 sys_pci_gpio_clock_config ();
272 REG_WRITE (PCI_CSR_BASE, PCI_INTEN_OFFSET, 0);
273 udelay (100);
274 READ_GPIO_REG (IXP425_GPIO_GPOUTR, regval);
275 WRITE_GPIO_REG (IXP425_GPIO_GPOUTR, regval | (1 << 13));
276 udelay (533);
277 crp_write (PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_0_DEFAULT);
278 crp_write (PCI_CFG_BASE_ADDRESS_1, IXP425_PCI_BAR_1_DEFAULT);
279 crp_write (PCI_CFG_BASE_ADDRESS_2, IXP425_PCI_BAR_2_DEFAULT);
280 crp_write (PCI_CFG_BASE_ADDRESS_3, IXP425_PCI_BAR_3_DEFAULT);
281 crp_write (PCI_CFG_BASE_ADDRESS_4, IXP425_PCI_BAR_4_DEFAULT);
282 crp_write (PCI_CFG_BASE_ADDRESS_5, IXP425_PCI_BAR_5_DEFAULT);
283
284 REG_WRITE (PCI_CSR_BASE, PCI_AHBMEMBASE_OFFSET,
285 IXP425_PCI_AHBMEMBASE_DEFAULT);
286
287 REG_WRITE (PCI_CSR_BASE, PCI_AHBIOBASE_OFFSET,
288 IXP425_PCI_AHBIOBASE_DEFAULT);
289
290 REG_WRITE (PCI_CSR_BASE, PCI_PCIMEMBASE_OFFSET,
291 IXP425_PCI_PCIMEMBASE_DEFAULT);
292
293 crp_write (PCI_CFG_SUB_VENDOR_ID, IXP425_PCI_SUB_VENDOR_SYSTEM);
294
295 REG_READ (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
296 regval |= PCI_CSR_IC | PCI_CSR_ABE | PCI_CSR_PDS;
297 REG_WRITE (PCI_CSR_BASE, PCI_CSR_OFFSET, regval);
298 crp_write (PCI_CFG_COMMAND, PCI_CFG_CMD_MAE | PCI_CFG_CMD_BME);
299 udelay (1000);
300
301 pci_write_config_word (0, PCI_CFG_COMMAND, INITIAL_PCI_CMD);
302 REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
303 | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE);
304#ifdef CONFIG_PCI_SCAN_SHOW
305 printf ("Device bus dev func deviceID vendorID \n");
306#endif
307 pci_bus_scan ();
308}
309
310void configure_pins (void)
311{
312 unsigned int regval;
313
314
315 READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
316 WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval & (~(1 << 8)));
317 READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
318
319 READ_GPIO_REG (IXP425_GPIO_GPOER, regval);
320 WRITE_GPIO_REG (IXP425_GPIO_GPOER,
321 (((~(3 << 13)) & regval) | (0xf << 8)));
322 READ_GPIO_REG (IXP425_GPIO_GPOER, regval);
323
324 READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval);
325 WRITE_GPIO_REG (IXP425_GPIO_GPIT2R,
326 (regval &
327 ((0x1 << 9) | (0x1 << 6) | (0x1 << 3) | 0x1)));
328 READ_GPIO_REG (IXP425_GPIO_GPIT2R, regval);
329
330 READ_GPIO_REG (IXP425_GPIO_GPISR, regval);
331 WRITE_GPIO_REG (IXP425_GPIO_GPISR, (regval | (0xf << 8)));
332 READ_GPIO_REG (IXP425_GPIO_GPISR, regval);
333}
334
335void sys_pci_gpio_clock_config (void)
336{
337 unsigned int regval;
338
339 READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
340 regval |= 0x1 << 4;
341 WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
342 READ_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
343 regval |= 0x1 << 8;
344 WRITE_GPIO_REG (IXP425_GPIO_GPCLKR, regval);
345}
346
347void pci_bus_scan (void)
348{
349 unsigned int bus = 0, dev, func = 0;
350 unsigned short data16;
351 unsigned int data32;
352 unsigned char intPin;
353
354
355 devices[0].bus = 0;
356 devices[0].device = 0;
357 devices[0].func = 0;
358
359 crp_read (PCI_CFG_VENDOR_ID, &data32);
360
361 devices[0].vendor_id = data32 & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK;
362 devices[0].device_id = data32 >> 16;
363 devices[0].error = FALSE;
364 devices[0].bar[NO_BAR].size = 0;
365
366 nDevices = 1;
367
368 nMBars = 0;
369 nIOBars = 0;
370
371 for (dev = 0; dev < IXP425_PCI_MAX_DEV; dev++) {
372
373
374 if (pci_device_exists (dev) != TRUE) {
375
376
377 REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
378 | PCI_ISR_PFE | PCI_ISR_PPE |
379 PCI_ISR_AHBE);
380 continue;
381 }
382
383
384 devices[nDevices].bus = bus;
385 devices[nDevices].device = dev;
386 devices[nDevices].func = func;
387
388 pci_read_config_word (dev, PCI_CFG_VENDOR_ID, &data16);
389
390 devices[nDevices].vendor_id = data16;
391
392 pci_read_config_word (dev, PCI_CFG_DEVICE_ID, &data16);
393 devices[nDevices].device_id = data16;
394
395
396 devices[nDevices].error = FALSE;
397
398
399 sys_pci_bar_info_get (nDevices, bus, dev, func);
400
401 pci_read_config_byte (dev, PCI_CFG_DEV_INT_PIN, &intPin);
402
403
404 if (intPin > PCI_IRQ_LINES) {
405 devices[nDevices].error = TRUE;
406 } else if (intPin != 0) {
407
408
409 devices[nDevices].irq = intPin;
410 }
411#ifdef CONFIG_PCI_SCAN_SHOW
412 printf ("%06d %03d %03d %04d %08d %08x\n", nDevices,
413 devices[nDevices].vendor_id);
414#endif
415 nDevices++;
416
417 }
418
419 calc_bars (memBars, nMBars, IXP425_PCI_BAR_MEM_BASE);
420 sys_pci_device_bars_write ();
421
422 REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PSE
423 | PCI_ISR_PFE | PCI_ISR_PPE | PCI_ISR_AHBE);
424}
425
426void sys_pci_bar_info_get (unsigned int devnum,
427 unsigned int bus,
428 unsigned int dev, unsigned int func)
429{
430 unsigned int data32;
431 unsigned int tmp;
432 unsigned int size;
433
434 pci_write_config_dword (devnum,
435 PCI_CFG_BASE_ADDRESS_0, IXP425_PCI_BAR_QUERY);
436 pci_read_config_dword (devnum, PCI_CFG_BASE_ADDRESS_0, &data32);
437
438 devices[devnum].bar[0].address = (data32 & 1);
439
440 if (data32 & 1) {
441
442 tmp = data32 & ~0x3;
443 size = ~(tmp - 1);
444 devices[devnum].bar[0].size = size;
445
446 if (nIOBars < IXP425_PCI_MAX_BAR) {
447 ioBars[nIOBars++] = &devices[devnum].bar[0];
448 }
449 } else {
450
451 tmp = data32 & ~IXP425_PCI_BOTTOM_NIBBLE_OF_LONG_MASK;
452 size = ~(tmp - 1);
453 devices[devnum].bar[0].size = size;
454
455 if (nMBars < IXP425_PCI_MAX_BAR) {
456 memBars[nMBars++] = &devices[devnum].bar[0];
457 } else {
458 devices[devnum].error = TRUE;
459 }
460
461 }
462
463 devices[devnum].bar[1].size = 0;
464}
465
466void sortBars (PciBar * Bars[], unsigned int nBars)
467{
468 unsigned int i, j;
469 PciBar *tmp;
470
471 if (nBars == 0) {
472 return;
473 }
474
475
476 for (i = 0; i < nBars - 1; i++) {
477 for (j = i + 1; j < nBars; j++) {
478 if (Bars[j]->size > Bars[i]->size) {
479
480 tmp = Bars[i];
481 Bars[i] = Bars[j];
482 Bars[j] = tmp;
483 }
484 }
485 }
486}
487
488void calc_bars (PciBar * Bars[], unsigned int nBars, unsigned int startAddr)
489{
490 unsigned int i;
491
492 if (nBars == 0) {
493 return;
494 }
495
496 for (i = 0; i < nBars; i++) {
497 Bars[i]->address |= startAddr;
498 startAddr += Bars[i]->size;
499 }
500}
501
502void sys_pci_device_bars_write (void)
503{
504 unsigned int i;
505 int addr;
506
507 for (i = 1; i < nDevices; i++) {
508 if (devices[i].error) {
509 continue;
510 }
511
512 pci_write_config_dword (devices[i].device,
513 PCI_CFG_BASE_ADDRESS_0,
514 devices[i].bar[0].address);
515 addr = BIT (31 - devices[i].device) |
516 (0 << PCI_NP_AD_FUNCSL) |
517 (PCI_CFG_BASE_ADDRESS_0 & ~3);
518 pci_write_config_dword (devices[i].device,
519 PCI_CFG_DEV_INT_LINE, devices[i].irq);
520
521 pci_write_config_word (devices[i].device,
522 PCI_CFG_COMMAND, INITIAL_PCI_CMD);
523
524 }
525}
526
527
528int pci_device_exists (unsigned int deviceNo)
529{
530 unsigned int vendorId;
531 unsigned int regval;
532
533 pci_read_config_dword (deviceNo, PCI_CFG_VENDOR_ID, &vendorId);
534
535
536
537
538
539 REG_READ (PCI_CSR_BASE, PCI_ISR_OFFSET, regval);
540 if ((vendorId != 0x0) && ((regval & PCI_ISR_PFE) == 0)) {
541 return TRUE;
542 }
543
544
545 REG_WRITE (PCI_CSR_BASE, PCI_ISR_OFFSET, PCI_ISR_PFE);
546 return FALSE;
547}
548
549pci_dev_t pci_find_devices (struct pci_device_id * ids, int devNo)
550{
551 unsigned int i;
552 unsigned int devdidvid;
553 unsigned int didvid;
554 unsigned int vendorId, deviceId;
555
556 vendorId = ids->vendor;
557 deviceId = ids->device;
558 didvid = ((deviceId << 16) & IXP425_PCI_TOP_WORD_OF_LONG_MASK) |
559 (vendorId & IXP425_PCI_BOTTOM_WORD_OF_LONG_MASK);
560
561 for (i = devNo + 1; i < nDevices; i++) {
562
563 pci_read_config_dword (devices[i].device, PCI_CFG_VENDOR_ID,
564 &devdidvid);
565
566 if (devdidvid == didvid) {
567 return devices[i].device;
568 }
569 }
570 return -1;
571}
572