1/* 2 * (C) Copyright 2004-2007 Freescale Semiconductor, Inc. 3 * 4 * MPC83xx Internal Memory Map 5 * 6 * Contributors: 7 * Dave Liu <daveliu@freescale.com> 8 * Tanya Jiang <tanya.jiang@freescale.com> 9 * Mandy Lavi <mandy.lavi@freescale.com> 10 * Eran Liberty <liberty@freescale.com> 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 * 27 */ 28#ifndef __IMMAP_83xx__ 29#define __IMMAP_83xx__ 30 31#include <asm/types.h> 32#include <asm/fsl_i2c.h> 33#include <asm/mpc8xxx_spi.h> 34#include <asm/fsl_lbc.h> 35 36/* 37 * Local Access Window 38 */ 39typedef struct law83xx { 40 u32 bar; /* LBIU local access window base address register */ 41 u32 ar; /* LBIU local access window attribute register */ 42} law83xx_t; 43 44/* 45 * System configuration registers 46 */ 47typedef struct sysconf83xx { 48 u32 immrbar; /* Internal memory map base address register */ 49 u8 res0[0x04]; 50 u32 altcbar; /* Alternate configuration base address register */ 51 u8 res1[0x14]; 52 law83xx_t lblaw[4]; /* LBIU local access window */ 53 u8 res2[0x20]; 54 law83xx_t pcilaw[2]; /* PCI local access window */ 55 u8 res3[0x10]; 56 law83xx_t pcielaw[2]; /* PCI Express local access window */ 57 u8 res4[0x10]; 58 law83xx_t ddrlaw[2]; /* DDR local access window */ 59 u8 res5[0x50]; 60 u32 sgprl; /* System General Purpose Register Low */ 61 u32 sgprh; /* System General Purpose Register High */ 62 u32 spridr; /* System Part and Revision ID Register */ 63 u8 res6[0x04]; 64 u32 spcr; /* System Priority Configuration Register */ 65 u32 sicrl; /* System I/O Configuration Register Low */ 66 u32 sicrh; /* System I/O Configuration Register High */ 67 u8 res7[0x04]; 68 u32 sidcr0; /* System I/O Delay Configuration Register 0 */ 69 u32 sidcr1; /* System I/O Delay Configuration Register 1 */ 70 u32 ddrcdr; /* DDR Control Driver Register */ 71 u32 ddrdsr; /* DDR Debug Status Register */ 72 u32 obir; /* Output Buffer Impedance Register */ 73 u8 res8[0xC]; 74 u32 pecr1; /* PCI Express control register 1 */ 75 u32 pecr2; /* PCI Express control register 2 */ 76 u8 res9[0xB8]; 77} sysconf83xx_t; 78 79/* 80 * Watch Dog Timer (WDT) Registers 81 */ 82typedef struct wdt83xx { 83 u8 res0[4]; 84 u32 swcrr; /* System watchdog control register */ 85 u32 swcnr; /* System watchdog count register */ 86 u8 res1[2]; 87 u16 swsrr; /* System watchdog service register */ 88 u8 res2[0xF0]; 89} wdt83xx_t; 90 91/* 92 * RTC/PIT Module Registers 93 */ 94typedef struct rtclk83xx { 95 u32 cnr; /* control register */ 96 u32 ldr; /* load register */ 97 u32 psr; /* prescale register */ 98 u32 ctr; /* counter value field register */ 99 u32 evr; /* event register */ 100 u32 alr; /* alarm register */ 101 u8 res0[0xE8]; 102} rtclk83xx_t; 103 104/* 105 * Global timer module 106 */ 107typedef struct gtm83xx { 108 u8 cfr1; /* Timer1/2 Configuration */ 109 u8 res0[3]; 110 u8 cfr2; /* Timer3/4 Configuration */ 111 u8 res1[10]; 112 u16 mdr1; /* Timer1 Mode Register */ 113 u16 mdr2; /* Timer2 Mode Register */ 114 u16 rfr1; /* Timer1 Reference Register */ 115 u16 rfr2; /* Timer2 Reference Register */ 116 u16 cpr1; /* Timer1 Capture Register */ 117 u16 cpr2; /* Timer2 Capture Register */ 118 u16 cnr1; /* Timer1 Counter Register */ 119 u16 cnr2; /* Timer2 Counter Register */ 120 u16 mdr3; /* Timer3 Mode Register */ 121 u16 mdr4; /* Timer4 Mode Register */ 122 u16 rfr3; /* Timer3 Reference Register */ 123 u16 rfr4; /* Timer4 Reference Register */ 124 u16 cpr3; /* Timer3 Capture Register */ 125 u16 cpr4; /* Timer4 Capture Register */ 126 u16 cnr3; /* Timer3 Counter Register */ 127 u16 cnr4; /* Timer4 Counter Register */ 128 u16 evr1; /* Timer1 Event Register */ 129 u16 evr2; /* Timer2 Event Register */ 130 u16 evr3; /* Timer3 Event Register */ 131 u16 evr4; /* Timer4 Event Register */ 132 u16 psr1; /* Timer1 Prescaler Register */ 133 u16 psr2; /* Timer2 Prescaler Register */ 134 u16 psr3; /* Timer3 Prescaler Register */ 135 u16 psr4; /* Timer4 Prescaler Register */ 136 u8 res[0xC0]; 137} gtm83xx_t; 138 139/* 140 * Integrated Programmable Interrupt Controller 141 */ 142typedef struct ipic83xx { 143 u32 sicfr; /* System Global Interrupt Configuration Register */ 144 u32 sivcr; /* System Global Interrupt Vector Register */ 145 u32 sipnr_h; /* System Internal Interrupt Pending Register - High */ 146 u32 sipnr_l; /* System Internal Interrupt Pending Register - Low */ 147 u32 siprr_a; /* System Internal Interrupt Group A Priority Register */ 148 u8 res0[8]; 149 u32 siprr_d; /* System Internal Interrupt Group D Priority Register */ 150 u32 simsr_h; /* System Internal Interrupt Mask Register - High */ 151 u32 simsr_l; /* System Internal Interrupt Mask Register - Low */ 152 u8 res1[4]; 153 u32 sepnr; /* System External Interrupt Pending Register */ 154 u32 smprr_a; /* System Mixed Interrupt Group A Priority Register */ 155 u32 smprr_b; /* System Mixed Interrupt Group B Priority Register */ 156 u32 semsr; /* System External Interrupt Mask Register */ 157 u32 secnr; /* System External Interrupt Control Register */ 158 u32 sersr; /* System Error Status Register */ 159 u32 sermr; /* System Error Mask Register */ 160 u32 sercr; /* System Error Control Register */ 161 u8 res2[4]; 162 u32 sifcr_h; /* System Internal Interrupt Force Register - High */ 163 u32 sifcr_l; /* System Internal Interrupt Force Register - Low */ 164 u32 sefcr; /* System External Interrupt Force Register */ 165 u32 serfr; /* System Error Force Register */ 166 u32 scvcr; /* System Critical Interrupt Vector Register */ 167 u32 smvcr; /* System Management Interrupt Vector Register */ 168 u8 res3[0x98]; 169} ipic83xx_t; 170 171/* 172 * System Arbiter Registers 173 */ 174typedef struct arbiter83xx { 175 u32 acr; /* Arbiter Configuration Register */ 176 u32 atr; /* Arbiter Timers Register */ 177 u8 res[4]; 178 u32 aer; /* Arbiter Event Register */ 179 u32 aidr; /* Arbiter Interrupt Definition Register */ 180 u32 amr; /* Arbiter Mask Register */ 181 u32 aeatr; /* Arbiter Event Attributes Register */ 182 u32 aeadr; /* Arbiter Event Address Register */ 183 u32 aerr; /* Arbiter Event Response Register */ 184 u8 res1[0xDC]; 185} arbiter83xx_t; 186 187/* 188 * Reset Module 189 */ 190typedef struct reset83xx { 191 u32 rcwl; /* Reset Configuration Word Low Register */ 192 u32 rcwh; /* Reset Configuration Word High Register */ 193 u8 res0[8]; 194 u32 rsr; /* Reset Status Register */ 195 u32 rmr; /* Reset Mode Register */ 196 u32 rpr; /* Reset protection Register */ 197 u32 rcr; /* Reset Control Register */ 198 u32 rcer; /* Reset Control Enable Register */ 199 u8 res1[0xDC]; 200} reset83xx_t; 201 202/* 203 * Clock Module 204 */ 205typedef struct clk83xx { 206 u32 spmr; /* system PLL mode Register */ 207 u32 occr; /* output clock control Register */ 208 u32 sccr; /* system clock control Register */ 209 u8 res0[0xF4]; 210} clk83xx_t; 211 212/* 213 * Power Management Control Module 214 */ 215typedef struct pmc83xx { 216 u32 pmccr; /* PMC Configuration Register */ 217 u32 pmcer; /* PMC Event Register */ 218 u32 pmcmr; /* PMC Mask Register */ 219 u32 pmccr1; /* PMC Configuration Register 1 */ 220 u32 pmccr2; /* PMC Configuration Register 2 */ 221 u8 res0[0xEC]; 222} pmc83xx_t; 223 224/* 225 * General purpose I/O module 226 */ 227typedef struct gpio83xx { 228 u32 dir; /* direction register */ 229 u32 odr; /* open drain register */ 230 u32 dat; /* data register */ 231 u32 ier; /* interrupt event register */ 232 u32 imr; /* interrupt mask register */ 233 u32 icr; /* external interrupt control register */ 234 u8 res0[0xE8]; 235} gpio83xx_t; 236 237/* 238 * QE Ports Interrupts Registers 239 */ 240typedef struct qepi83xx { 241 u8 res0[0xC]; 242 u32 qepier; /* QE Ports Interrupt Event Register */ 243 u32 qepimr; /* QE Ports Interrupt Mask Register */ 244 u32 qepicr; /* QE Ports Interrupt Control Register */ 245 u8 res1[0xE8]; 246} qepi83xx_t; 247 248/* 249 * QE Parallel I/O Ports 250 */ 251typedef struct gpio_n { 252 u32 podr; /* Open Drain Register */ 253 u32 pdat; /* Data Register */ 254 u32 dir1; /* direction register 1 */ 255 u32 dir2; /* direction register 2 */ 256 u32 ppar1; /* Pin Assignment Register 1 */ 257 u32 ppar2; /* Pin Assignment Register 2 */ 258} gpio_n_t; 259 260typedef struct qegpio83xx { 261 gpio_n_t ioport[0x7]; 262 u8 res0[0x358]; 263} qepio83xx_t; 264 265/* 266 * QE Secondary Bus Access Windows 267 */ 268typedef struct qesba83xx { 269 u32 lbmcsar; /* Local bus memory controller start address */ 270 u32 sdmcsar; /* Secondary DDR memory controller start address */ 271 u8 res0[0x38]; 272 u32 lbmcear; /* Local bus memory controller end address */ 273 u32 sdmcear; /* Secondary DDR memory controller end address */ 274 u8 res1[0x38]; 275 u32 lbmcar; /* Local bus memory controller attributes */ 276 u32 sdmcar; /* Secondary DDR memory controller attributes */ 277 u8 res2[0x378]; 278} qesba83xx_t; 279 280/* 281 * DDR Memory Controller Memory Map 282 */ 283typedef struct ddr_cs_bnds { 284 u32 csbnds; 285 u8 res0[4]; 286} ddr_cs_bnds_t; 287 288typedef struct ddr83xx { 289 ddr_cs_bnds_t csbnds[4];/* Chip Select x Memory Bounds */ 290 u8 res0[0x60]; 291 u32 cs_config[4]; /* Chip Select x Configuration */ 292 u8 res1[0x70]; 293 u32 timing_cfg_3; /* SDRAM Timing Configuration 3 */ 294 u32 timing_cfg_0; /* SDRAM Timing Configuration 0 */ 295 u32 timing_cfg_1; /* SDRAM Timing Configuration 1 */ 296 u32 timing_cfg_2; /* SDRAM Timing Configuration 2 */ 297 u32 sdram_cfg; /* SDRAM Control Configuration */ 298 u32 sdram_cfg2; /* SDRAM Control Configuration 2 */ 299 u32 sdram_mode; /* SDRAM Mode Configuration */ 300 u32 sdram_mode2; /* SDRAM Mode Configuration 2 */ 301 u32 sdram_md_cntl; /* SDRAM Mode Control */ 302 u32 sdram_interval; /* SDRAM Interval Configuration */ 303 u32 ddr_data_init; /* SDRAM Data Initialization */ 304 u8 res2[4]; 305 u32 sdram_clk_cntl; /* SDRAM Clock Control */ 306 u8 res3[0x14]; 307 u32 ddr_init_addr; /* DDR training initialization address */ 308 u32 ddr_init_ext_addr; /* DDR training initialization extended address */ 309 u8 res4[0xAA8]; 310 u32 ddr_ip_rev1; /* DDR IP block revision 1 */ 311 u32 ddr_ip_rev2; /* DDR IP block revision 2 */ 312 u8 res5[0x200]; 313 u32 data_err_inject_hi; /* Memory Data Path Error Injection Mask High */ 314 u32 data_err_inject_lo; /* Memory Data Path Error Injection Mask Low */ 315 u32 ecc_err_inject; /* Memory Data Path Error Injection Mask ECC */ 316 u8 res6[0x14]; 317 u32 capture_data_hi; /* Memory Data Path Read Capture High */ 318 u32 capture_data_lo; /* Memory Data Path Read Capture Low */ 319 u32 capture_ecc; /* Memory Data Path Read Capture ECC */ 320 u8 res7[0x14]; 321 u32 err_detect; /* Memory Error Detect */ 322 u32 err_disable; /* Memory Error Disable */ 323 u32 err_int_en; /* Memory Error Interrupt Enable */ 324 u32 capture_attributes; /* Memory Error Attributes Capture */ 325 u32 capture_address; /* Memory Error Address Capture */ 326 u32 capture_ext_address;/* Memory Error Extended Address Capture */ 327 u32 err_sbe; /* Memory Single-Bit ECC Error Management */ 328 u8 res8[0xA4]; 329 u32 debug_reg; 330 u8 res9[0xFC]; 331} ddr83xx_t; 332 333/* 334 * DUART 335 */ 336typedef struct duart83xx { 337 u8 urbr_ulcr_udlb; /* combined register for URBR, UTHR and UDLB */ 338 u8 uier_udmb; /* combined register for UIER and UDMB */ 339 u8 uiir_ufcr_uafr; /* combined register for UIIR, UFCR and UAFR */ 340 u8 ulcr; /* line control register */ 341 u8 umcr; /* MODEM control register */ 342 u8 ulsr; /* line status register */ 343 u8 umsr; /* MODEM status register */ 344 u8 uscr; /* scratch register */ 345 u8 res0[8]; 346 u8 udsr; /* DMA status register */ 347 u8 res1[3]; 348 u8 res2[0xEC]; 349} duart83xx_t; 350 351/* 352 * DMA/Messaging Unit 353 */ 354typedef struct dma83xx { 355 u32 res0[0xC]; /* 0x0-0x29 reseverd */ 356 u32 omisr; /* 0x30 Outbound message interrupt status register */ 357 u32 omimr; /* 0x34 Outbound message interrupt mask register */ 358 u32 res1[0x6]; /* 0x38-0x49 reserved */ 359 u32 imr0; /* 0x50 Inbound message register 0 */ 360 u32 imr1; /* 0x54 Inbound message register 1 */ 361 u32 omr0; /* 0x58 Outbound message register 0 */ 362 u32 omr1; /* 0x5C Outbound message register 1 */ 363 u32 odr; /* 0x60 Outbound doorbell register */ 364 u32 res2; /* 0x64-0x67 reserved */ 365 u32 idr; /* 0x68 Inbound doorbell register */ 366 u32 res3[0x5]; /* 0x6C-0x79 reserved */ 367 u32 imisr; /* 0x80 Inbound message interrupt status register */ 368 u32 imimr; /* 0x84 Inbound message interrupt mask register */ 369 u32 res4[0x1E]; /* 0x88-0x99 reserved */ 370 u32 dmamr0; /* 0x100 DMA 0 mode register */ 371 u32 dmasr0; /* 0x104 DMA 0 status register */ 372 u32 dmacdar0; /* 0x108 DMA 0 current descriptor address register */ 373 u32 res5; /* 0x10C reserved */ 374 u32 dmasar0; /* 0x110 DMA 0 source address register */ 375 u32 res6; /* 0x114 reserved */ 376 u32 dmadar0; /* 0x118 DMA 0 destination address register */ 377 u32 res7; /* 0x11C reserved */ 378 u32 dmabcr0; /* 0x120 DMA 0 byte count register */ 379 u32 dmandar0; /* 0x124 DMA 0 next descriptor address register */ 380 u32 res8[0x16]; /* 0x128-0x179 reserved */ 381 u32 dmamr1; /* 0x180 DMA 1 mode register */ 382 u32 dmasr1; /* 0x184 DMA 1 status register */ 383 u32 dmacdar1; /* 0x188 DMA 1 current descriptor address register */ 384 u32 res9; /* 0x18C reserved */ 385 u32 dmasar1; /* 0x190 DMA 1 source address register */ 386 u32 res10; /* 0x194 reserved */ 387 u32 dmadar1; /* 0x198 DMA 1 destination address register */ 388 u32 res11; /* 0x19C reserved */ 389 u32 dmabcr1; /* 0x1A0 DMA 1 byte count register */ 390 u32 dmandar1; /* 0x1A4 DMA 1 next descriptor address register */ 391 u32 res12[0x16]; /* 0x1A8-0x199 reserved */ 392 u32 dmamr2; /* 0x200 DMA 2 mode register */ 393 u32 dmasr2; /* 0x204 DMA 2 status register */ 394 u32 dmacdar2; /* 0x208 DMA 2 current descriptor address register */ 395 u32 res13; /* 0x20C reserved */ 396 u32 dmasar2; /* 0x210 DMA 2 source address register */ 397 u32 res14; /* 0x214 reserved */ 398 u32 dmadar2; /* 0x218 DMA 2 destination address register */ 399 u32 res15; /* 0x21C reserved */ 400 u32 dmabcr2; /* 0x220 DMA 2 byte count register */ 401 u32 dmandar2; /* 0x224 DMA 2 next descriptor address register */ 402 u32 res16[0x16]; /* 0x228-0x279 reserved */ 403 u32 dmamr3; /* 0x280 DMA 3 mode register */ 404 u32 dmasr3; /* 0x284 DMA 3 status register */ 405 u32 dmacdar3; /* 0x288 DMA 3 current descriptor address register */ 406 u32 res17; /* 0x28C reserved */ 407 u32 dmasar3; /* 0x290 DMA 3 source address register */ 408 u32 res18; /* 0x294 reserved */ 409 u32 dmadar3; /* 0x298 DMA 3 destination address register */ 410 u32 res19; /* 0x29C reserved */ 411 u32 dmabcr3; /* 0x2A0 DMA 3 byte count register */ 412 u32 dmandar3; /* 0x2A4 DMA 3 next descriptor address register */ 413 u32 dmagsr; /* 0x2A8 DMA general status register */ 414 u32 res20[0x15]; /* 0x2AC-0x2FF reserved */ 415} dma83xx_t; 416 417/* 418 * PCI Software Configuration Registers 419 */ 420typedef struct pciconf83xx { 421 u32 config_address; 422 u32 config_data; 423 u32 int_ack; 424 u8 res[116]; 425} pciconf83xx_t; 426 427/* 428 * PCI Outbound Translation Register 429 */ 430typedef struct pci_outbound_window { 431 u32 potar; 432 u8 res0[4]; 433 u32 pobar; 434 u8 res1[4]; 435 u32 pocmr; 436 u8 res2[4]; 437} pot83xx_t; 438 439/* 440 * Sequencer 441 */ 442typedef struct ios83xx { 443 pot83xx_t pot[6]; 444 u8 res0[0x60]; 445 u32 pmcr; 446 u8 res1[4]; 447 u32 dtcr; 448 u8 res2[4]; 449} ios83xx_t; 450 451/* 452 * PCI Controller Control and Status Registers 453 */ 454typedef struct pcictrl83xx { 455 u32 esr; 456 u32 ecdr; 457 u32 eer; 458 u32 eatcr; 459 u32 eacr; 460 u32 eeacr; 461 u32 edlcr; 462 u32 edhcr; 463 u32 gcr; 464 u32 ecr; 465 u32 gsr; 466 u8 res0[12]; 467 u32 pitar2; 468 u8 res1[4]; 469 u32 pibar2; 470 u32 piebar2; 471 u32 piwar2; 472 u8 res2[4]; 473 u32 pitar1; 474 u8 res3[4]; 475 u32 pibar1; 476 u32 piebar1; 477 u32 piwar1; 478 u8 res4[4]; 479 u32 pitar0; 480 u8 res5[4]; 481 u32 pibar0; 482 u8 res6[4]; 483 u32 piwar0; 484 u8 res7[132]; 485} pcictrl83xx_t; 486 487/* 488 * USB 489 */ 490typedef struct usb83xx { 491 u8 fixme[0x1000]; 492} usb83xx_t; 493 494/* 495 * TSEC 496 */ 497typedef struct tsec83xx { 498 u8 fixme[0x1000]; 499} tsec83xx_t; 500 501/* 502 * Security 503 */ 504typedef struct security83xx { 505 u8 fixme[0x10000]; 506} security83xx_t; 507 508/* 509 * PCI Express 510 */ 511struct pex_inbound_window { 512 u32 ar; 513 u32 tar; 514 u32 barl; 515 u32 barh; 516}; 517 518struct pex_outbound_window { 519 u32 ar; 520 u32 bar; 521 u32 tarl; 522 u32 tarh; 523}; 524 525struct pex_csb_bridge { 526 u32 pex_csb_ver; 527 u32 pex_csb_cab; 528 u32 pex_csb_ctrl; 529 u8 res0[8]; 530 u32 pex_dms_dstmr; 531 u8 res1[4]; 532 u32 pex_cbs_stat; 533 u8 res2[0x20]; 534 u32 pex_csb_obctrl; 535 u32 pex_csb_obstat; 536 u8 res3[0x98]; 537 u32 pex_csb_ibctrl; 538 u32 pex_csb_ibstat; 539 u8 res4[0xb8]; 540 u32 pex_wdma_ctrl; 541 u32 pex_wdma_addr; 542 u32 pex_wdma_stat; 543 u8 res5[0x94]; 544 u32 pex_rdma_ctrl; 545 u32 pex_rdma_addr; 546 u32 pex_rdma_stat; 547 u8 res6[0xd4]; 548 u32 pex_ombcr; 549 u32 pex_ombdr; 550 u8 res7[0x38]; 551 u32 pex_imbcr; 552 u32 pex_imbdr; 553 u8 res8[0x38]; 554 u32 pex_int_enb; 555 u32 pex_int_stat; 556 u32 pex_int_apio_vec1; 557 u32 pex_int_apio_vec2; 558 u8 res9[0x10]; 559 u32 pex_int_ppio_vec1; 560 u32 pex_int_ppio_vec2; 561 u32 pex_int_wdma_vec1; 562 u32 pex_int_wdma_vec2; 563 u32 pex_int_rdma_vec1; 564 u32 pex_int_rdma_vec2; 565 u32 pex_int_misc_vec; 566 u8 res10[4]; 567 u32 pex_int_axi_pio_enb; 568 u32 pex_int_axi_wdma_enb; 569 u32 pex_int_axi_rdma_enb; 570 u32 pex_int_axi_misc_enb; 571 u32 pex_int_axi_pio_stat; 572 u32 pex_int_axi_wdma_stat; 573 u32 pex_int_axi_rdma_stat; 574 u32 pex_int_axi_misc_stat; 575 u8 res11[0xa0]; 576 struct pex_outbound_window pex_outbound_win[4]; 577 u8 res12[0x100]; 578 u32 pex_epiwtar0; 579 u32 pex_epiwtar1; 580 u32 pex_epiwtar2; 581 u32 pex_epiwtar3; 582 u8 res13[0x70]; 583 struct pex_inbound_window pex_inbound_win[4]; 584}; 585 586typedef struct pex83xx { 587 u8 pex_cfg_header[0x404]; 588 u32 pex_ltssm_stat; 589 u8 res0[0x30]; 590 u32 pex_ack_replay_timeout; 591 u8 res1[4]; 592 u32 pex_gclk_ratio; 593 u8 res2[0xc]; 594 u32 pex_pm_timer; 595 u32 pex_pme_timeout; 596 u8 res3[4]; 597 u32 pex_aspm_req_timer; 598 u8 res4[0x18]; 599 u32 pex_ssvid_update; 600 u8 res5[0x34]; 601 u32 pex_cfg_ready; 602 u8 res6[0x24]; 603 u32 pex_bar_sizel; 604 u8 res7[4]; 605 u32 pex_bar_sel; 606 u8 res8[0x20]; 607 u32 pex_bar_pf; 608 u8 res9[0x88]; 609 u32 pex_pme_to_ack_tor; 610 u8 res10[0xc]; 611 u32 pex_ss_intr_mask; 612 u8 res11[0x25c]; 613 struct pex_csb_bridge bridge; 614 u8 res12[0x160]; 615} pex83xx_t; 616 617/* 618 * SATA 619 */ 620typedef struct sata83xx { 621 u8 fixme[0x1000]; 622} sata83xx_t; 623 624/* 625 * eSDHC 626 */ 627typedef struct sdhc83xx { 628 u8 fixme[0x1000]; 629} sdhc83xx_t; 630 631/* 632 * SerDes 633 */ 634typedef struct serdes83xx { 635 u8 fixme[0x100]; 636} serdes83xx_t; 637 638/* 639 * On Chip ROM 640 */ 641typedef struct rom83xx { 642 u8 mem[0x10000]; 643} rom83xx_t; 644 645/* 646 * TDM 647 */ 648typedef struct tdm83xx { 649 u8 fixme[0x200]; 650} tdm83xx_t; 651 652/* 653 * TDM DMAC 654 */ 655typedef struct tdmdmac83xx { 656 u8 fixme[0x2000]; 657} tdmdmac83xx_t; 658 659#if defined(CONFIG_MPC834X) 660typedef struct immap { 661 sysconf83xx_t sysconf; /* System configuration */ 662 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 663 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 664 rtclk83xx_t pit; /* Periodic Interval Timer */ 665 gtm83xx_t gtm[2]; /* Global Timers Module */ 666 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 667 arbiter83xx_t arbiter; /* System Arbiter Registers */ 668 reset83xx_t reset; /* Reset Module */ 669 clk83xx_t clk; /* System Clock Module */ 670 pmc83xx_t pmc; /* Power Management Control Module */ 671 gpio83xx_t gpio[2]; /* General purpose I/O module */ 672 u8 res0[0x200]; 673 u8 dll_ddr[0x100]; 674 u8 dll_lbc[0x100]; 675 u8 res1[0xE00]; 676 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 677 fsl_i2c_t i2c[2]; /* I2C Controllers */ 678 u8 res2[0x1300]; 679 duart83xx_t duart[2]; /* DUART */ 680 u8 res3[0x900]; 681 fsl_lbus_t lbus; /* Local Bus Controller Registers */ 682 u8 res4[0x1000]; 683 spi8xxx_t spi; /* Serial Peripheral Interface */ 684 dma83xx_t dma; /* DMA */ 685 pciconf83xx_t pci_conf[2]; /* PCI Software Configuration Registers */ 686 ios83xx_t ios; /* Sequencer */ 687 pcictrl83xx_t pci_ctrl[2]; /* PCI Controller Control and Status Registers */ 688 u8 res5[0x19900]; 689 usb83xx_t usb[2]; 690 tsec83xx_t tsec[2]; 691 u8 res6[0xA000]; 692 security83xx_t security; 693 u8 res7[0xC0000]; 694} immap_t; 695 696#elif defined(CONFIG_MPC8313) 697typedef struct immap { 698 sysconf83xx_t sysconf; /* System configuration */ 699 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 700 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 701 rtclk83xx_t pit; /* Periodic Interval Timer */ 702 gtm83xx_t gtm[2]; /* Global Timers Module */ 703 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 704 arbiter83xx_t arbiter; /* System Arbiter Registers */ 705 reset83xx_t reset; /* Reset Module */ 706 clk83xx_t clk; /* System Clock Module */ 707 pmc83xx_t pmc; /* Power Management Control Module */ 708 gpio83xx_t gpio[1]; /* General purpose I/O module */ 709 u8 res0[0x1300]; 710 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 711 fsl_i2c_t i2c[2]; /* I2C Controllers */ 712 u8 res1[0x1300]; 713 duart83xx_t duart[2]; /* DUART */ 714 u8 res2[0x900]; 715 fsl_lbus_t lbus; /* Local Bus Controller Registers */ 716 u8 res3[0x1000]; 717 spi8xxx_t spi; /* Serial Peripheral Interface */ 718 dma83xx_t dma; /* DMA */ 719 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ 720 u8 res4[0x80]; 721 ios83xx_t ios; /* Sequencer */ 722 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ 723 u8 res5[0x1aa00]; 724 usb83xx_t usb[1]; 725 tsec83xx_t tsec[2]; 726 u8 res6[0xA000]; 727 security83xx_t security; 728 u8 res7[0xC0000]; 729} immap_t; 730 731#elif defined(CONFIG_MPC8315) 732typedef struct immap { 733 sysconf83xx_t sysconf; /* System configuration */ 734 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 735 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 736 rtclk83xx_t pit; /* Periodic Interval Timer */ 737 gtm83xx_t gtm[2]; /* Global Timers Module */ 738 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 739 arbiter83xx_t arbiter; /* System Arbiter Registers */ 740 reset83xx_t reset; /* Reset Module */ 741 clk83xx_t clk; /* System Clock Module */ 742 pmc83xx_t pmc; /* Power Management Control Module */ 743 gpio83xx_t gpio[1]; /* General purpose I/O module */ 744 u8 res0[0x1300]; 745 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 746 fsl_i2c_t i2c[2]; /* I2C Controllers */ 747 u8 res1[0x1300]; 748 duart83xx_t duart[2]; /* DUART */ 749 u8 res2[0x900]; 750 fsl_lbus_t lbus; /* Local Bus Controller Registers */ 751 u8 res3[0x1000]; 752 spi8xxx_t spi; /* Serial Peripheral Interface */ 753 dma83xx_t dma; /* DMA */ 754 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ 755 u8 res4[0x80]; 756 ios83xx_t ios; /* Sequencer */ 757 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ 758 u8 res5[0xa00]; 759 pex83xx_t pciexp[2]; /* PCI Express Controller */ 760 u8 res6[0xb000]; 761 tdm83xx_t tdm; /* TDM Controller */ 762 u8 res7[0x1e00]; 763 sata83xx_t sata[2]; /* SATA Controller */ 764 u8 res8[0x9000]; 765 usb83xx_t usb[1]; /* USB DR Controller */ 766 tsec83xx_t tsec[2]; 767 u8 res9[0x6000]; 768 tdmdmac83xx_t tdmdmac; /* TDM DMAC */ 769 u8 res10[0x2000]; 770 security83xx_t security; 771 u8 res11[0xA3000]; 772 serdes83xx_t serdes[1]; /* SerDes Registers */ 773 u8 res12[0x1CF00]; 774} immap_t; 775 776#elif defined(CONFIG_MPC837X) 777typedef struct immap { 778 sysconf83xx_t sysconf; /* System configuration */ 779 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 780 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 781 rtclk83xx_t pit; /* Periodic Interval Timer */ 782 gtm83xx_t gtm[2]; /* Global Timers Module */ 783 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 784 arbiter83xx_t arbiter; /* System Arbiter Registers */ 785 reset83xx_t reset; /* Reset Module */ 786 clk83xx_t clk; /* System Clock Module */ 787 pmc83xx_t pmc; /* Power Management Control Module */ 788 gpio83xx_t gpio[2]; /* General purpose I/O module */ 789 u8 res0[0x1200]; 790 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 791 fsl_i2c_t i2c[2]; /* I2C Controllers */ 792 u8 res1[0x1300]; 793 duart83xx_t duart[2]; /* DUART */ 794 u8 res2[0x900]; 795 fsl_lbus_t lbus; /* Local Bus Controller Registers */ 796 u8 res3[0x1000]; 797 spi8xxx_t spi; /* Serial Peripheral Interface */ 798 dma83xx_t dma; /* DMA */ 799 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ 800 u8 res4[0x80]; 801 ios83xx_t ios; /* Sequencer */ 802 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ 803 u8 res5[0xa00]; 804 pex83xx_t pciexp[2]; /* PCI Express Controller */ 805 u8 res6[0xd000]; 806 sata83xx_t sata[4]; /* SATA Controller */ 807 u8 res7[0x7000]; 808 usb83xx_t usb[1]; /* USB DR Controller */ 809 tsec83xx_t tsec[2]; 810 u8 res8[0x8000]; 811 sdhc83xx_t sdhc; /* SDHC Controller */ 812 u8 res9[0x1000]; 813 security83xx_t security; 814 u8 res10[0xA3000]; 815 serdes83xx_t serdes[2]; /* SerDes Registers */ 816 u8 res11[0xCE00]; 817 rom83xx_t rom; /* On Chip ROM */ 818} immap_t; 819 820#elif defined(CONFIG_MPC8360) 821typedef struct immap { 822 sysconf83xx_t sysconf; /* System configuration */ 823 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 824 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 825 rtclk83xx_t pit; /* Periodic Interval Timer */ 826 u8 res0[0x200]; 827 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 828 arbiter83xx_t arbiter; /* System Arbiter Registers */ 829 reset83xx_t reset; /* Reset Module */ 830 clk83xx_t clk; /* System Clock Module */ 831 pmc83xx_t pmc; /* Power Management Control Module */ 832 qepi83xx_t qepi; /* QE Ports Interrupts Registers */ 833 u8 res1[0x300]; 834 u8 dll_ddr[0x100]; 835 u8 dll_lbc[0x100]; 836 u8 res2[0x200]; 837 qepio83xx_t qepio; /* QE Parallel I/O ports */ 838 qesba83xx_t qesba; /* QE Secondary Bus Access Windows */ 839 u8 res3[0x400]; 840 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 841 fsl_i2c_t i2c[2]; /* I2C Controllers */ 842 u8 res4[0x1300]; 843 duart83xx_t duart[2]; /* DUART */ 844 u8 res5[0x900]; 845 fsl_lbus_t lbus; /* Local Bus Controller Registers */ 846 u8 res6[0x2000]; 847 dma83xx_t dma; /* DMA */ 848 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ 849 u8 res7[128]; 850 ios83xx_t ios; /* Sequencer (IOS) */ 851 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ 852 u8 res8[0x4A00]; 853 ddr83xx_t ddr_secondary; /* Secondary DDR Memory Controller Memory Map */ 854 u8 res9[0x22000]; 855 security83xx_t security; 856 u8 res10[0xC0000]; 857 u8 qe[0x100000]; /* QE block */ 858} immap_t; 859 860#elif defined(CONFIG_MPC832X) 861typedef struct immap { 862 sysconf83xx_t sysconf; /* System configuration */ 863 wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */ 864 rtclk83xx_t rtc; /* Real Time Clock Module Registers */ 865 rtclk83xx_t pit; /* Periodic Interval Timer */ 866 gtm83xx_t gtm[2]; /* Global Timers Module */ 867 ipic83xx_t ipic; /* Integrated Programmable Interrupt Controller */ 868 arbiter83xx_t arbiter; /* System Arbiter Registers */ 869 reset83xx_t reset; /* Reset Module */ 870 clk83xx_t clk; /* System Clock Module */ 871 pmc83xx_t pmc; /* Power Management Control Module */ 872 qepi83xx_t qepi; /* QE Ports Interrupts Registers */ 873 u8 res0[0x300]; 874 u8 dll_ddr[0x100]; 875 u8 dll_lbc[0x100]; 876 u8 res1[0x200]; 877 qepio83xx_t qepio; /* QE Parallel I/O ports */ 878 u8 res2[0x800]; 879 ddr83xx_t ddr; /* DDR Memory Controller Memory */ 880 fsl_i2c_t i2c[2]; /* I2C Controllers */ 881 u8 res3[0x1300]; 882 duart83xx_t duart[2]; /* DUART */ 883 u8 res4[0x900]; 884 fsl_lbus_t lbus; /* Local Bus Controller Registers */ 885 u8 res5[0x2000]; 886 dma83xx_t dma; /* DMA */ 887 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */ 888 u8 res6[128]; 889 ios83xx_t ios; /* Sequencer (IOS) */ 890 pcictrl83xx_t pci_ctrl[1]; /* PCI Controller Control and Status Registers */ 891 u8 res7[0x27A00]; 892 security83xx_t security; 893 u8 res8[0xC0000]; 894 u8 qe[0x100000]; /* QE block */ 895} immap_t; 896#endif 897 898#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000) 899#define CONFIG_SYS_MPC83xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) 900#endif /* __IMMAP_83xx__ */ 901