1/* 2 * (C) Copyright 2001, 2002, 2003 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* ------------------------------------------------------------------------- */ 25/* 26 * Configuration settings for the A-3000 board (Artis Microsystems Inc.). 27 * http://artismicro.com 28 */ 29 30/* ------------------------------------------------------------------------- */ 31 32/* 33 * board/config.h - configuration options, board specific 34 */ 35 36#ifndef __CONFIG_H 37#define __CONFIG_H 38 39/* 40 * High Level Configuration Options 41 * (easy to change) 42 */ 43 44#define CONFIG_MPC824X 1 45#define CONFIG_MPC8245 1 46#define CONFIG_A3000 1 47 48 49#define CONFIG_CONS_INDEX 1 50#define CONFIG_BAUDRATE 9600 51#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 52 53#define CONFIG_BOOTDELAY 5 54 55 56/* 57 * BOOTP options 58 */ 59#define CONFIG_BOOTP_BOOTFILESIZE 60#define CONFIG_BOOTP_BOOTPATH 61#define CONFIG_BOOTP_GATEWAY 62#define CONFIG_BOOTP_HOSTNAME 63 64 65/* 66 * Command line configuration. 67 */ 68#include <config_cmd_default.h> 69 70 71/* 72 * Miscellaneous configurable options 73 */ 74#undef CONFIG_SYS_LONGHELP /* undef to save memory */ 75#define CONFIG_SYS_PROMPT "A3000> " /* Monitor Command Prompt */ 76#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 77 78/* Print Buffer Size 79 */ 80#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 81#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */ 82#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 83#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* Default load address */ 84 85/*----------------------------------------------------------------------- 86 * PCI stuff 87 *----------------------------------------------------------------------- 88 */ 89#define CONFIG_HARD_I2C 1 /* To enable I2C support */ 90#undef CONFIG_SOFT_I2C /* I2C bit-banged */ 91#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 92#define CONFIG_SYS_I2C_SLAVE 0x7F 93 94/*----------------------------------------------------------------------- 95 * PCI stuff 96 *----------------------------------------------------------------------- 97 */ 98#define CONFIG_PCI /* include pci support */ 99#undef CONFIG_PCI_PNP 100#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ 101 102#define CONFIG_NET_MULTI /* Multi ethernet cards support */ 103 104/* #define CONFIG_TULIP */ 105/* #define CONFIG_EEPRO100 */ 106#define CONFIG_NATSEMI 107 108#define PCI_ENET0_IOADDR 0x80000000 109#define PCI_ENET0_MEMADDR 0x80000000 110#define PCI_ENET1_IOADDR 0x81000000 111#define PCI_ENET1_MEMADDR 0x81000000 112#define PCI_ENET2_IOADDR 0x82000000 113#define PCI_ENET2_MEMADDR 0x82000000 114#define PCI_ENET3_IOADDR 0x83000000 115#define PCI_ENET3_MEMADDR 0x83000000 116 117 118/*----------------------------------------------------------------------- 119 * Start addresses for the final memory configuration 120 * (Set up by the startup code) 121 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 122 */ 123#define CONFIG_SYS_SDRAM_BASE 0x00000000 124 125#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */ 126#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ 127#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE0_PRELIM 128#define CONFIG_SYS_FLASH_BANKS { CONFIG_SYS_FLASH_BASE0_PRELIM } 129 130/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the 131 * reset vector is actually located at FFB00100, but the 8245 132 * takes care of us. 133 */ 134#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 135 136#define CONFIG_SYS_EUMB_ADDR 0xFC000000 137 138#define CONFIG_SYS_MONITOR_BASE TEXT_BASE 139#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 140#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 141 142#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ 143#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ 144 145 /* Maximum amount of RAM. 146 */ 147#define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 0 .. 128 MB of (S)DRAM */ 148 149 150#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE 151#undef CONFIG_SYS_RAMBOOT 152#else 153#define CONFIG_SYS_RAMBOOT 154#endif 155 156/* 157 * NS16550 Configuration 158 */ 159#define CONFIG_SYS_NS16550 160#define CONFIG_SYS_NS16550_SERIAL 161 162#define CONFIG_SYS_NS16550_REG_SIZE 1 163 164#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 165 166#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) 167#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) 168 169/*----------------------------------------------------------------------- 170 * Definitions for initial stack pointer and data area 171 */ 172 173/* #define CONFIG_SYS_MONITOR_BASE TEXT_BASE */ 174/*#define CONFIG_SYS_GBL_DATA_SIZE 256*/ 175#define CONFIG_SYS_GBL_DATA_SIZE 128 176#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 177#define CONFIG_SYS_INIT_RAM_END 0x1000 178#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 179 180 181/* 182 * Low Level Configuration Settings 183 * (address mappings, register initial values, etc.) 184 * You should know what you are doing if you make changes here. 185 * For the detail description refer to the MPC8240 user's manual. 186 */ 187 188#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ 189#define CONFIG_SYS_HZ 1000 190 191 /* Bit-field values for MCCR1. 192 */ 193#define CONFIG_SYS_ROMNAL 7 194#define CONFIG_SYS_ROMFAL 11 195#define CONFIG_SYS_DBUS_SIZE 0x3 196 197 /* Bit-field values for MCCR2. 198 */ 199#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ 200#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ 201 202 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. 203 */ 204#define CONFIG_SYS_BSTOPRE 121 205 206 /* Bit-field values for MCCR3. 207 */ 208#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ 209 210 /* Bit-field values for MCCR4. 211 */ 212#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */ 213#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ 214#define CONFIG_SYS_ACTORW 3 /* FIXME was 2 */ 215#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ 216#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ 217#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 218#define CONFIG_SYS_EXTROM 1 219#define CONFIG_SYS_REGDIMM 0 220 221#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ 222 223#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ 224 225/* Memory bank settings. 226 * Only bits 20-29 are actually used from these vales to set the 227 * start/end addresses. The upper two bits will always be 0, and the lower 228 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end 229 * address. Refer to the MPC8240 book. 230 */ 231 232#define CONFIG_SYS_BANK0_START 0x00000000 233#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) 234#define CONFIG_SYS_BANK0_ENABLE 1 235#define CONFIG_SYS_BANK1_START 0x3ff00000 236#define CONFIG_SYS_BANK1_END 0x3fffffff 237#define CONFIG_SYS_BANK1_ENABLE 0 238#define CONFIG_SYS_BANK2_START 0x3ff00000 239#define CONFIG_SYS_BANK2_END 0x3fffffff 240#define CONFIG_SYS_BANK2_ENABLE 0 241#define CONFIG_SYS_BANK3_START 0x3ff00000 242#define CONFIG_SYS_BANK3_END 0x3fffffff 243#define CONFIG_SYS_BANK3_ENABLE 0 244#define CONFIG_SYS_BANK4_START 0x3ff00000 245#define CONFIG_SYS_BANK4_END 0x3fffffff 246#define CONFIG_SYS_BANK4_ENABLE 0 247#define CONFIG_SYS_BANK5_START 0x3ff00000 248#define CONFIG_SYS_BANK5_END 0x3fffffff 249#define CONFIG_SYS_BANK5_ENABLE 0 250#define CONFIG_SYS_BANK6_START 0x3ff00000 251#define CONFIG_SYS_BANK6_END 0x3fffffff 252#define CONFIG_SYS_BANK6_ENABLE 0 253#define CONFIG_SYS_BANK7_START 0x3ff00000 254#define CONFIG_SYS_BANK7_END 0x3fffffff 255#define CONFIG_SYS_BANK7_ENABLE 0 256 257#define CONFIG_SYS_ODCR 0xff 258 259#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 260#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 261 262#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) 263#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 264 265#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 266#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) 267 268#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 269#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 270 271#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 272#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 273#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 274#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 275#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 276#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 277#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 278#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 279 280/* 281 * For booting Linux, the board info and command line data 282 * have to be in the first 8 MB of memory, since this is 283 * the maximum mapped by the Linux kernel during initialization. 284 */ 285#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 286 287/*----------------------------------------------------------------------- 288 * FLASH organization 289 */ 290#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ 291#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max number of sectors per flash */ 292 293#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 294#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 295 296 297 /* Warining: environment is not EMBEDDED in the U-Boot code. 298 * It's stored in flash separately. 299 */ 300#define CONFIG_ENV_IS_IN_FLASH 1 301#define CONFIG_ENV_ADDR 0xFFFE0000 302#define CONFIG_ENV_SIZE 0x00020000 /* Size of the Environment */ 303#define CONFIG_ENV_SECT_SIZE 0x00020000 /* Size of the Environment Sector */ 304 305/*----------------------------------------------------------------------- 306 * Cache Configuration 307 */ 308#define CONFIG_SYS_CACHELINE_SIZE 32 309#if defined(CONFIG_CMD_KGDB) 310# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 311#endif 312 313/* 314 * Internal Definitions 315 * 316 * Boot Flags 317 */ 318#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 319#define BOOTFLAG_WARM 0x02 /* Software reboot */ 320 321#endif /* __CONFIG_H */ 322