1/* 2 * Copyright (C) 2004-2005 Arabella Software Ltd. 3 * Yuli Barcohen <yuli@arabellasw.com> 4 * 5 * Support for Analogue&Micro Adder boards family. 6 * Tested on AdderII and Adder87x. 7 * 8 * See file CREDITS for list of people who contributed to this 9 * project. 10 * 11 * This program is free software; you can redistribute it and/or 12 * modify it under the terms of the GNU General Public License as 13 * published by the Free Software Foundation; either version 2 of 14 * the License, or (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 24 * MA 02111-1307 USA 25 */ 26#ifndef __CONFIG_H 27#define __CONFIG_H 28 29#if !defined(CONFIG_MPC875) && !defined(CONFIG_MPC852T) 30#define CONFIG_MPC875 31#endif 32 33#define CONFIG_ADDER /* Analogue&Micro Adder board */ 34 35#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 36#define CONFIG_BAUDRATE 38400 37 38#define CONFIG_ETHER_ON_FEC1 39#define CONFIG_ETHER_ON_FEC2 40#define CONFIG_HAS_ETH0 41#define CONFIG_HAS_ETH1 42 43#if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) 44#define CONFIG_SYS_DISCOVER_PHY 45#define CONFIG_MII_INIT 1 46#define FEC_ENET 47#endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */ 48 49#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ 50#define CONFIG_8xx_CPUCLK_DEFAULT 50000000 51#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000 52#ifdef CONFIG_MPC852T 53#define CONFIG_SYS_8xx_CPUCLK_MAX 50000000 54#else 55#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 56#endif /* CONFIG_MPC852T */ 57 58 59/* 60 * BOOTP options 61 */ 62#define CONFIG_BOOTP_BOOTFILESIZE 63#define CONFIG_BOOTP_BOOTPATH 64#define CONFIG_BOOTP_GATEWAY 65#define CONFIG_BOOTP_HOSTNAME 66 67 68/* 69 * Command line configuration. 70 */ 71#include <config_cmd_default.h> 72 73#define CONFIG_CMD_DHCP 74#define CONFIG_CMD_IMMAP 75#define CONFIG_CMD_MII 76#define CONFIG_CMD_PING 77 78 79#define CONFIG_BOOTDELAY 5 /* Autoboot after 5 seconds */ 80#define CONFIG_BOOTCOMMAND "bootm fe040000" /* Autoboot command */ 81#define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw mtdparts=1M(ROM)ro,-(root)" 82 83#define CONFIG_BZIP2 /* Include support for bzip2 compressed images */ 84#undef CONFIG_WATCHDOG /* Disable platform specific watchdog */ 85 86/*----------------------------------------------------------------------- 87 * Miscellaneous configurable options 88 */ 89#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 90#define CONFIG_SYS_HUSH_PARSER 91#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 92#define CONFIG_SYS_LONGHELP /* #undef to save memory */ 93#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 94#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ 95#define CONFIG_SYS_MAXARGS 16 /* Max number of command args */ 96#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 97 98#define CONFIG_SYS_LOAD_ADDR 0x400000 /* Default load address */ 99 100#define CONFIG_SYS_HZ 1000 /* Decrementer freq: 1 ms ticks */ 101 102#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 103 104/*----------------------------------------------------------------------- 105 * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero) 106 */ 107#define CONFIG_SYS_SDRAM_BASE 0x00000000 108#define CONFIG_SYS_SDRAM_MAX_SIZE 0x01000000 /* Up to 16 Mbyte */ 109 110#define CONFIG_SYS_MAMR 0x00002114 111 112/* 113 * 4096 Up to 4096 SDRAM rows 114 * 1000 factor s -> ms 115 * 32 PTP (pre-divider from MPTPR) 116 * 4 Number of refresh cycles per period 117 * 64 Refresh cycle in ms per number of rows 118 */ 119#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 120 121#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 122#define CONFIG_SYS_MEMTEST_END 0x00500000 /* 1 ... 5 MB in SDRAM */ 123 124#define CONFIG_SYS_RESET_ADDRESS 0x09900000 125 126/*----------------------------------------------------------------------- 127 * For booting Linux, the board info and command line data 128 * have to be in the first 8 MB of memory, since this is 129 * the maximum mapped by the Linux kernel during initialization. 130 */ 131#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 132 133#define CONFIG_SYS_MONITOR_BASE TEXT_BASE 134#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for Monitor */ 135#ifdef CONFIG_BZIP2 136#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ 137#else 138#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 KB for malloc() */ 139#endif /* CONFIG_BZIP2 */ 140 141/*----------------------------------------------------------------------- 142 * Flash organisation 143 */ 144#define CONFIG_SYS_FLASH_BASE 0xFE000000 145#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ 146#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 147#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ 148#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max num of sects on one chip */ 149 150/* Environment is in flash */ 151#define CONFIG_ENV_IS_IN_FLASH 152#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */ 153#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 154 155#define CONFIG_ENV_OVERWRITE 156 157#define CONFIG_SYS_OR0_PRELIM 0xFF000774 158#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_MS_GPCM | BR_V) 159 160#define CONFIG_SYS_DIRECT_FLASH_TFTP 161 162/*----------------------------------------------------------------------- 163 * Internal Memory Map Register 164 */ 165#define CONFIG_SYS_IMMR 0xFF000000 166 167/*----------------------------------------------------------------------- 168 * Definitions for initial stack pointer and data area (in DPRAM) 169 */ 170#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 171#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ 172#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Size in bytes reserved for initial data */ 173#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 174#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 175 176/*----------------------------------------------------------------------- 177 * Configuration registers 178 */ 179#ifdef CONFIG_WATCHDOG 180#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ 181 SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \ 182 SYPCR_SWP) 183#else 184#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \ 185 SYPCR_SWF | SYPCR_SWP) 186#endif /* CONFIG_WATCHDOG */ 187 188#define CONFIG_SYS_SIUMCR (SIUMCR_MLRC01 | SIUMCR_DBGC11) 189 190/* TBSCR - Time Base Status and Control Register */ 191#define CONFIG_SYS_TBSCR (TBSCR_TBF | TBSCR_TBE) 192 193/* PISCR - Periodic Interrupt Status and Control */ 194#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 195 196/* PLPRCR - PLL, Low-Power, and Reset Control Register */ 197/* #define CONFIG_SYS_PLPRCR PLPRCR_TEXPS */ 198 199/* SCCR - System Clock and reset Control Register */ 200#define SCCR_MASK SCCR_EBDF11 201#define CONFIG_SYS_SCCR SCCR_RTSEL 202 203#define CONFIG_SYS_DER 0 204 205/*----------------------------------------------------------------------- 206 * Cache Configuration 207 */ 208#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx chips */ 209 210/*----------------------------------------------------------------------- 211 * Internal Definitions 212 * 213 * Boot Flags 214 */ 215#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from flash */ 216#define BOOTFLAG_WARM 0x02 /* Software reboot */ 217 218/* pass open firmware flat tree */ 219#define CONFIG_OF_LIBFDT 1 220#define CONFIG_OF_BOARD_SETUP 1 221 222#endif /* __CONFIG_H */ 223