1/* 2 * (C) Copyright 2001 3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_405GP 1 /* This is a PPC405 CPU */ 37#define CONFIG_4xx 1 /* ...member of PPC4xx family */ 38#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ 39 40#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ 41 42#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ 43 44#define CONFIG_BAUDRATE 9600 45#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 46 47#undef CONFIG_BOOTARGS 48#undef CONFIG_BOOTCOMMAND 49 50#define CONFIG_PREBOOT /* enable preboot variable */ 51 52#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 53#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 54 55#define CONFIG_PPC4xx_EMAC 56#define CONFIG_MII 1 /* MII PHY management */ 57#define CONFIG_PHY_ADDR 0 /* PHY address */ 58#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ 59#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ 60 61#define CONFIG_NET_MULTI 1 62#undef CONFIG_HAS_ETH1 63 64/* 65 * BOOTP options 66 */ 67#define CONFIG_BOOTP_SUBNETMASK 68#define CONFIG_BOOTP_GATEWAY 69#define CONFIG_BOOTP_HOSTNAME 70#define CONFIG_BOOTP_BOOTPATH 71#define CONFIG_BOOTP_DNS 72#define CONFIG_BOOTP_DNS2 73#define CONFIG_BOOTP_SEND_HOSTNAME 74 75 76/* 77 * Command line configuration. 78 */ 79#include <config_cmd_default.h> 80 81#define CONFIG_CMD_DHCP 82#define CONFIG_CMD_PCI 83#define CONFIG_CMD_IRQ 84#define CONFIG_CMD_IDE 85#define CONFIG_CMD_FAT 86#define CONFIG_CMD_ELF 87#define CONFIG_CMD_MII 88#define CONFIG_CMD_EEPROM 89 90 91#define CONFIG_MAC_PARTITION 92#define CONFIG_DOS_PARTITION 93 94#define CONFIG_SUPPORT_VFAT 95 96#undef CONFIG_WATCHDOG /* watchdog disabled */ 97 98#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ 99 100/* 101 * Miscellaneous configurable options 102 */ 103#define CONFIG_SYS_LONGHELP /* undef to save memory */ 104#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 105 106#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ 107#ifdef CONFIG_SYS_HUSH_PARSER 108#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 109#endif 110 111#if defined(CONFIG_CMD_KGDB) 112#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 113#else 114#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 115#endif 116#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 117#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 118#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 119 120#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */ 121 122#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ 123 124#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 125#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 126 127#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ 128#define CONFIG_SYS_BASE_BAUD 691200 129 130/* The following table includes the supported baudrates */ 131#define CONFIG_SYS_BAUDRATE_TABLE \ 132 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 133 57600, 115200, 230400, 460800, 921600 } 134 135#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 136#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 137 138#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 139 140#define CONFIG_LOOPW 1 /* enable loopw command */ 141 142#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ 143 144/*----------------------------------------------------------------------- 145 * PCI stuff 146 *----------------------------------------------------------------------- 147 */ 148#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ 149#define PCI_HOST_FORCE 1 /* configure as pci host */ 150#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 151 152#define CONFIG_PCI /* include pci support */ 153#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ 154#define CONFIG_PCI_PNP /* do pci plug-and-play */ 155 /* resource configuration */ 156 157#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ 158 159#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/ 160 161#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ 162 163#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ 164#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ 165#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ 166#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ 167#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ 168#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ 169#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ 170#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ 171#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ 172#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ 173 174/*----------------------------------------------------------------------- 175 * IDE/ATA stuff 176 *----------------------------------------------------------------------- 177 */ 178#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ 179#undef CONFIG_IDE_LED /* no led for ide supported */ 180#undef CONFIG_IDE_RESET /* no reset for ide supported */ 181 182#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE busses */ 183#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */ 184 185#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000 186#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 187 188#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */ 189#define CONFIG_SYS_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */ 190#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */ 191 192/*----------------------------------------------------------------------- 193 * Start addresses for the final memory configuration 194 * (Set up by the startup code) 195 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 196 */ 197#define CONFIG_SYS_SDRAM_BASE 0x00000000 198#define CONFIG_SYS_FLASH_BASE TEXT_BASE 199#define CONFIG_SYS_MONITOR_BASE TEXT_BASE 200#define CONFIG_SYS_MONITOR_LEN (~(TEXT_BASE) + 1) 201#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ 202 203/* 204 * For booting Linux, the board info and command line data 205 * have to be in the first 8 MB of memory, since this is 206 * the maximum mapped by the Linux kernel during initialization. 207 */ 208#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 209/*----------------------------------------------------------------------- 210 * FLASH organization 211 */ 212#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 213#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 214 215#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 216#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 217 218#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ 219#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ 220#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ 221/* 222 * The following defines are added for buggy IOP480 byte interface. 223 * All other boards should use the standard values (CPCI405 etc.) 224 */ 225#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ 226#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ 227#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ 228 229#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 230 231#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ 232#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ 233#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/ 234 235#if 1 /* Use NVRAM for environment variables */ 236/*----------------------------------------------------------------------- 237 * NVRAM organization 238 */ 239#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ 240#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ 241#define CONFIG_ENV_ADDR \ 242 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ 243 244#else /* Use EEPROM for environment variables */ 245 246#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 247#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ 248#define CONFIG_ENV_SIZE 0x400 /* 1024 bytes may be used for env vars */ 249 /* total size of a CAT24WC08 is 1024 bytes */ 250#endif 251 252/*----------------------------------------------------------------------- 253 * I2C EEPROM (CAT24WC08) for environment 254 */ 255#define CONFIG_HARD_I2C /* I2c with hardware support */ 256#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 257#define CONFIG_SYS_I2C_SLAVE 0x7F 258 259#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ 260#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 261/* mask of address bits that overflow into the "EEPROM chip address" */ 262#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 263#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ 264 /* 16 byte page write mode using*/ 265 /* last 4 bits of the address */ 266#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 267 268/* 269 * Init Memory Controller: 270 * 271 * BR0/1 and OR0/1 (FLASH) 272 */ 273 274#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ 275#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ 276 277/*----------------------------------------------------------------------- 278 * External Bus Controller (EBC) Setup 279 */ 280 281/* Memory Bank 0 (Flash Bank 0) initialization */ 282#define CONFIG_SYS_EBC_PB0AP 0x92015480 283#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ 284 285/* Memory Bank 1 (Flash Bank 1) initialization */ 286#define CONFIG_SYS_EBC_PB1AP 0x92015480 287#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ 288 289/* Memory Bank 2 (CAN0, 1, 2, Codeswitch) initialization */ 290#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ 291#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ 292 293/* Memory Bank 3 (CompactFlash IDE) initialization */ 294#define CONFIG_SYS_EBC_PB3AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */ 295#define CONFIG_SYS_EBC_PB3CR 0xF011A000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */ 296 297/* Memory Bank 4 (NVRAM) initialization */ 298#define CONFIG_SYS_EBC_PB4AP 0x01005280 /* TWT=2,WBN=1,WBF=1,TH=1,SOR=1 */ 299#define CONFIG_SYS_EBC_PB4CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */ 300 301/* Memory Bank 5 (Quart) initialization */ 302#define CONFIG_SYS_EBC_PB5AP 0x04005B80 /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/ 303#define CONFIG_SYS_EBC_PB5CR 0xF0318000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit */ 304 305/*----------------------------------------------------------------------- 306 * FPGA stuff 307 */ 308 309/* FPGA program pin configuration */ 310#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */ 311#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */ 312#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */ 313#define CONFIG_SYS_FPGA_INIT 0x00400000 /* FPGA init pin (ppc input) */ 314#define CONFIG_SYS_FPGA_DONE 0x00800000 /* FPGA done pin (ppc input) */ 315 316/*----------------------------------------------------------------------- 317 * Definitions for initial stack pointer and data area (in data cache) 318 */ 319#if 1 /* test-only */ 320#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ 321 322#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ 323#else 324#define CONFIG_SYS_INIT_RAM_ADDR 0x00df0000 /* inside of SDRAM */ 325#endif 326#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ 327#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 328#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 329#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 330 331 332/* 333 * Internal Definitions 334 * 335 * Boot Flags 336 */ 337#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 338#define BOOTFLAG_WARM 0x02 /* Software reboot */ 339 340#endif /* __CONFIG_H */ 341