1/* 2 * (C) Copyright 2001-2003 3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_405GP 1 /* This is a PPC405 CPU */ 37#define CONFIG_4xx 1 /* ...member of PPC4xx family */ 38#define CONFIG_CPCIISER4 1 /* ...on a CPCIISER4 board */ 39 40#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ 41 42#define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */ 43 44#define CONFIG_BAUDRATE 9600 45#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 46 47#undef CONFIG_BOOTARGS 48#define CONFIG_BOOTCOMMAND "bootm fff00000" 49 50#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 51#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 52 53#define CONFIG_PPC4xx_EMAC 54#define CONFIG_MII 1 /* MII PHY management */ 55#define CONFIG_PHY_ADDR 0 /* PHY address */ 56#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ 57 58 59/* 60 * BOOTP options 61 */ 62#define CONFIG_BOOTP_BOOTFILESIZE 63#define CONFIG_BOOTP_BOOTPATH 64#define CONFIG_BOOTP_GATEWAY 65#define CONFIG_BOOTP_HOSTNAME 66 67 68/* 69 * BOOTP options 70 */ 71#define CONFIG_BOOTP_BOOTFILESIZE 72#define CONFIG_BOOTP_BOOTPATH 73#define CONFIG_BOOTP_GATEWAY 74#define CONFIG_BOOTP_HOSTNAME 75 76 77/* 78 * Command line configuration. 79 */ 80#include <config_cmd_default.h> 81 82#define CONFIG_CMD_PCI 83#define CONFIG_CMD_IRQ 84#define CONFIG_CMD_MII 85#define CONFIG_CMD_ELF 86#define CONFIG_CMD_EEPROM 87 88 89#undef CONFIG_WATCHDOG /* watchdog disabled */ 90 91#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ 92 93/* 94 * Miscellaneous configurable options 95 */ 96#define CONFIG_SYS_LONGHELP /* undef to save memory */ 97#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 98#if defined(CONFIG_CMD_KGDB) 99#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 100#else 101#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 102#endif 103#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 104#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 105#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 106 107#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ 108 109#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 110#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 111 112#define CONFIG_SYS_EXT_SERIAL_CLOCK 1843200 /* use external serial clock */ 113 114/* The following table includes the supported baudrates */ 115#define CONFIG_SYS_BAUDRATE_TABLE \ 116 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 117 57600, 115200, 230400, 460800, 921600 } 118 119#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 120#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 121 122#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 123 124#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ 125 126/*----------------------------------------------------------------------- 127 * PCI stuff 128 *----------------------------------------------------------------------- 129 */ 130#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ 131#define PCI_HOST_FORCE 1 /* configure as pci host */ 132#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 133 134#define CONFIG_PCI /* include pci support */ 135#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ 136#define CONFIG_PCI_PNP /* do pci plug-and-play */ 137 /* resource configuration */ 138 139#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ 140#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */ 141#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ 142#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ 143#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ 144#define CONFIG_SYS_PCI_PTM2LA 0xffe00000 /* point to flash */ 145#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ 146#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ 147 148/*----------------------------------------------------------------------- 149 * Start addresses for the final memory configuration 150 * (Set up by the startup code) 151 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 152 */ 153#define CONFIG_SYS_SDRAM_BASE 0x00000000 154#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 155#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 156#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ 157#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ 158 159/* 160 * For booting Linux, the board info and command line data 161 * have to be in the first 8 MB of memory, since this is 162 * the maximum mapped by the Linux kernel during initialization. 163 */ 164#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 165/*----------------------------------------------------------------------- 166 * FLASH organization 167 */ 168#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 169#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 170 171#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 172#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 173 174#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ 175#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ 176#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ 177/* 178 * The following defines are added for buggy IOP480 byte interface. 179 * All other boards should use the standard values (CPCI405 etc.) 180 */ 181#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ 182#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ 183#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ 184 185#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 186 187/*----------------------------------------------------------------------- 188 * I2C EEPROM (CAT24WC08) for environment 189 */ 190#define CONFIG_HARD_I2C /* I2C with hardware support */ 191#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 192#define CONFIG_SYS_I2C_SLAVE 0x7F 193 194#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ 195#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 196/* mask of address bits that overflow into the "EEPROM chip address" */ 197#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 198#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ 199 /* 16 byte page write mode using*/ 200 /* last 4 bits of the address */ 201#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 202 203#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 204#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ 205#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ 206 /* total size of a CAT24WC08 is 1024 bytes */ 207 208/* 209 * Init Memory Controller: 210 * 211 * BR0/1 and OR0/1 (FLASH) 212 */ 213 214#define FLASH_BASE0_PRELIM 0xFFF00000 /* FLASH bank #0 */ 215#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ 216 217/*----------------------------------------------------------------------- 218 * External Bus Controller (EBC) Setup 219 */ 220 221/* Memory Bank 0 (Flash Bank 0) initialization */ 222#define CONFIG_SYS_EBC_PB0AP 0x92015480 223#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ 224 225/* Memory Bank 1 (Uart 8bit) initialization */ 226#define CONFIG_SYS_EBC_PB1AP 0x01000480 /* TWT=2,TH=2,no Ready,BEM=0,SOR=1 */ 227#define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ 228 229/* Memory Bank 2 (Uart 32bit) initialization */ 230#define CONFIG_SYS_EBC_PB2AP 0x000004c0 /* no Ready, BEM=1 */ 231#define CONFIG_SYS_EBC_PB2CR 0xF011C000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=32bit */ 232 233/* Memory Bank 3 (FPGA Reset) initialization */ 234#define CONFIG_SYS_EBC_PB3AP 0x010004C0 /* no Ready, BEM=1 */ 235#define CONFIG_SYS_EBC_PB3CR 0xF021A000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */ 236 237/*----------------------------------------------------------------------- 238 * Definitions for initial stack pointer and data area (in DPRAM) 239 */ 240#define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */ 241#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */ 242#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */ 243#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 244#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 245#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 246 247/* 248 * Internal Definitions 249 * 250 * Boot Flags 251 */ 252#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 253#define BOOTFLAG_WARM 0x02 /* Software reboot */ 254 255#endif /* __CONFIG_H */ 256