1/* 2 * (C) Copyright 2005 3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ 37#define CONFIG_MPC8272_FAMILY 1 38#define CONFIG_IDS8247 1 39#define CPU_ID_STR "MPC8247" 40#define CONFIG_CPM2 1 /* Has a CPM2 */ 41 42#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 43 44#define CONFIG_BOOTCOUNT_LIMIT 45 46#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 47 48#undef CONFIG_BOOTARGS 49 50#define CONFIG_EXTRA_ENV_SETTINGS \ 51 "netdev=eth0\0" \ 52 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 53 "nfsroot=${serverip}:${rootpath}\0" \ 54 "ramargs=setenv bootargs root=/dev/ram rw " \ 55 "console=ttyS0,115200\0" \ 56 "addip=setenv bootargs ${bootargs} " \ 57 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 58 ":${hostname}:${netdev}:off panic=1\0" \ 59 "flash_nfs=run nfsargs addip;" \ 60 "bootm ${kernel_addr}\0" \ 61 "flash_self=run ramargs addip;" \ 62 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 63 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 64 "rootpath=/opt/eldk/ppc_82xx\0" \ 65 "bootfile=/tftpboot/IDS8247/uImage\0" \ 66 "kernel_addr=ff800000\0" \ 67 "ramdisk_addr=ffa00000\0" \ 68 "" 69#define CONFIG_BOOTCOMMAND "run flash_self" 70 71#define CONFIG_MISC_INIT_R 1 72 73/* enable I2C and select the hardware/software driver */ 74#undef CONFIG_HARD_I2C /* I2C with hardware support */ 75#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ 76#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 77#define CONFIG_SYS_I2C_SLAVE 0x7F 78 79/* 80 * Software (bit-bang) I2C driver configuration 81 */ 82 83#define I2C_PORT 0 /* Port A=0, B=1, C=2, D=3 */ 84#define I2C_ACTIVE (iop->pdir |= 0x00000080) 85#define I2C_TRISTATE (iop->pdir &= ~0x00000080) 86#define I2C_READ ((iop->pdat & 0x00000080) != 0) 87#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00000080; \ 88 else iop->pdat &= ~0x00000080 89#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00000100; \ 90 else iop->pdat &= ~0x00000100 91#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 92 93#if 0 94#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 95#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 96#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 97#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 98 99#define CONFIG_I2C_X 100#endif 101 102/* 103 * select serial console configuration 104 * use the extern UART for the console 105 */ 106#define CONFIG_CONS_INDEX 1 107#define CONFIG_BAUDRATE 115200 108/* 109 * NS16550 Configuration 110 */ 111#define CONFIG_SYS_NS16550 112#define CONFIG_SYS_NS16550_SERIAL 113 114#define CONFIG_SYS_NS16550_REG_SIZE 1 115 116#define CONFIG_SYS_NS16550_CLK 14745600 117 118#define CONFIG_SYS_UART_BASE 0xE0000000 119#define CONFIG_SYS_UART_SIZE 0x10000 120 121#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_UART_BASE + 0x8000) 122 123 124/* pass open firmware flat tree */ 125#define CONFIG_OF_LIBFDT 1 126#define CONFIG_OF_BOARD_SETUP 1 127 128#define OF_CPU "PowerPC,8247@0" 129#define OF_SOC "soc@f0000000" 130#define OF_TBCLK (bd->bi_busfreq / 4) 131#define OF_STDOUT_PATH "/soc@f0000000/serial8250@e0008000" 132 133 134/* 135 * select ethernet configuration 136 * 137 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then 138 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 139 * for FCC) 140 * 141 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be 142 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. 143 */ 144#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ 145#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ 146#undef CONFIG_ETHER_NONE /* define if ether on something else */ 147#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */ 148#define CONFIG_ETHER_ON_FCC1 149#define FCC_ENET 150 151/* 152 * - Rx-CLK is CLK10 153 * - Tx-CLK is CLK9 154 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 155 * - Enable Full Duplex in FSMR 156 */ 157# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) 158# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9) 159# define CONFIG_SYS_CPMFCR_RAMTYPE 0 160# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 161 162 163/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ 164#define CONFIG_8260_CLKIN 66666666 /* in Hz */ 165 166#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 167#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 168 169#undef CONFIG_WATCHDOG /* watchdog disabled */ 170 171#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 172 173/* 174 * BOOTP options 175 */ 176#define CONFIG_BOOTP_SUBNETMASK 177#define CONFIG_BOOTP_GATEWAY 178#define CONFIG_BOOTP_HOSTNAME 179#define CONFIG_BOOTP_BOOTPATH 180#define CONFIG_BOOTP_BOOTFILESIZE 181 182#define CONFIG_RTC_PCF8563 183#define CONFIG_SYS_I2C_RTC_ADDR 0x51 184 185/* 186 * Command line configuration. 187 */ 188#include <config_cmd_default.h> 189 190#define CONFIG_CMD_DHCP 191#define CONFIG_CMD_NFS 192#define CONFIG_CMD_NAND 193#define CONFIG_CMD_I2C 194#define CONFIG_CMD_SNTP 195 196 197/* 198 * Miscellaneous configurable options 199 */ 200#define CONFIG_SYS_LONGHELP /* undef to save memory */ 201#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 202#if defined(CONFIG_CMD_KGDB) 203#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 204#else 205#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 206#endif 207#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 208#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 209#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 210 211#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 212#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 213 214#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 215 216#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 217 218#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 219 220#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ 221 222/* 223 * For booting Linux, the board info and command line data 224 * have to be in the first 8 MB of memory, since this is 225 * the maximum mapped by the Linux kernel during initialization. 226 */ 227#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 228 229#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ 230#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 231#define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 } 232#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 233/* What should the base address of the main FLASH be and how big is 234 * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk 235 * The main FLASH is whichever is connected to *CS0. 236 */ 237#define CONFIG_SYS_FLASH0_BASE 0xFFF00000 238#define CONFIG_SYS_FLASH0_SIZE 8 239 240/* Flash bank size (for preliminary settings) 241 */ 242#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE 243 244/*----------------------------------------------------------------------- 245 * FLASH organization 246 */ 247#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 248#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ 249 250#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ 251#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 252 253/* Environment in flash */ 254#define CONFIG_ENV_IS_IN_FLASH 1 255#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x60000) 256#define CONFIG_ENV_SIZE 0x20000 257#define CONFIG_ENV_SECT_SIZE 0x20000 258 259/*----------------------------------------------------------------------- 260 * NAND-FLASH stuff 261 *----------------------------------------------------------------------- 262 */ 263#if defined(CONFIG_CMD_NAND) 264 265#define CONFIG_NAND_LEGACY 266#define CONFIG_SYS_NAND0_BASE 0xE1000000 267 268#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ 269#define SECTORSIZE 512 270#define NAND_NO_RB 271 272#define ADDR_COLUMN 1 273#define ADDR_PAGE 2 274#define ADDR_COLUMN_PAGE 3 275 276#define NAND_ChipID_UNKNOWN 0x00 277#define NAND_MAX_FLOORS 1 278 279#define NAND_DISABLE_CE(nand) do \ 280{ \ 281 *(((volatile __u8 *)(nand->IO_ADDR)) + 0xc) = 0; \ 282} while(0) 283 284#define NAND_ENABLE_CE(nand) do \ 285{ \ 286 *(((volatile __u8 *)(nand->IO_ADDR)) + 0x8) = 0; \ 287} while(0) 288 289#define NAND_CTL_CLRALE(nandptr) do \ 290{ \ 291 *(((volatile __u8 *)nandptr) + 0x8) = 0; \ 292} while(0) 293 294#define NAND_CTL_SETALE(nandptr) do \ 295{ \ 296 *(((volatile __u8 *)nandptr) + 0x9) = 0; \ 297} while(0) 298 299#define NAND_CTL_CLRCLE(nandptr) do \ 300{ \ 301 *(((volatile __u8 *)nandptr) + 0x8) = 0; \ 302} while(0) 303 304#define NAND_CTL_SETCLE(nandptr) do \ 305{ \ 306 *(((volatile __u8 *)nandptr) + 0xa) = 0; \ 307} while(0) 308 309#ifdef NAND_NO_RB 310/* constant delay (see also tR in the datasheet) */ 311#define NAND_WAIT_READY(nand) do { \ 312 udelay(12); \ 313} while (0) 314#else 315/* use the R/B pin */ 316#endif 317 318#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x2)) = (__u8)(d); } while(0) 319#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x1)) = (__u8)(d); } while(0) 320#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0) 321#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0))) 322 323#endif /* CONFIG_CMD_NAND */ 324 325/*----------------------------------------------------------------------- 326 * Hard Reset Configuration Words 327 * 328 * if you change bits in the HRCW, you must also change the CONFIG_SYS_* 329 * defines for the various registers affected by the HRCW e.g. changing 330 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. 331 */ 332#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000) 333 334/* no slaves so just fill with zeros */ 335#define CONFIG_SYS_HRCW_SLAVE1 0 336#define CONFIG_SYS_HRCW_SLAVE2 0 337#define CONFIG_SYS_HRCW_SLAVE3 0 338#define CONFIG_SYS_HRCW_SLAVE4 0 339#define CONFIG_SYS_HRCW_SLAVE5 0 340#define CONFIG_SYS_HRCW_SLAVE6 0 341#define CONFIG_SYS_HRCW_SLAVE7 0 342 343/*----------------------------------------------------------------------- 344 * Internal Memory Mapped Register 345 */ 346#define CONFIG_SYS_IMMR 0xF0000000 347 348/*----------------------------------------------------------------------- 349 * Definitions for initial stack pointer and data area (in DPRAM) 350 */ 351#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 352#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ 353#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ 354#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 355#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 356 357/*----------------------------------------------------------------------- 358 * Start addresses for the final memory configuration 359 * (Set up by the startup code) 360 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 361 * 362 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE 363 */ 364#define CONFIG_SYS_SDRAM_BASE 0x00000000 365#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE 366#define CONFIG_SYS_MONITOR_BASE TEXT_BASE 367#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 368#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ 369 370/* 371 * Internal Definitions 372 * 373 * Boot Flags 374 */ 375#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ 376#define BOOTFLAG_WARM 0x02 /* Software reboot */ 377 378 379/*----------------------------------------------------------------------- 380 * Cache Configuration 381 */ 382#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 383#if defined(CONFIG_CMD_KGDB) 384# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 385#endif 386 387/*----------------------------------------------------------------------- 388 * HIDx - Hardware Implementation-dependent Registers 2-11 389 *----------------------------------------------------------------------- 390 * HID0 also contains cache control - initially enable both caches and 391 * invalidate contents, then the final state leaves only the instruction 392 * cache enabled. Note that Power-On and Hard reset invalidate the caches, 393 * but Soft reset does not. 394 * 395 * HID1 has only read-only information - nothing to set. 396 */ 397 398#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI) 399#define CONFIG_SYS_HID0_FINAL 0 400#define CONFIG_SYS_HID2 0 401 402/*----------------------------------------------------------------------- 403 * RMR - Reset Mode Register 5-5 404 *----------------------------------------------------------------------- 405 * turn on Checkstop Reset Enable 406 */ 407#define CONFIG_SYS_RMR 0 408 409/*----------------------------------------------------------------------- 410 * BCR - Bus Configuration 4-25 411 *----------------------------------------------------------------------- 412 */ 413#define CONFIG_SYS_BCR 0 414 415/*----------------------------------------------------------------------- 416 * SIUMCR - SIU Module Configuration 4-31 417 *----------------------------------------------------------------------- 418 */ 419#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01) 420 421/*----------------------------------------------------------------------- 422 * SYPCR - System Protection Control 4-35 423 * SYPCR can only be written once after reset! 424 *----------------------------------------------------------------------- 425 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable 426 */ 427#if defined(CONFIG_WATCHDOG) 428#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 429 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) 430#else 431#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 432 SYPCR_SWRI|SYPCR_SWP) 433#endif /* CONFIG_WATCHDOG */ 434 435/*----------------------------------------------------------------------- 436 * TMCNTSC - Time Counter Status and Control 4-40 437 *----------------------------------------------------------------------- 438 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 439 * and enable Time Counter 440 */ 441#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 442 443/*----------------------------------------------------------------------- 444 * PISCR - Periodic Interrupt Status and Control 4-42 445 *----------------------------------------------------------------------- 446 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 447 * Periodic timer 448 */ 449#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 450 451/*----------------------------------------------------------------------- 452 * SCCR - System Clock Control 9-8 453 *----------------------------------------------------------------------- 454 * Ensure DFBRG is Divide by 16 455 */ 456#define CONFIG_SYS_SCCR (0x00000028 | SCCR_DFBRG01) 457 458/*----------------------------------------------------------------------- 459 * RCCR - RISC Controller Configuration 13-7 460 *----------------------------------------------------------------------- 461 */ 462#define CONFIG_SYS_RCCR 0 463 464/* 465 * Init Memory Controller: 466 * 467 * Bank Bus Machine PortSz Device 468 * ---- --- ------- ------ ------ 469 * 0 60x GPCM 16 bit FLASH 470 * 1 60x GPCM 8 bit NAND 471 * 2 60x SDRAM 32 bit SDRAM 472 * 3 60x GPCM 8 bit UART 473 * 474 */ 475 476#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ 477 478/* Minimum mask to separate preliminary 479 * address ranges for CS[0:2] 480 */ 481#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (32<<20) /* less than 32 MB */ 482 483#define CONFIG_SYS_MPTPR 0x6600 484 485/*----------------------------------------------------------------------------- 486 * Address for Mode Register Set (MRS) command 487 *----------------------------------------------------------------------------- 488 */ 489#define CONFIG_SYS_MRS_OFFS 0x00000110 490 491 492/* Bank 0 - FLASH 493 */ 494#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ 495 BRx_PS_8 |\ 496 BRx_MS_GPCM_P |\ 497 BRx_V) 498 499#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ 500 ORxG_SCY_6_CLK ) 501 502#if defined(CONFIG_CMD_NAND) 503/* Bank 1 - NAND Flash 504*/ 505#define CONFIG_SYS_NAND_BASE CONFIG_SYS_NAND0_BASE 506#define CONFIG_SYS_NAND_SIZE 0x8000 507 508#define CONFIG_SYS_OR_TIMING_NAND 0x000036 509 510#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) 511#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND ) 512#endif 513 514/* Bank 2 - 60x bus SDRAM 515 */ 516#define CONFIG_SYS_PSRT 0x20 517#define CONFIG_SYS_LSRT 0x20 518 519#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ 520 BRx_PS_32 |\ 521 BRx_MS_SDRAM_P |\ 522 BRx_V) 523 524#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2 525 526 527/* SDRAM initialization values 528*/ 529#define CONFIG_SYS_OR2 ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\ 530 ORxS_BPD_4 |\ 531 ORxS_ROWST_PBI0_A9 |\ 532 ORxS_NUMR_12) 533 534#define CONFIG_SYS_PSDMR (PSDMR_SDAM_A14_IS_A5 |\ 535 PSDMR_BSMA_A15_A17 |\ 536 PSDMR_SDA10_PBI0_A10 |\ 537 PSDMR_RFRC_5_CLK |\ 538 PSDMR_PRETOACT_2W |\ 539 PSDMR_ACTTORW_2W |\ 540 PSDMR_BL |\ 541 PSDMR_LDOTOPRE_2C |\ 542 PSDMR_WRC_3C |\ 543 PSDMR_CL_3) 544 545/* Bank 3 - UART 546*/ 547 548#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V ) 549#define CONFIG_SYS_OR3_PRELIM (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX ) 550 551#endif /* __CONFIG_H */ 552