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26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30
31#define CONFIG_BOOKE 1
32#define CONFIG_E500 1
33#define CONFIG_MPC85xx 1
34#define CONFIG_MPC8544 1
35#define CONFIG_MPC8544DS 1
36
37#define CONFIG_PCI 1
38#define CONFIG_PCI1 1
39#define CONFIG_PCIE1 1
40#define CONFIG_PCIE2 1
41#define CONFIG_PCIE3 1
42#define CONFIG_FSL_PCI_INIT 1
43#define CONFIG_FSL_PCIE_RESET 1
44#define CONFIG_SYS_PCI_64BIT 1
45
46#define CONFIG_FSL_LAW 1
47
48#define CONFIG_TSEC_ENET
49#define CONFIG_ENV_OVERWRITE
50#define CONFIG_INTERRUPTS
51
52
53
54
55
56
57#define CONFIG_ASSUME_AMD_FLASH
58
59#ifndef __ASSEMBLY__
60extern unsigned long get_board_sys_clk(unsigned long dummy);
61#endif
62#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
63
64
65
66
67#define CONFIG_L2_CACHE
68#define CONFIG_BTB
69
70
71
72
73#define CONFIG_ENABLE_36BIT_PHYS 1
74
75#define CONFIG_SYS_MEMTEST_START 0x00200000
76#define CONFIG_SYS_MEMTEST_END 0x00400000
77#define CONFIG_PANIC_HANG
78
79
80
81
82
83#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
84#define CONFIG_SYS_CCSRBAR 0xe0000000
85#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
86#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
87
88#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000)
89#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000)
90#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000)
91#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0xb000)
92
93
94#define CONFIG_FSL_DDR2
95#undef CONFIG_FSL_DDR_INTERACTIVE
96#define CONFIG_SPD_EEPROM
97#define CONFIG_DDR_SPD
98
99#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
100#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
101
102#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
103#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
104#define CONFIG_VERY_BIG_RAM
105
106#define CONFIG_NUM_DDR_CONTROLLERS 1
107#define CONFIG_DIMM_SLOTS_PER_CTLR 1
108#define CONFIG_CHIP_SELECTS_PER_CTRL 2
109
110
111#define SPD_EEPROM_ADDRESS 0x51
112
113
114#ifndef CONFIG_SPD_EEPROM
115#error ("CONFIG_SPD_EEPROM is required")
116#endif
117
118#undef CONFIG_CLOCKS_IN_MHZ
119
120
121
122
123
124
125
126
127
128
129
130
131
132
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135
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142
143
144
145
146
147
148#define CONFIG_SYS_BOOT_BLOCK 0xfc000000
149
150#define CONFIG_SYS_FLASH_BASE 0xff800000
151
152#define CONFIG_SYS_BR0_PRELIM 0xff801001
153#define CONFIG_SYS_BR1_PRELIM 0xfe801001
154
155#define CONFIG_SYS_OR0_PRELIM 0xff806e65
156#define CONFIG_SYS_OR1_PRELIM 0xff806e65
157
158#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
159
160#define CONFIG_SYS_FLASH_QUIET_TEST
161#define CONFIG_SYS_MAX_FLASH_BANKS 1
162#define CONFIG_SYS_MAX_FLASH_SECT 128
163#undef CONFIG_SYS_FLASH_CHECKSUM
164#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
165#define CONFIG_SYS_FLASH_WRITE_TOUT 500
166#define CONFIG_FLASH_SHOW_PROGRESS 45
167
168#define CONFIG_SYS_MONITOR_BASE TEXT_BASE
169
170#define CONFIG_FLASH_CFI_DRIVER
171#define CONFIG_SYS_FLASH_CFI
172#define CONFIG_SYS_FLASH_EMPTY_INFO
173
174#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
175
176#define CONFIG_SYS_BR2_PRELIM 0xf8201001
177#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7
178
179#define CONFIG_SYS_BR3_PRELIM 0xf8100801
180#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7
181
182#define CONFIG_FSL_PIXIS 1
183#define PIXIS_BASE 0xf8100000
184#define PIXIS_ID 0x0
185#define PIXIS_VER 0x1
186#define PIXIS_PVER 0x2
187#define PIXIS_RST 0x4
188#define PIXIS_AUX 0x6
189
190#define PIXIS_SPD 0x7
191#define PIXIS_VCTL 0x10
192#define PIXIS_VCFGEN0 0x12
193#define PIXIS_VCFGEN1 0x13
194#define PIXIS_VBOOT 0x16
195#define PIXIS_VSPEED0 0x17
196#define PIXIS_VSPEED1 0x18
197#define PIXIS_VCLKH 0x19
198#define PIXIS_VCLKL 0x1A
199#define PIXIS_VSPEED2 0x1d
200#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40
201#define PIXIS_VSPEED2_TSEC1SER 0x2
202#define PIXIS_VSPEED2_TSEC3SER 0x1
203#define PIXIS_VCFGEN1_TSEC1SER 0x20
204#define PIXIS_VCFGEN1_TSEC3SER 0x40
205#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
206#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
207
208
209#define CONFIG_SYS_INIT_RAM_LOCK 1
210#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000
211#define CONFIG_SYS_INIT_RAM_END 0x00004000
212
213
214#define CONFIG_SYS_GBL_DATA_SIZE 128
215#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
216#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
217
218#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
219#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
220
221
222
223
224
225#define CONFIG_CONS_INDEX 1
226#undef CONFIG_SERIAL_SOFTWARE_FIFO
227#define CONFIG_SYS_NS16550
228#define CONFIG_SYS_NS16550_SERIAL
229#define CONFIG_SYS_NS16550_REG_SIZE 1
230#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
231
232#define CONFIG_SYS_BAUDRATE_TABLE \
233 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
234
235#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
236#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
237
238
239#define CONFIG_SYS_HUSH_PARSER
240#ifdef CONFIG_SYS_HUSH_PARSER
241#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
242#endif
243
244
245#define CONFIG_OF_LIBFDT 1
246#define CONFIG_OF_BOARD_SETUP 1
247#define CONFIG_OF_STDOUT_VIA_ALIAS 1
248
249#define CONFIG_SYS_64BIT_STRTOUL 1
250#define CONFIG_SYS_64BIT_VSPRINTF 1
251
252
253#define CONFIG_FSL_I2C
254#define CONFIG_HARD_I2C
255#undef CONFIG_SOFT_I2C
256#define CONFIG_SYS_I2C_SPEED 400000
257#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
258#define CONFIG_SYS_I2C_SLAVE 0x7F
259#define CONFIG_SYS_I2C_NOPROBES {0x69}
260#define CONFIG_SYS_I2C_OFFSET 0x3100
261
262
263
264
265
266#define CONFIG_SYS_PCIE_VIRT 0x80000000
267#define CONFIG_SYS_PCIE_PHYS 0x80000000
268#define CONFIG_SYS_PCI_VIRT 0xc0000000
269#define CONFIG_SYS_PCI_PHYS 0xc0000000
270
271#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
272#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
273#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
274#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000
275#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
276#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
277#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
278#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000
279
280
281#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
282#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
283#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
284#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000
285#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
286#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
287#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
288#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000
289
290
291#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
292#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
293#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
294#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
295#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
296#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
297#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
298#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000
299
300
301#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
302#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
303#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
304#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000
305#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000
306#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
307#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000
308#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000
309#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
310#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
311#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
312#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000
313
314#if defined(CONFIG_PCI)
315
316
317#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
318
319
320
321
322
323#define CONFIG_VIDEO
324
325#if defined(CONFIG_VIDEO)
326#define CONFIG_BIOSEMU
327#define CONFIG_CFB_CONSOLE
328#define CONFIG_VIDEO_SW_CURSOR
329#define CONFIG_VGA_AS_SINGLE_DEVICE
330#define CONFIG_ATI_RADEON_FB
331#define CONFIG_VIDEO_LOGO
332
333#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
334#endif
335
336#define CONFIG_NET_MULTI
337#define CONFIG_PCI_PNP
338
339#undef CONFIG_EEPRO100
340#undef CONFIG_TULIP
341#define CONFIG_RTL8139
342
343#ifdef CONFIG_RTL8139
344
345#define KSEG1ADDR(x) (x)
346#define _IO_BASE 0x00000000
347#endif
348
349#ifndef CONFIG_PCI_PNP
350 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
351 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
352 #define PCI_IDSEL_NUMBER 0x11
353#endif
354
355#define CONFIG_PCI_SCAN_SHOW
356#define CONFIG_DOS_PARTITION
357#define CONFIG_SCSI_AHCI
358
359#ifdef CONFIG_SCSI_AHCI
360#define CONFIG_SATA_ULI5288
361#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
362#define CONFIG_SYS_SCSI_MAX_LUN 1
363#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
364#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
365#endif
366
367#endif
368
369
370#if defined(CONFIG_TSEC_ENET)
371
372#ifndef CONFIG_NET_MULTI
373#define CONFIG_NET_MULTI 1
374#endif
375
376#define CONFIG_MII 1
377#define CONFIG_MII_DEFAULT_TSEC 1
378#define CONFIG_TSEC1 1
379#define CONFIG_TSEC1_NAME "eTSEC1"
380#define CONFIG_TSEC3 1
381#define CONFIG_TSEC3_NAME "eTSEC3"
382
383#define CONFIG_PIXIS_SGMII_CMD
384#define CONFIG_FSL_SGMII_RISER 1
385#define SGMII_RISER_PHY_OFFSET 0x1c
386
387#define TSEC1_PHY_ADDR 0
388#define TSEC3_PHY_ADDR 1
389
390#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
391#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
392
393#define TSEC1_PHYIDX 0
394#define TSEC3_PHYIDX 0
395
396#define CONFIG_ETHPRIME "eTSEC1"
397
398#define CONFIG_PHY_GIGE 1
399#endif
400
401
402
403
404#define CONFIG_ENV_IS_IN_FLASH 1
405#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
406#define CONFIG_ENV_ADDR 0xfff80000
407#else
408#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000)
409#endif
410#define CONFIG_ENV_SIZE 0x2000
411#define CONFIG_ENV_SECT_SIZE 0x10000
412
413#define CONFIG_LOADS_ECHO 1
414#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
415
416
417
418
419#define CONFIG_BOOTP_BOOTFILESIZE
420#define CONFIG_BOOTP_BOOTPATH
421#define CONFIG_BOOTP_GATEWAY
422#define CONFIG_BOOTP_HOSTNAME
423
424
425
426
427
428#include <config_cmd_default.h>
429
430#define CONFIG_CMD_PING
431#define CONFIG_CMD_I2C
432#define CONFIG_CMD_MII
433#define CONFIG_CMD_ELF
434#define CONFIG_CMD_IRQ
435#define CONFIG_CMD_SETEXPR
436
437#if defined(CONFIG_PCI)
438 #define CONFIG_CMD_PCI
439 #define CONFIG_CMD_BEDBUG
440 #define CONFIG_CMD_NET
441 #define CONFIG_CMD_SCSI
442 #define CONFIG_CMD_EXT2
443#endif
444
445
446#undef CONFIG_WATCHDOG
447
448
449
450
451#define CONFIG_SYS_LONGHELP
452#define CONFIG_CMDLINE_EDITING
453#define CONFIG_SYS_LOAD_ADDR 0x2000000
454#define CONFIG_SYS_PROMPT "=> "
455#if defined(CONFIG_CMD_KGDB)
456#define CONFIG_SYS_CBSIZE 1024
457#else
458#define CONFIG_SYS_CBSIZE 256
459#endif
460#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
461#define CONFIG_SYS_MAXARGS 16
462#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
463#define CONFIG_SYS_HZ 1000
464
465
466
467
468
469
470#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
471
472
473
474
475
476
477#define BOOTFLAG_COLD 0x01
478#define BOOTFLAG_WARM 0x02
479
480#if defined(CONFIG_CMD_KGDB)
481#define CONFIG_KGDB_BAUDRATE 230400
482#define CONFIG_KGDB_SER_INDEX 2
483#endif
484
485
486
487
488
489
490#if defined(CONFIG_TSEC_ENET)
491#define CONFIG_HAS_ETH0
492#define CONFIG_ETHADDR 00:E0:0C:02:00:FD
493#define CONFIG_HAS_ETH1
494#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD
495#endif
496
497#define CONFIG_IPADDR 192.168.1.251
498
499#define CONFIG_HOSTNAME 8544ds_unknown
500#define CONFIG_ROOTPATH /nfs/mpc85xx
501#define CONFIG_BOOTFILE 8544ds/uImage.uboot
502#define CONFIG_UBOOTPATH 8544ds/u-boot.bin
503
504#define CONFIG_SERVERIP 192.168.1.1
505#define CONFIG_GATEWAYIP 192.168.1.1
506#define CONFIG_NETMASK 255.255.0.0
507
508#define CONFIG_LOADADDR 1000000
509
510#define CONFIG_BOOTDELAY 10
511#undef CONFIG_BOOTARGS
512
513#define CONFIG_BAUDRATE 115200
514
515#define CONFIG_EXTRA_ENV_SETTINGS \
516 "netdev=eth0\0" \
517 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
518 "tftpflash=tftpboot $loadaddr $uboot; " \
519 "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
520 "erase " MK_STR(TEXT_BASE) " +$filesize; " \
521 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
522 "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
523 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
524 "consoledev=ttyS0\0" \
525 "ramdiskaddr=2000000\0" \
526 "ramdiskfile=8544ds/ramdisk.uboot\0" \
527 "fdtaddr=c00000\0" \
528 "fdtfile=8544ds/mpc8544ds.dtb\0" \
529 "bdev=sda3\0"
530
531#define CONFIG_NFSBOOTCOMMAND \
532 "setenv bootargs root=/dev/nfs rw " \
533 "nfsroot=$serverip:$rootpath " \
534 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
535 "console=$consoledev,$baudrate $othbootargs;" \
536 "tftp $loadaddr $bootfile;" \
537 "tftp $fdtaddr $fdtfile;" \
538 "bootm $loadaddr - $fdtaddr"
539
540#define CONFIG_RAMBOOTCOMMAND \
541 "setenv bootargs root=/dev/ram rw " \
542 "console=$consoledev,$baudrate $othbootargs;" \
543 "tftp $ramdiskaddr $ramdiskfile;" \
544 "tftp $loadaddr $bootfile;" \
545 "tftp $fdtaddr $fdtfile;" \
546 "bootm $loadaddr $ramdiskaddr $fdtaddr"
547
548#define CONFIG_BOOTCOMMAND \
549 "setenv bootargs root=/dev/$bdev rw " \
550 "console=$consoledev,$baudrate $othbootargs;" \
551 "tftp $loadaddr $bootfile;" \
552 "tftp $fdtaddr $fdtfile;" \
553 "bootm $loadaddr - $fdtaddr"
554
555#endif
556