1/* 2 * (C) Copyright 2001 3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35 36#define CONFIG_405GP 1 /* This is a PPC405 CPU */ 37#define CONFIG_4xx 1 /* ...member of PPC4xx family */ 38#define CONFIG_ORSG 1 /* ...on a ORSG board */ 39 40#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ 41 42#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ 43 44#define CONFIG_BAUDRATE 9600 45#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 46 47#undef CONFIG_BOOTARGS 48#define CONFIG_BOOTCOMMAND "go fff00100" 49 50#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 51#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 52 53#define CONFIG_PPC4xx_EMAC 54#define CONFIG_MII 1 /* MII PHY management */ 55#define CONFIG_PHY_ADDR 0 /* PHY address */ 56#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ 57 58 59/* 60 * BOOTP options 61 */ 62#define CONFIG_BOOTP_BOOTFILESIZE 63#define CONFIG_BOOTP_BOOTPATH 64#define CONFIG_BOOTP_GATEWAY 65#define CONFIG_BOOTP_HOSTNAME 66 67 68/* 69 * Command line configuration. 70 */ 71#include <config_cmd_default.h> 72 73#define CONFIG_CMD_PCI 74#define CONFIG_CMD_IRQ 75#define CONFIG_CMD_ASKENV 76#define CONFIG_CMD_ELF 77#define CONFIG_CMD_BSP 78#define CONFIG_CMD_EEPROM 79 80 81#define CONFIG_MAC_PARTITION 82#define CONFIG_DOS_PARTITION 83 84#undef CONFIG_WATCHDOG /* watchdog disabled */ 85 86#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ 87 88/* 89 * Miscellaneous configurable options 90 */ 91#define CONFIG_SYS_LONGHELP /* undef to save memory */ 92#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 93#if defined(CONFIG_CMD_KGDB) 94#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 95#else 96#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 97#endif 98#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 99#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 100#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 101 102#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/ 103 104#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 105#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 106 107#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ 108#define CONFIG_SYS_BASE_BAUD 691200 109 110/* The following table includes the supported baudrates */ 111#define CONFIG_SYS_BAUDRATE_TABLE \ 112 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 113 57600, 115200, 230400, 460800, 921600 } 114 115#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 116#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ 117 118#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 119 120#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ 121 122/*----------------------------------------------------------------------- 123 * PCI stuff 124 *----------------------------------------------------------------------- 125 */ 126#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ 127#define PCI_HOST_FORCE 1 /* configure as pci host */ 128#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 129 130#define CONFIG_PCI /* include pci support */ 131#define CONFIG_PCI_HOST PCI_HOST_ADAPTER /* select pci adapter */ 132#undef CONFIG_PCI_PNP /* no pci plug-and-play */ 133 /* resource configuration */ 134 135#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ 136 137#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ 138#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0411 /* PCI Device ID: ORSG */ 139#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ 140#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ 141#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ 142#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ 143#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ 144#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ 145#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ 146 147/*----------------------------------------------------------------------- 148 * Start addresses for the final memory configuration 149 * (Set up by the startup code) 150 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 151 */ 152#define CONFIG_SYS_SDRAM_BASE 0x00000000 153#define CONFIG_SYS_FLASH_BASE 0xFFFD0000 154#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 155#define CONFIG_SYS_MONITOR_LEN (192 * 1024) /* Reserve 192 kB for Monitor */ 156#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ 157 158/* 159 * For booting Linux, the board info and command line data 160 * have to be in the first 8 MB of memory, since this is 161 * the maximum mapped by the Linux kernel during initialization. 162 */ 163#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 164/*----------------------------------------------------------------------- 165 * FLASH organization 166 */ 167#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 168#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 169 170#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 171#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 172 173#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */ 174#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ 175#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ 176/* 177 * The following defines are added for buggy IOP480 byte interface. 178 * All other boards should use the standard values (CPCI405 etc.) 179 */ 180#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ 181#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ 182#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ 183 184#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 185 186#if 0 /* Use NVRAM for environment variables */ 187/*----------------------------------------------------------------------- 188 * NVRAM organization 189 */ 190#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */ 191#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000 /* NVRAM base address */ 192#define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */ 193#define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */ 194#define CONFIG_ENV_ADDR \ 195 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env */ 196#define CONFIG_SYS_NVRAM_VXWORKS_OFFS 0x6900 /* Offset for VxWorks eth-addr */ 197 198#else /* Use EEPROM for environment variables */ 199 200#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 201#define CONFIG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ 202#define CONFIG_ENV_SIZE 0x300 /* 768 bytes may be used for env vars */ 203 /* total size of a CAT24WC08 is 1024 bytes */ 204#endif 205 206/*----------------------------------------------------------------------- 207 * I2C EEPROM (CAT24WC08) for environment 208 */ 209#define CONFIG_HARD_I2C /* I2c with hardware support */ 210#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 211#define CONFIG_SYS_I2C_SLAVE 0x7F 212 213#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ 214#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ 215/* mask of address bits that overflow into the "EEPROM chip address" */ 216#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07 217#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */ 218 /* 16 byte page write mode using*/ 219 /* last 4 bits of the address */ 220#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 221 222/* 223 * Init Memory Controller: 224 * 225 * BR0/1 and OR0/1 (FLASH) 226 */ 227 228#define FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank #0 */ 229#define FLASH_BASE1_PRELIM 0xFFC00000 /* FLASH bank #1 */ 230 231/*----------------------------------------------------------------------- 232 * External Bus Controller (EBC) Setup 233 */ 234 235/* Memory Bank 0 (Flash Bank 0) initialization */ 236#define CONFIG_SYS_EBC_PB0AP 0x92015480 237#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */ 238 239/* Memory Bank 1 (Flash Bank 1) initialization */ 240#define CONFIG_SYS_EBC_PB1AP 0x92015480 241#define CONFIG_SYS_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */ 242 243/* Memory Bank 2 (PLD - FPGA-boot) initialization */ 244#define CONFIG_SYS_EBC_PB2AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ 245 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ 246#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */ 247 248/* Memory Bank 3 (PLD - OSL) initialization */ 249#define CONFIG_SYS_EBC_PB3AP 0x02015480 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ 250 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x0,SOR=0x1,BEM=0x0,PEN=0x0*/ 251#define CONFIG_SYS_EBC_PB3CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */ 252 253/* Memory Bank 4 (Spartan2 1) initialization */ 254#define CONFIG_SYS_EBC_PB4AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ 255 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ 256#define CONFIG_SYS_EBC_PB4CR 0xF209C000 /* BAS=0xF20,BS=16MB,BU=R/W,BW=32bit*/ 257 258/* Memory Bank 5 (Spartan2 2) initialization */ 259#define CONFIG_SYS_EBC_PB5AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ 260 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ 261#define CONFIG_SYS_EBC_PB5CR 0xF309C000 /* BAS=0xF30,BS=16MB,BU=R/W,BW=32bit*/ 262 263/* Memory Bank 6 (Virtex 1) initialization */ 264#define CONFIG_SYS_EBC_PB6AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ 265 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ 266#define CONFIG_SYS_EBC_PB6CR 0xF409A000 /* BAS=0xF40,BS=16MB,BU=R/W,BW=16bit*/ 267 268/* Memory Bank 7 (Virtex 2) initialization */ 269#define CONFIG_SYS_EBC_PB7AP 0x02015580 /* BME=0x0,TWT=0x04,CSN=0x0,OEN=0x1 */ 270 /* WBN=0x1,WBF=0x1,TH=0x2,RE=0x1,SOR=0x1,BEM=0x0,PEN=0x0*/ 271#define CONFIG_SYS_EBC_PB7CR 0xF509A000 /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/ 272 273 274#define CONFIG_SYS_VXWORKS_MAC_PTR 0x00000000 /* Pass Ethernet MAC to VxWorks */ 275 276/*----------------------------------------------------------------------- 277 * Definitions for initial stack pointer and data area (in DPRAM) 278 */ 279 280/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ 281#define CONFIG_SYS_TEMP_STACK_OCM 1 282 283/* On Chip Memory location */ 284#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 285#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 286 287#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ 288#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */ 289#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 290#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 291#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 292 293 294/* 295 * Internal Definitions 296 * 297 * Boot Flags 298 */ 299#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 300#define BOOTFLAG_WARM 0x02 /* Software reboot */ 301 302#endif /* __CONFIG_H */ 303