1/* 2 * (C) Copyright 2001-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24/* 25 * board/config.h - configuration options, board specific 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31#undef CONFIG_SYS_RAMBOOT 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37 38#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */ 39#define CONFIG_PM828 1 /* ...on a PM828 module */ 40#define CONFIG_CPM2 1 /* Has a CPM2 */ 41 42#undef CONFIG_DB_CR826_J30x_ON /* J30x jumpers on D.B. carrier */ 43 44#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 45 46#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 47 48#undef CONFIG_BOOTARGS 49#define CONFIG_BOOTCOMMAND \ 50 "bootp;" \ 51 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 52 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ 53 "bootm" 54 55/* enable I2C and select the hardware/software driver */ 56#undef CONFIG_HARD_I2C 57#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ 58# define CONFIG_SYS_I2C_SPEED 50000 59# define CONFIG_SYS_I2C_SLAVE 0xFE 60/* 61 * Software (bit-bang) I2C driver configuration 62 */ 63#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */ 64#define I2C_ACTIVE (iop->pdir |= 0x00010000) 65#define I2C_TRISTATE (iop->pdir &= ~0x00010000) 66#define I2C_READ ((iop->pdat & 0x00010000) != 0) 67#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \ 68 else iop->pdat &= ~0x00010000 69#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \ 70 else iop->pdat &= ~0x00020000 71#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ 72 73 74#define CONFIG_RTC_PCF8563 75#define CONFIG_SYS_I2C_RTC_ADDR 0x51 76 77/* 78 * select serial console configuration 79 * 80 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 81 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 82 * for SCC). 83 * 84 * if CONFIG_CONS_NONE is defined, then the serial console routines must 85 * defined elsewhere (for example, on the cogent platform, there are serial 86 * ports on the motherboard which are used for the serial console - see 87 * cogent/cma101/serial.[ch]). 88 */ 89#define CONFIG_CONS_ON_SMC /* define if console on SMC */ 90#undef CONFIG_CONS_ON_SCC /* define if console on SCC */ 91#undef CONFIG_CONS_NONE /* define if console on something else*/ 92#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ 93 94/* 95 * select ethernet configuration 96 * 97 * if CONFIG_ETHER_ON_SCC is selected, then 98 * - CONFIG_ETHER_INDEX must be set to the channel number (1-4) 99 * - CONFIG_NET_MULTI must not be defined 100 * 101 * if CONFIG_ETHER_ON_FCC is selected, then 102 * - one or more CONFIG_ETHER_ON_FCCx (x=1,2,3) must also be selected 103 * - CONFIG_NET_MULTI must be defined 104 * 105 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be 106 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. 107 */ 108#define CONFIG_NET_MULTI 109#undef CONFIG_ETHER_NONE /* define if ether on something else */ 110 111#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ 112#define CONFIG_ETHER_INDEX 1 /* which SCC channel for ethernet */ 113 114#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ 115/* 116 * - Rx-CLK is CLK11 117 * - Tx-CLK is CLK10 118 */ 119#define CONFIG_ETHER_ON_FCC1 120# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK) 121#ifndef CONFIG_DB_CR826_J30x_ON 122# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK10) 123#else 124# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12) 125#endif 126/* 127 * - Rx-CLK is CLK15 128 * - Tx-CLK is CLK14 129 */ 130#define CONFIG_ETHER_ON_FCC2 131# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK) 132# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14) 133/* 134 * - RAM for BD/Buffers is on the 60x Bus (see 28-13) 135 * - Enable Full Duplex in FSMR 136 */ 137# define CONFIG_SYS_CPMFCR_RAMTYPE 0 138# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) 139 140/* system clock rate (CLKIN) - equal to the 60x and local bus speed */ 141#define CONFIG_8260_CLKIN 100000000 /* in Hz */ 142 143#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC) 144#define CONFIG_BAUDRATE 230400 145#else 146#define CONFIG_BAUDRATE 9600 147#endif 148 149#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 150#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 151 152#undef CONFIG_WATCHDOG /* watchdog disabled */ 153 154/* 155 * BOOTP options 156 */ 157#define CONFIG_BOOTP_SUBNETMASK 158#define CONFIG_BOOTP_GATEWAY 159#define CONFIG_BOOTP_HOSTNAME 160#define CONFIG_BOOTP_BOOTPATH 161#define CONFIG_BOOTP_BOOTFILESIZE 162 163 164/* 165 * Command line configuration. 166 */ 167#include <config_cmd_default.h> 168 169#define CONFIG_CMD_BEDBUG 170#define CONFIG_CMD_DATE 171#define CONFIG_CMD_DHCP 172#define CONFIG_CMD_DOC 173#define CONFIG_CMD_EEPROM 174#define CONFIG_CMD_I2C 175#define CONFIG_CMD_NFS 176#define CONFIG_CMD_SNTP 177 178#ifdef CONFIG_PCI 179#define CONFIG_CMD_PCI 180#endif 181 182 183/* 184 * Disk-On-Chip configuration 185 */ 186#define CONFIG_NAND_LEGACY 187 188#define CONFIG_SYS_DOC_SHORT_TIMEOUT 189#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ 190 191#define CONFIG_SYS_DOC_SUPPORT_2000 192#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM 193 194/* 195 * Miscellaneous configurable options 196 */ 197#define CONFIG_SYS_LONGHELP /* undef to save memory */ 198#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 199#if defined(CONFIG_CMD_KGDB) 200#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 201#else 202#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 203#endif 204#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 205#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 206#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 207 208#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 209#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 210 211#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 212 213#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 214 215#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 216 217#define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ 218 219/* 220 * For booting Linux, the board info and command line data 221 * have to be in the first 8 MB of memory, since this is 222 * the maximum mapped by the Linux kernel during initialization. 223 */ 224#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 225 226/*----------------------------------------------------------------------- 227 * Flash and Boot ROM mapping 228 */ 229 230#define CONFIG_SYS_BOOTROM_BASE 0xFF800000 231#define CONFIG_SYS_BOOTROM_SIZE 0x00080000 232#define CONFIG_SYS_FLASH0_BASE 0x40000000 233#define CONFIG_SYS_FLASH0_SIZE 0x02000000 234#define CONFIG_SYS_DOC_BASE 0xFF800000 235#define CONFIG_SYS_DOC_SIZE 0x00100000 236 237 238/* Flash bank size (for preliminary settings) 239 */ 240#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE 241 242/*----------------------------------------------------------------------- 243 * FLASH organization 244 */ 245#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ 246#define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */ 247 248#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ 249#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 250 251#if 0 252/* Start port with environment in flash; switch to EEPROM later */ 253#define CONFIG_ENV_IS_IN_FLASH 1 254#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x40000) 255#define CONFIG_ENV_SIZE 0x40000 256#define CONFIG_ENV_SECT_SIZE 0x40000 257#else 258/* Final version: environment in EEPROM */ 259#define CONFIG_ENV_IS_IN_EEPROM 1 260#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 261#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 262#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 263#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 264#define CONFIG_ENV_OFFSET 512 265#define CONFIG_ENV_SIZE (2048 - 512) 266#endif 267 268/*----------------------------------------------------------------------- 269 * Hard Reset Configuration Words 270 * 271 * if you change bits in the HRCW, you must also change the CONFIG_SYS_* 272 * defines for the various registers affected by the HRCW e.g. changing 273 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR. 274 */ 275#if defined(CONFIG_BOOT_ROM) 276#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS01 | HRCW_CIP | HRCW_ISB100 | HRCW_BMS) 277#else 278#define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS) 279#endif 280 281/* no slaves so just fill with zeros */ 282#define CONFIG_SYS_HRCW_SLAVE1 0 283#define CONFIG_SYS_HRCW_SLAVE2 0 284#define CONFIG_SYS_HRCW_SLAVE3 0 285#define CONFIG_SYS_HRCW_SLAVE4 0 286#define CONFIG_SYS_HRCW_SLAVE5 0 287#define CONFIG_SYS_HRCW_SLAVE6 0 288#define CONFIG_SYS_HRCW_SLAVE7 0 289 290/*----------------------------------------------------------------------- 291 * Internal Memory Mapped Register 292 */ 293#define CONFIG_SYS_IMMR 0xF0000000 294 295/*----------------------------------------------------------------------- 296 * Definitions for initial stack pointer and data area (in DPRAM) 297 */ 298#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 299#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ 300#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/ 301#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 302#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 303 304/*----------------------------------------------------------------------- 305 * Start addresses for the final memory configuration 306 * (Set up by the startup code) 307 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 308 * 309 * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE, local SDRAM 310 * is mapped at SDRAM_BASE2_PRELIM. 311 */ 312#define CONFIG_SYS_SDRAM_BASE 0x00000000 313#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE 314#define CONFIG_SYS_MONITOR_BASE TEXT_BASE 315#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 316#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/ 317 318#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 319# define CONFIG_SYS_RAMBOOT 320#endif 321 322#ifdef CONFIG_PCI 323#define CONFIG_PCI_PNP 324#define CONFIG_EEPRO100 325#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 326#endif 327 328/* 329 * Internal Definitions 330 * 331 * Boot Flags 332 */ 333#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/ 334#define BOOTFLAG_WARM 0x02 /* Software reboot */ 335 336 337/*----------------------------------------------------------------------- 338 * Cache Configuration 339 */ 340#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */ 341#if defined(CONFIG_CMD_KGDB) 342# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 343#endif 344 345/*----------------------------------------------------------------------- 346 * HIDx - Hardware Implementation-dependent Registers 2-11 347 *----------------------------------------------------------------------- 348 * HID0 also contains cache control - initially enable both caches and 349 * invalidate contents, then the final state leaves only the instruction 350 * cache enabled. Note that Power-On and Hard reset invalidate the caches, 351 * but Soft reset does not. 352 * 353 * HID1 has only read-only information - nothing to set. 354 */ 355#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\ 356 HID0_IFEM|HID0_ABE) 357#define CONFIG_SYS_HID0_FINAL (HID0_ICE|HID0_IFEM|HID0_ABE) 358#define CONFIG_SYS_HID2 0 359 360/*----------------------------------------------------------------------- 361 * RMR - Reset Mode Register 5-5 362 *----------------------------------------------------------------------- 363 * turn on Checkstop Reset Enable 364 */ 365#define CONFIG_SYS_RMR RMR_CSRE 366 367/*----------------------------------------------------------------------- 368 * BCR - Bus Configuration 4-25 369 *----------------------------------------------------------------------- 370 */ 371 372#define BCR_APD01 0x10000000 373#define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */ 374 375/*----------------------------------------------------------------------- 376 * SIUMCR - SIU Module Configuration 4-31 377 *----------------------------------------------------------------------- 378 */ 379#if 0 380#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_CS10PC01) 381#else 382#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC10|SIUMCR_APPC10) 383#endif 384 385 386/*----------------------------------------------------------------------- 387 * SYPCR - System Protection Control 4-35 388 * SYPCR can only be written once after reset! 389 *----------------------------------------------------------------------- 390 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable 391 */ 392#if defined(CONFIG_WATCHDOG) 393#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 394 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) 395#else 396#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ 397 SYPCR_SWRI|SYPCR_SWP) 398#endif /* CONFIG_WATCHDOG */ 399 400/*----------------------------------------------------------------------- 401 * TMCNTSC - Time Counter Status and Control 4-40 402 *----------------------------------------------------------------------- 403 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, 404 * and enable Time Counter 405 */ 406#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) 407 408/*----------------------------------------------------------------------- 409 * PISCR - Periodic Interrupt Status and Control 4-42 410 *----------------------------------------------------------------------- 411 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable 412 * Periodic timer 413 */ 414#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) 415 416/*----------------------------------------------------------------------- 417 * SCCR - System Clock Control 9-8 418 *----------------------------------------------------------------------- 419 */ 420#define CONFIG_SYS_SCCR (SCCR_DFBRG00) 421 422/*----------------------------------------------------------------------- 423 * RCCR - RISC Controller Configuration 13-7 424 *----------------------------------------------------------------------- 425 */ 426#define CONFIG_SYS_RCCR 0 427 428/* 429 * Init Memory Controller: 430 * 431 * Bank Bus Machine PortSz Device 432 * ---- --- ------- ------ ------ 433 * 0 60x GPCM 64 bit FLASH 434 * 1 60x SDRAM 64 bit SDRAM 435 * 436 */ 437 438 /* Initialize SDRAM on local bus 439 */ 440#define CONFIG_SYS_INIT_LOCAL_SDRAM 441 442 443/* Minimum mask to separate preliminary 444 * address ranges for CS[0:2] 445 */ 446#define CONFIG_SYS_MIN_AM_MASK 0xC0000000 447 448/* 449 * we use the same values for 32 MB and 128 MB SDRAM 450 * refresh rate = 7.68 uS (100 MHz Bus Clock) 451 */ 452#define CONFIG_SYS_MPTPR 0x2000 453#define CONFIG_SYS_PSRT 0x16 454 455#define CONFIG_SYS_MRS_OFFS 0x00000000 456 457 458#if defined(CONFIG_BOOT_ROM) 459/* 460 * Bank 0 - Boot ROM (8 bit wide) 461 */ 462#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\ 463 BRx_PS_8 |\ 464 BRx_MS_GPCM_P |\ 465 BRx_V) 466 467#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\ 468 ORxG_CSNT |\ 469 ORxG_ACS_DIV1 |\ 470 ORxG_SCY_5_CLK |\ 471 ORxG_EHTR |\ 472 ORxG_TRLX) 473 474/* 475 * Bank 1 - Flash (64 bit wide) 476 */ 477#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ 478 BRx_PS_64 |\ 479 BRx_MS_GPCM_P |\ 480 BRx_V) 481 482#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ 483 ORxG_CSNT |\ 484 ORxG_ACS_DIV1 |\ 485 ORxG_SCY_5_CLK |\ 486 ORxG_EHTR |\ 487 ORxG_TRLX) 488 489#else /* ! CONFIG_BOOT_ROM */ 490 491/* 492 * Bank 0 - Flash (64 bit wide) 493 */ 494#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\ 495 BRx_PS_64 |\ 496 BRx_MS_GPCM_P |\ 497 BRx_V) 498 499#define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\ 500 ORxG_CSNT |\ 501 ORxG_ACS_DIV1 |\ 502 ORxG_SCY_5_CLK |\ 503 ORxG_EHTR |\ 504 ORxG_TRLX) 505 506/* 507 * Bank 1 - Disk-On-Chip 508 */ 509#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\ 510 BRx_PS_8 |\ 511 BRx_MS_GPCM_P |\ 512 BRx_V) 513 514#define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\ 515 ORxG_CSNT |\ 516 ORxG_ACS_DIV1 |\ 517 ORxG_SCY_5_CLK |\ 518 ORxG_EHTR |\ 519 ORxG_TRLX) 520 521#endif /* CONFIG_BOOT_ROM */ 522 523/* Bank 2 - SDRAM 524 */ 525 526#ifndef CONFIG_SYS_RAMBOOT 527#define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\ 528 BRx_PS_64 |\ 529 BRx_MS_SDRAM_P |\ 530 BRx_V) 531 532 /* SDRAM initialization values for 8-column chips 533 */ 534#define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\ 535 ORxS_BPD_4 |\ 536 ORxS_ROWST_PBI0_A9 |\ 537 ORxS_NUMR_12) 538 539#define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\ 540 PSDMR_BSMA_A14_A16 |\ 541 PSDMR_SDA10_PBI0_A10 |\ 542 PSDMR_RFRC_7_CLK |\ 543 PSDMR_PRETOACT_2W |\ 544 PSDMR_ACTTORW_2W |\ 545 PSDMR_LDOTOPRE_1C |\ 546 PSDMR_WRC_1C |\ 547 PSDMR_CL_2) 548 549 /* SDRAM initialization values for 9-column chips 550 */ 551#define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\ 552 ORxS_BPD_4 |\ 553 ORxS_ROWST_PBI0_A7 |\ 554 ORxS_NUMR_13) 555 556#define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\ 557 PSDMR_BSMA_A13_A15 |\ 558 PSDMR_SDA10_PBI0_A9 |\ 559 PSDMR_RFRC_7_CLK |\ 560 PSDMR_PRETOACT_2W |\ 561 PSDMR_ACTTORW_2W |\ 562 PSDMR_LDOTOPRE_1C |\ 563 PSDMR_WRC_1C |\ 564 PSDMR_CL_2) 565 566#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_9COL 567#define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_9COL 568 569#endif /* CONFIG_SYS_RAMBOOT */ 570 571#endif /* __CONFIG_H */ 572