LXR uboot/include/configs/omap2420h4.h

   1/*
   2 * (C) Copyright 2004
   3 * Texas Instruments.
   4 * Richard Woodruff <r-woodruff2@ti.com>
   5 * Kshitij Gupta <kshitij@ti.com>
   6 *
   7 * Configuration settings for the 242x TI H4 board.
   8 *
   9 * See file CREDITS for list of people who contributed to this
  10 * project.
  11 *
  12 * This program is free software; you can redistribute it and/or
  13 * modify it under the terms of the GNU General Public License as
  14 * published by the Free Software Foundation; either version 2 of
  15 * the License, or (at your option) any later version.
  16 *
  17 * This program is distributed in the hope that it will be useful,
  18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 * GNU General Public License for more details.
  21 *
  22 * You should have received a copy of the GNU General Public License
  23 * along with this program; if not, write to the Free Software
  24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25 * MA 02111-1307 USA
  26 */
  27
  28#ifndef __CONFIG_H
  29#define __CONFIG_H
  30
  31/*
  32 * High Level Configuration Options
  33 */
  34#define CONFIG_ARM1136           1    /* This is an arm1136 CPU core */
  35#define CONFIG_OMAP              1    /* in a TI OMAP core */
  36#define CONFIG_OMAP2420          1    /* which is in a 2420 */
  37#define CONFIG_OMAP2420H4        1    /* and on a H4 board */
  38/*#define CONFIG_APTIX           1    #* define if on APTIX test chip */
  39/*#define CONFIG_VIRTIO          1    #* Using Virtio simulator */
  40
  41/* Clock config to target*/
  42#define PRCM_CONFIG_II  1
  43/* #define PRCM_CONFIG_III              1 */
  44
  45#include <asm/arch/omap2420.h>        /* get chip and board defs */
  46
  47/* On H4, NOR and NAND flash are mutual exclusive.
  48   Define this if you want to use NAND
  49 */
  50/*#define CONFIG_SYS_NAND_BOOT */
  51
  52#ifdef CONFIG_APTIX
  53#define V_SCLK                   1500000
  54#else
  55#define V_SCLK                   12000000
  56#endif
  57
  58/* input clock of PLL */
  59/* the OMAP2420 H4 has 12MHz, 13MHz, or 19.2Mhz crystal input */
  60#define CONFIG_SYS_CLK_FREQ      V_SCLK
  61
  62#undef CONFIG_USE_IRQ                 /* no support for IRQs */
  63#define CONFIG_MISC_INIT_R
  64
  65#define CONFIG_CMDLINE_TAG       1    /* enable passing of ATAGs */
  66#define CONFIG_SETUP_MEMORY_TAGS 1
  67#define CONFIG_INITRD_TAG        1
  68#define CONFIG_REVISION_TAG      1
  69
  70/*
  71 * Size of malloc() pool
  72 */
  73#define CONFIG_ENV_SIZE             SZ_128K     /* Total Size of Environment Sector */
  74#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + SZ_128K)
  75#define CONFIG_SYS_GBL_DATA_SIZE        128  /* size in bytes reserved for initial data */
  76
  77/*
  78 * Hardware drivers
  79 */
  80
  81/*
  82 * SMC91c96 Etherent
  83 */
  84#define CONFIG_DRIVER_LAN91C96
  85#define CONFIG_LAN91C96_BASE     (H4_CS1_BASE+0x300)
  86#define CONFIG_LAN91C96_EXT_PHY
  87
  88/*
  89 * NS16550 Configuration
  90 */
  91#ifdef CONFIG_APTIX
  92#define V_NS16550_CLK            (6000000)   /* 6MHz in current MaxSet */
  93#else
  94#define V_NS16550_CLK            (48000000)  /* 48MHz (APLL96/2) */
  95#endif
  96
  97#define CONFIG_SYS_NS16550
  98#define CONFIG_SYS_NS16550_SERIAL
  99#define CONFIG_SYS_NS16550_REG_SIZE     (-4)
 100#define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK   /* 3MHz (1.5MHz*2) */
 101#define CONFIG_SYS_NS16550_COM1         OMAP2420_UART1
 102
 103/*
 104 * select serial console configuration
 105 */
 106#define CONFIG_SERIAL1           1    /* UART1 on H4 */
 107
 108  /*
 109   * I2C configuration
 110   */
 111#define CONFIG_HARD_I2C
 112#define CONFIG_SYS_I2C_SPEED          100000
 113#define CONFIG_SYS_I2C_SLAVE          1
 114#define CONFIG_DRIVER_OMAP24XX_I2C
 115
 116/* allow to overwrite serial and ethaddr */
 117#define CONFIG_ENV_OVERWRITE
 118#define CONFIG_CONS_INDEX        1
 119#define CONFIG_BAUDRATE          115200
 120#define CONFIG_SYS_BAUDRATE_TABLE       {9600, 19200, 38400, 57600, 115200}
 121
 122
 123/*
 124 * Command line configuration.
 125 */
 126#include <config_cmd_default.h>
 127
 128#ifdef CONFIG_SYS_NAND_BOOT
 129    #define CONFIG_CMD_DHCP
 130    #define CONFIG_CMD_I2C
 131    #define CONFIG_CMD_NAND
 132    #define CONFIG_CMD_JFFS2
 133#else
 134    #define CONFIG_CMD_DHCP
 135    #define CONFIG_CMD_I2C
 136    #define CONFIG_CMD_JFFS2
 137
 138    #undef CONFIG_CMD_AUTOSCRIPT
 139#endif
 140
 141
 142/*
 143 * BOOTP options
 144 */
 145#define CONFIG_BOOTP_SUBNETMASK
 146#define CONFIG_BOOTP_GATEWAY
 147#define CONFIG_BOOTP_HOSTNAME
 148#define CONFIG_BOOTP_BOOTPATH
 149
 150
 151/*
 152 *  Board NAND Info.
 153 */
 154#define CONFIG_NAND_LEGACY
 155#define CONFIG_SYS_NAND_ADDR 0x04000000  /* physical address to access nand at CS0*/
 156
 157#define CONFIG_SYS_MAX_NAND_DEVICE 1    /* Max number of NAND devices */
 158#define SECTORSIZE          512
 159
 160#define ADDR_COLUMN         1
 161#define ADDR_PAGE           2
 162#define ADDR_COLUMN_PAGE    3
 163
 164#define NAND_ChipID_UNKNOWN 0x00
 165#define NAND_MAX_FLOORS     1
 166
 167#define WRITE_NAND_COMMAND(d, adr) do {*(volatile u16 *)0x6800A07C = d;} while(0)
 168#define WRITE_NAND_ADDRESS(d, adr) do {*(volatile u16 *)0x6800A080 = d;} while(0)
 169#define WRITE_NAND(d, adr) do {*(volatile u16 *)0x6800A084 = d;} while(0)
 170#define READ_NAND(adr) (*(volatile u16 *)0x6800A084)
 171#define NAND_WAIT_READY(nand)  udelay(10)
 172
 173#define NAND_NO_RB          1
 174
 175#define CONFIG_SYS_NAND_WP
 176#define NAND_WP_OFF()  do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0)
 177#define NAND_WP_ON()  do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0)
 178
 179#define NAND_CTL_CLRALE(nandptr)
 180#define NAND_CTL_SETALE(nandptr)
 181#define NAND_CTL_CLRCLE(nandptr)
 182#define NAND_CTL_SETCLE(nandptr)
 183#define NAND_DISABLE_CE(nand)
 184#define NAND_ENABLE_CE(nand)
 185
 186#define CONFIG_BOOTDELAY         3
 187
 188#ifdef NFS_BOOT_DEFAULTS
 189#define CONFIG_BOOTARGS          "mem=32M console=ttyS0,115200n8 noinitrd root=/dev/nfs rw nfsroot=128.247.77.158:/home/a0384864/wtbu/rootfs ip=dhcp"
 190#else
 191#define CONFIG_BOOTARGS          "root=/dev/ram0 rw mem=32M console=ttyS0,115200n8 initrd=0x80600000,8M ramdisk_size=8192"
 192#endif
 193
 194#define CONFIG_NETMASK           255.255.254.0
 195#define CONFIG_IPADDR            128.247.77.90
 196#define CONFIG_SERVERIP          128.247.77.158
 197#define CONFIG_BOOTFILE          "uImage"
 198
 199/*
 200 * Miscellaneous configurable options
 201 */
 202#ifdef CONFIG_APTIX
 203#define V_PROMPT                 "OMAP2420 Aptix # "
 204#else
 205#define V_PROMPT                 "OMAP242x H4 # "
 206#endif
 207
 208#define CONFIG_SYS_LONGHELP             /* undef to save memory */
 209#define CONFIG_SYS_PROMPT               V_PROMPT
 210#define CONFIG_SYS_CBSIZE               256  /* Console I/O Buffer Size */
 211/* Print Buffer Size */
 212#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 213#define CONFIG_SYS_MAXARGS              16          /* max number of command args */
 214#define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE  /* Boot Argument Buffer Size */
 215
 216#define CONFIG_SYS_MEMTEST_START        (OMAP2420_SDRC_CS0)  /* memtest works on */
 217#define CONFIG_SYS_MEMTEST_END          (OMAP2420_SDRC_CS0+SZ_31M)
 218
 219#undef  CONFIG_SYS_CLKS_IN_HZ           /* everything, incl board info, in Hz */
 220
 221#define CONFIG_SYS_LOAD_ADDR            (OMAP2420_SDRC_CS0) /* default load address */
 222
 223/* The 2420 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
 224 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
 225 */
 226#ifdef CONFIG_APTIX
 227#define V_PVT                    3
 228#else
 229#define V_PVT                    7  /* use with 12MHz/128 */
 230#endif
 231
 232#define CONFIG_SYS_TIMERBASE            OMAP2420_GPT2
 233#define CONFIG_SYS_PVT                  V_PVT  /* 2^(pvt+1) */
 234#define CONFIG_SYS_HZ                    ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PVT))
 235
 236/*-----------------------------------------------------------------------
 237 * Stack sizes
 238 *
 239 * The stack sizes are set up in start.S using the settings below
 240 */
 241#define CONFIG_STACKSIZE         SZ_128K /* regular stack */
 242#ifdef CONFIG_USE_IRQ
 243#define CONFIG_STACKSIZE_IRQ     SZ_4K   /* IRQ stack */
 244#define CONFIG_STACKSIZE_FIQ     SZ_4K   /* FIQ stack */
 245#endif
 246
 247/*-----------------------------------------------------------------------
 248 * Physical Memory Map
 249 */
 250#define CONFIG_NR_DRAM_BANKS     2                 /* CS1 may or may not be populated */
 251#define PHYS_SDRAM_1             OMAP2420_SDRC_CS0
 252#define PHYS_SDRAM_1_SIZE        SZ_32M            /* at least 32 meg */
 253#define PHYS_SDRAM_2             OMAP2420_SDRC_CS1
 254
 255#define PHYS_FLASH_SECT_SIZE     SZ_128K
 256#define PHYS_FLASH_1             H4_CS0_BASE       /* Flash Bank #1 */
 257#define PHYS_FLASH_SIZE_1        SZ_32M
 258#define PHYS_FLASH_2             (H4_CS0_BASE+SZ_32M) /* same cs, 2 chips in series */
 259#define PHYS_FLASH_SIZE_2        SZ_32M
 260
 261/*-----------------------------------------------------------------------
 262 * FLASH and environment organization
 263 */
 264#define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 265#define CONFIG_SYS_MAX_FLASH_BANKS      2           /* max number of memory banks */
 266#define CONFIG_SYS_MAX_FLASH_SECT       (259)        /* max number of sectors on one chip */
 267#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */
 268#define CONFIG_SYS_MONITOR_LEN          SZ_128K      /* Reserve 1 sector */
 269#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + PHYS_FLASH_SIZE_1 }
 270
 271#ifdef CONFIG_SYS_NAND_BOOT
 272#define CONFIG_ENV_IS_IN_NAND   1
 273#define CONFIG_ENV_OFFSET       0x80000 /* environment starts here  */
 274#else
 275#define CONFIG_ENV_ADDR             (CONFIG_SYS_FLASH_BASE + SZ_128K)
 276#define CONFIG_ENV_IS_IN_FLASH      1
 277#define CONFIG_ENV_SECT_SIZE    PHYS_FLASH_SECT_SIZE
 278#define CONFIG_ENV_OFFSET       ( CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN ) /* Environment after Monitor */
 279#endif
 280
 281/*-----------------------------------------------------------------------
 282 * CFI FLASH driver setup
 283 */
 284#define CONFIG_SYS_FLASH_CFI            1       /* Flash memory is CFI compliant */
 285#define CONFIG_FLASH_CFI_DRIVER 1       /* Use drivers/mtd/cfi_flash.c */
 286#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* Use buffered writes (~10x faster) */
 287#define CONFIG_SYS_FLASH_PROTECTION     1       /* Use hardware sector protection */
 288
 289/* timeout values are in ticks */
 290#define CONFIG_SYS_FLASH_ERASE_TOUT     (100*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 291#define CONFIG_SYS_FLASH_WRITE_TOUT     (100*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 292
 293#define CONFIG_SYS_JFFS2_MEM_NAND
 294
 295/*
 296 * JFFS2 partitions
 297 */
 298/* No command line, one static partition, whole device */
 299#undef CONFIG_JFFS2_CMDLINE
 300#define CONFIG_JFFS2_DEV                "nor1"
 301#define CONFIG_JFFS2_PART_SIZE          0xFFFFFFFF
 302#define CONFIG_JFFS2_PART_OFFSET        0x00000000
 303
 304/* mtdparts command line support */
 305/* Note: fake mtd_id used, no linux mtd map file */
 306/*
 307#define CONFIG_JFFS2_CMDLINE
 308#define MTDIDS_DEFAULT          "nor1=omap2420-1"
 309#define MTDPARTS_DEFAULT        "mtdparts=omap2420-1:-(jffs2)"
 310*/
 311
 312#endif                                                  /* __CONFIG_H */
 313