LXR uboot/include/configs/omap3

   1/*
   2 * (C) Copyright 2006-2008
   3 * Texas Instruments.
   4 * Richard Woodruff <r-woodruff2@ti.com>
   5 * Syed Mohammed Khasim <x0khasim@ti.com>
   6 * Nishanth Menon <nm@ti.com>
   7 *
   8 * Configuration settings for the TI OMAP3430 Zoom MDK board.
   9 *
  10 * See file CREDITS for list of people who contributed to this
  11 * project.
  12 *
  13 * This program is free software; you can redistribute it and/or
  14 * modify it under the terms of the GNU General Public License as
  15 * published by the Free Software Foundation; either version 2 of
  16 * the License, or (at your option) any later version.
  17 *
  18 * This program is distributed in the hope that it will be useful,
  19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21 * GNU General Public License for more details.
  22 *
  23 * You should have received a copy of the GNU General Public License
  24 * along with this program; if not, write to the Free Software
  25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26 * MA 02111-1307 USA
  27 */
  28
  29#ifndef __CONFIG_H
  30#define __CONFIG_H
  31#include <asm/sizes.h>
  32
  33/*
  34 * High Level Configuration Options
  35 */
  36#define CONFIG_ARMCORTEXA8      1       /* This is an ARM V7 CPU core */
  37#define CONFIG_OMAP             1       /* in a TI OMAP core */
  38#define CONFIG_OMAP34XX         1       /* which is a 34XX */
  39#define CONFIG_OMAP3430         1       /* which is in a 3430 */
  40#define CONFIG_OMAP3_ZOOM1      1       /* working with Zoom MDK Rev1 */
  41
  42#include <asm/arch/cpu.h>               /* get chip and board defs */
  43#include <asm/arch/omap3.h>
  44
  45/* Clock Defines */
  46#define V_OSCK                  26000000        /* Clock output from T2 */
  47#define V_SCLK                  (V_OSCK >> 1)
  48
  49#undef CONFIG_USE_IRQ                           /* no support for IRQs */
  50#define CONFIG_MISC_INIT_R
  51
  52#define CONFIG_CMDLINE_TAG              1       /* enable passing of ATAGs */
  53#define CONFIG_SETUP_MEMORY_TAGS        1
  54#define CONFIG_INITRD_TAG               1
  55#define CONFIG_REVISION_TAG             1
  56
  57/*
  58 * Size of malloc() pool
  59 */
  60#define CONFIG_ENV_SIZE                 SZ_128K /* Total Size Environment */
  61                                                /* Sector */
  62#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + SZ_128K)
  63#define CONFIG_SYS_GBL_DATA_SIZE        128     /* bytes reserved for */
  64                                                /* initial data */
  65
  66/*
  67 * Hardware drivers
  68 */
  69
  70/*
  71 * NS16550 Configuration
  72 */
  73#define V_NS16550_CLK                   48000000        /* 48MHz (APLL96/2) */
  74
  75#define CONFIG_SYS_NS16550
  76#define CONFIG_SYS_NS16550_SERIAL
  77#define CONFIG_SYS_NS16550_REG_SIZE     (-4)
  78#define CONFIG_SYS_NS16550_CLK          V_NS16550_CLK
  79
  80/*
  81 * select serial console configuration
  82 */
  83#define CONFIG_CONS_INDEX               3
  84#define CONFIG_SYS_NS16550_COM3         OMAP34XX_UART3
  85#define CONFIG_SERIAL3                  3       /* UART3 */
  86
  87/* allow to overwrite serial and ethaddr */
  88#define CONFIG_ENV_OVERWRITE
  89#define CONFIG_BAUDRATE                 115200
  90#define CONFIG_SYS_BAUDRATE_TABLE       {4800, 9600, 19200, 38400, 57600,\
  91                                        115200}
  92#define CONFIG_MMC                      1
  93#define CONFIG_OMAP3_MMC                1
  94#define CONFIG_DOS_PARTITION            1
  95
  96/* commands to include */
  97#include <config_cmd_default.h>
  98
  99#define CONFIG_CMD_EXT2         /* EXT2 Support                 */
 100#define CONFIG_CMD_FAT          /* FAT support                  */
 101#define CONFIG_CMD_JFFS2        /* JFFS2 Support                */
 102
 103#define CONFIG_CMD_I2C          /* I2C serial bus support       */
 104#define CONFIG_CMD_MMC          /* MMC support                  */
 105#define CONFIG_CMD_NAND         /* NAND support                 */
 106#define CONFIG_CMD_NAND_LOCK_UNLOCK /* Enable lock/unlock support */
 107
 108#undef CONFIG_CMD_FLASH         /* flinfo, erase, protect       */
 109#undef CONFIG_CMD_FPGA          /* FPGA configuration Support   */
 110#undef CONFIG_CMD_IMI           /* iminfo                       */
 111#undef CONFIG_CMD_IMLS          /* List all found images        */
 112#undef CONFIG_CMD_NET           /* bootp, tftpboot, rarpboot    */
 113#undef CONFIG_CMD_NFS           /* NFS support                  */
 114
 115#define CONFIG_SYS_NO_FLASH
 116#define CONFIG_SYS_I2C_SPEED            100000
 117#define CONFIG_SYS_I2C_SLAVE            1
 118#define CONFIG_SYS_I2C_BUS              0
 119#define CONFIG_SYS_I2C_BUS_SELECT       1
 120#define CONFIG_DRIVER_OMAP34XX_I2C      1
 121
 122/*
 123 * Board NAND Info.
 124 */
 125#define CONFIG_NAND_OMAP_GPMC
 126#define CONFIG_SYS_NAND_ADDR            NAND_BASE       /* physical address */
 127                                                        /* to access nand */
 128#define CONFIG_SYS_NAND_BASE            NAND_BASE       /* physical address */
 129                                                        /* to access nand at */
 130                                                        /* CS0 */
 131#define GPMC_NAND_ECC_LP_x16_LAYOUT     1
 132
 133#define CONFIG_SYS_MAX_NAND_DEVICE      1               /* Max number of NAND */
 134                                                        /* devices */
 135#define SECTORSIZE                      512
 136
 137#define NAND_ALLOW_ERASE_ALL
 138#define ADDR_COLUMN                     1
 139#define ADDR_PAGE                       2
 140#define ADDR_COLUMN_PAGE                3
 141
 142#define NAND_ChipID_UNKNOWN             0x00
 143#define NAND_MAX_FLOORS                 1
 144#define NAND_MAX_CHIPS                  1
 145#define NAND_NO_RB                      1
 146#define CONFIG_SYS_NAND_WP
 147
 148#define CONFIG_JFFS2_NAND
 149/* nand device jffs2 lives on */
 150#define CONFIG_JFFS2_DEV                "nand0"
 151/* start of jffs2 partition */
 152#define CONFIG_JFFS2_PART_OFFSET        0x680000
 153#define CONFIG_JFFS2_PART_SIZE          0xf980000       /* size of jffs2 */
 154                                                        /* partition */
 155
 156/* Environment information */
 157#define CONFIG_BOOTDELAY                10
 158
 159#define CONFIG_EXTRA_ENV_SETTINGS \
 160        "loadaddr=0x82000000\0" \
 161        "console=ttyS2,115200n8\0" \
 162        "videomode=1024x768@60,vxres=1024,vyres=768\0" \
 163        "videospec=omapfb:vram:2M,vram:4M\0" \
 164        "mmcargs=setenv bootargs console=${console} " \
 165                "video=${videospec},mode:${videomode} " \
 166                "root=/dev/mmcblk0p2 rw " \
 167                "rootfstype=ext3 rootwait\0" \
 168        "nandargs=setenv bootargs console=${console} " \
 169                "video=${videospec},mode:${videomode} " \
 170                "root=/dev/mtdblock4 rw " \
 171                "rootfstype=jffs2\0" \
 172        "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
 173        "bootscript=echo Running bootscript from mmc ...; " \
 174                "autoscr ${loadaddr}\0" \
 175        "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
 176        "mmcboot=echo Booting from mmc ...; " \
 177                "run mmcargs; " \
 178                "bootm ${loadaddr}\0" \
 179        "nandboot=echo Booting from nand ...; " \
 180                "run nandargs; " \
 181                "nand read ${loadaddr} 280000 400000; " \
 182                "bootm ${loadaddr}\0" \
 183
 184#define CONFIG_BOOTCOMMAND \
 185        "if mmcinit; then " \
 186                "if run loadbootscript; then " \
 187                        "run bootscript; " \
 188                "else " \
 189                        "if run loaduimage; then " \
 190                                "run mmcboot; " \
 191                        "else run nandboot; " \
 192                        "fi; " \
 193                "fi; " \
 194        "else run nandboot; fi"
 195
 196#define CONFIG_AUTO_COMPLETE            1
 197/*
 198 * Miscellaneous configurable options
 199 */
 200#define V_PROMPT                        "OMAP3 Zoom1# "
 201
 202#define CONFIG_SYS_LONGHELP             /* undef to save memory */
 203#define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 204#define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 205#define CONFIG_SYS_PROMPT               V_PROMPT
 206#define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 207/* Print Buffer Size */
 208#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 209                                        sizeof(CONFIG_SYS_PROMPT) + 16)
 210#define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 211/* Boot Argument Buffer Size */
 212#define CONFIG_SYS_BARGSIZE             (CONFIG_SYS_CBSIZE)
 213
 214#define CONFIG_SYS_MEMTEST_START        (OMAP34XX_SDRC_CS0)     /* memtest */
 215                                                                /* works on */
 216#define CONFIG_SYS_MEMTEST_END          (OMAP34XX_SDRC_CS0 + \
 217                                        0x01F00000) /* 31MB */
 218
 219#undef  CONFIG_SYS_CLKS_IN_HZ           /* everything, incl board info, in Hz */
 220
 221#define CONFIG_SYS_LOAD_ADDR            (OMAP34XX_SDRC_CS0)     /* default */
 222                                                        /* load address */
 223
 224/*
 225 * 2430 has 12 GP timers, they can be driven by the SysClk (12/13/19.2) or by
 226 * 32KHz clk, or from external sig. This rate is divided by a local divisor.
 227 */
 228#define V_PVT                           7
 229
 230#define CONFIG_SYS_TIMERBASE            (OMAP34XX_GPT2)
 231#define CONFIG_SYS_PVT                  V_PVT   /* 2^(pvt+1) */
 232#define CONFIG_SYS_HZ                   ((V_SCLK) / (2 << CONFIG_SYS_PVT))
 233
 234/*-----------------------------------------------------------------------
 235 * Stack sizes
 236 *
 237 * The stack sizes are set up in start.S using the settings below
 238 */
 239#define CONFIG_STACKSIZE        SZ_128K /* regular stack */
 240#ifdef CONFIG_USE_IRQ
 241#define CONFIG_STACKSIZE_IRQ    SZ_4K   /* IRQ stack */
 242#define CONFIG_STACKSIZE_FIQ    SZ_4K   /* FIQ stack */
 243#endif
 244
 245/*-----------------------------------------------------------------------
 246 * Physical Memory Map
 247 */
 248#define CONFIG_NR_DRAM_BANKS    2       /* CS1 may or may not be populated */
 249#define PHYS_SDRAM_1            OMAP34XX_SDRC_CS0
 250#define PHYS_SDRAM_1_SIZE       SZ_32M  /* at least 32 meg */
 251#define PHYS_SDRAM_2            OMAP34XX_SDRC_CS1
 252
 253/* SDRAM Bank Allocation method */
 254#define SDRC_R_B_C              1
 255
 256/*-----------------------------------------------------------------------
 257 * FLASH and environment organization
 258 */
 259
 260/* **** PISMO SUPPORT *** */
 261
 262/* Configure the PISMO */
 263#define PISMO1_NAND_SIZE                GPMC_SIZE_128M
 264#define PISMO1_ONEN_SIZE                GPMC_SIZE_128M
 265
 266#define CONFIG_SYS_MAX_FLASH_SECT       520     /* max number of sectors on */
 267                                                /* one chip */
 268#define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of flash banks */
 269#define CONFIG_SYS_MONITOR_LEN          SZ_256K /* Reserve 2 sectors */
 270
 271#define CONFIG_SYS_FLASH_BASE           boot_flash_base
 272
 273/* Monitor at start of flash */
 274#define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_FLASH_BASE
 275#define CONFIG_SYS_ONENAND_BASE         ONENAND_MAP
 276
 277#define CONFIG_ENV_IS_IN_NAND           1
 278#define ONENAND_ENV_OFFSET              0x260000 /* environment starts here */
 279#define SMNAND_ENV_OFFSET               0x260000 /* environment starts here */
 280
 281#define CONFIG_SYS_ENV_SECT_SIZE        boot_flash_sec
 282#define CONFIG_ENV_OFFSET               boot_flash_off
 283#define CONFIG_ENV_ADDR                 SMNAND_ENV_OFFSET
 284
 285/*-----------------------------------------------------------------------
 286 * CFI FLASH driver setup
 287 */
 288/* timeout values are in ticks */
 289#define CONFIG_SYS_FLASH_ERASE_TOUT     (100 * CONFIG_SYS_HZ)
 290#define CONFIG_SYS_FLASH_WRITE_TOUT     (100 * CONFIG_SYS_HZ)
 291
 292/* Flash banks JFFS2 should use */
 293#define CONFIG_SYS_MAX_MTD_BANKS        (CONFIG_SYS_MAX_FLASH_BANKS + \
 294                                        CONFIG_SYS_MAX_NAND_DEVICE)
 295#define CONFIG_SYS_JFFS2_MEM_NAND
 296/* use flash_info[2] */
 297#define CONFIG_SYS_JFFS2_FIRST_BANK     CONFIG_SYS_MAX_FLASH_BANKS
 298#define CONFIG_SYS_JFFS2_NUM_BANKS      1
 299
 300#ifndef __ASSEMBLY__
 301extern gpmc_csx_t *nand_cs_base;
 302extern gpmc_t *gpmc_cfg_base;
 303extern unsigned int boot_flash_base;
 304extern volatile unsigned int boot_flash_env_addr;
 305extern unsigned int boot_flash_off;
 306extern unsigned int boot_flash_sec;
 307extern unsigned int boot_flash_type;
 308#endif
 309
 310
 311#define WRITE_NAND_COMMAND(d, adr)\
 312                        writel(d, &nand_cs_base->nand_cmd)
 313#define WRITE_NAND_ADDRESS(d, adr)\
 314                        writel(d, &nand_cs_base->nand_adr)
 315#define WRITE_NAND(d, adr) writew(d, &nand_cs_base->nand_dat)
 316#define READ_NAND(adr) readl(&nand_cs_base->nand_dat)
 317
 318/* Other NAND Access APIs */
 319#define NAND_WP_OFF() do {readl(&gpmc_cfg_base->config) |= GPMC_CONFIG_WP; } \
 320                        while (0)
 321#define NAND_WP_ON() do {readl(&gpmc_cfg_base->config) &= ~GPMC_CONFIG_WP; } \
 322                        while (0)
 323#define NAND_DISABLE_CE(nand)
 324#define NAND_ENABLE_CE(nand)
 325#define NAND_WAIT_READY(nand)   udelay(10)
 326
 327#endif                          /* __CONFIG_H */
 328