LXR uboot/include/configs/p3p440.h

   1/*
   2 * (C) Copyright 2005-2006
   3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4 *
   5 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
   6 *
   7 * See file CREDITS for list of people who contributed to this
   8 * project.
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License as
  12 * published by the Free Software Foundation; either version 2 of
  13 * the License, or (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * You should have received a copy of the GNU General Public License
  21 * along with this program; if not, write to the Free Software
  22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23 * MA 02111-1307 USA
  24 */
  25
  26/************************************************************************
  27 * board/config_p3p440.h - configuration for Prodrive P3P440
  28 ***********************************************************************/
  29
  30#ifndef __CONFIG_H
  31#define __CONFIG_H
  32
  33/*-----------------------------------------------------------------------
  34 * High Level Configuration Options
  35 *----------------------------------------------------------------------*/
  36#define CONFIG_P3P440           1           /* Board is P3P440          */
  37#define CONFIG_440GP            1           /* Specifc GP support       */
  38#define CONFIG_440              1           /* ... PPC440 family        */
  39#define CONFIG_4xx              1           /* ... PPC4xx family        */
  40#define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_early_init_f  */
  41#define CONFIG_MISC_INIT_R      1           /* Call misc_init_r         */
  42#define CONFIG_SYS_CLK_FREQ     33333333    /* external freq to pll     */
  43
  44/*-----------------------------------------------------------------------
  45 * Base addresses -- Note these are effective addresses where the
  46 * actual resources get mapped (not physical addresses)
  47 *----------------------------------------------------------------------*/
  48#define CONFIG_SYS_SDRAM_BASE       0x00000000      /* _must_ be 0              */
  49#define CONFIG_SYS_FLASH_BASE       0xff800000      /* start of FLASH           */
  50#define CONFIG_SYS_MONITOR_BASE    0xfffc0000       /* start of monitor         */
  51#define CONFIG_SYS_PCI_MEMBASE      0x80000000      /* mapped pci memory        */
  52#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000       /* internal peripherals     */
  53#define CONFIG_SYS_ISRAM_BASE       0xc0000000      /* internal SRAM            */
  54#define CONFIG_SYS_PCI_BASE         0xd0000000      /* internal PCI regs        */
  55
  56#define CONFIG_SYS_USB_BASE         (CONFIG_SYS_PERIPHERAL_BASE + 0x00000000)
  57
  58/*-----------------------------------------------------------------------
  59 * Initial RAM & stack pointer (placed in internal SRAM)
  60 *----------------------------------------------------------------------*/
  61#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_ISRAM_BASE  /* Initial RAM address   */
  62#define CONFIG_SYS_INIT_RAM_END 0x2000      /* End of used area in RAM  */
  63#define CONFIG_SYS_GBL_DATA_SIZE        128         /* num bytes initial data   */
  64
  65#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  66#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  67
  68#define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Mon*/
  69#define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc*/
  70
  71/*-----------------------------------------------------------------------
  72 * DDR SDRAM
  73 *----------------------------------------------------------------------*/
  74#define CONFIG_SDRAM_BANK0      1       /* init onboard DDR SDRAM bank 0*/
  75#define CONFIG_SDRAM_ECC                /* enable ECC support           */
  76#define CONFIG_SYS_SDRAM_TABLE  { \
  77                {(256 << 20), 13, 0x000C4001}, /* 256MB mode 3, 13x10(4)*/ \
  78                {(64 << 20),  12, 0x00082001}} /* 64MB mode 2, 12x9(4)  */
  79
  80/*-----------------------------------------------------------------------
  81 * Serial Port
  82 *----------------------------------------------------------------------*/
  83#undef CONFIG_SYS_EXT_SERIAL_CLOCK
  84#define CONFIG_BAUDRATE         115200
  85
  86#define CONFIG_SYS_BAUDRATE_TABLE                                               \
  87        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,               \
  88                        57600, 115200, 230400, 460800, 921600 }
  89
  90/*-----------------------------------------------------------------------
  91 * I2C
  92 *----------------------------------------------------------------------*/
  93#define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
  94#undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
  95#define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address  */
  96#define CONFIG_SYS_I2C_SLAVE            0x7F
  97#define CONFIG_SYS_I2C_NOPROBES {0x69}  /* Don't probe these addrs      */
  98
  99/*-----------------------------------------------------------------------
 100 * I2C RTC
 101 *----------------------------------------------------------------------*/
 102#define CONFIG_RTC_MAX6900      1               /* MAX6900 RTC          */
 103
 104/*-----------------------------------------------------------------------
 105 * I2C EEPROM (PCF8594C) for environment
 106 *----------------------------------------------------------------------*/
 107#define CONFIG_SYS_I2C_EEPROM_ADDR      0x54    /* EEPROM PCF8594C              */
 108#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 109/* mask of address bits that overflow into the "EEPROM chip address"    */
 110#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 111#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3     /* The Philips PCF8594C has     */
 112                                        /* 8 byte page write mode using */
 113                                        /* last 3 bits of the address   */
 114#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   40   /* and takes up to 40 msec */
 115
 116/*-----------------------------------------------------------------------
 117 * Default configuration (environment varibles...)
 118 *----------------------------------------------------------------------*/
 119#define CONFIG_PREBOOT  "echo;" \
 120        "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 121        "echo"
 122
 123#undef  CONFIG_BOOTARGS
 124
 125#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 126        "netdev=eth0\0"                                                 \
 127        "hostname=p3p440\0"                                             \
 128        "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 129                "nfsroot=${serverip}:${rootpath}\0"                     \
 130        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 131        "addip=setenv bootargs ${bootargs} "                            \
 132                "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 133                ":${hostname}:${netdev}:off panic=1\0"                  \
 134        "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 135        "flash_nfs=run nfsargs addip addtty;"                           \
 136                "bootm ${kernel_addr}\0"                                \
 137        "flash_self=run ramargs addip addtty;"                          \
 138                "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 139        "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 140                "bootm\0"                                               \
 141        "rootpath=/opt/eldk/ppc_4xx\0"                                  \
 142        "bootfile=/tftpboot/p3p440/uImage\0"                            \
 143        "kernel_addr=ff800000\0"                                        \
 144        "ramdisk_addr=ff810000\0"                                       \
 145        "load=tftp 100000 /tftpboot/p3p440/u-boot.bin\0"                \
 146        "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;"   \
 147                "cp.b 100000 fffc0000 40000;"                           \
 148                "setenv filesize;saveenv\0"                             \
 149        "upd=run load update\0"                                         \
 150        "unlock=yes\0"                                                  \
 151        ""
 152#define CONFIG_BOOTCOMMAND      "run net_nfs"
 153
 154#define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 155
 156#define CONFIG_BAUDRATE         115200
 157
 158#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 159#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 160
 161#define CONFIG_PPC4xx_EMAC
 162#define CONFIG_MII              1       /* MII PHY management           */
 163#define CONFIG_PHY_ADDR         0x1c    /* PHY address                  */
 164#define CONFIG_HAS_ETH1
 165#define CONFIG_PHY1_ADDR        0x1d    /* EMAC1 PHY address            */
 166#define CONFIG_NET_MULTI        1
 167#define CONFIG_SYS_RX_ETH_BUFFER        32      /* Number of ethernet rx buffers & descriptors */
 168
 169#define CONFIG_NETCONSOLE               /* include NetConsole support   */
 170
 171
 172/*
 173 * BOOTP options
 174 */
 175#define CONFIG_BOOTP_BOOTFILESIZE
 176#define CONFIG_BOOTP_BOOTPATH
 177#define CONFIG_BOOTP_GATEWAY
 178#define CONFIG_BOOTP_HOSTNAME
 179
 180
 181/*
 182 * Command line configuration.
 183 */
 184#include <config_cmd_default.h>
 185
 186#define CONFIG_CMD_ASKENV
 187#define CONFIG_CMD_DATE
 188#define CONFIG_CMD_DHCP
 189#define CONFIG_CMD_DIAG
 190#define CONFIG_CMD_ELF
 191#define CONFIG_CMD_I2C
 192#define CONFIG_CMD_IRQ
 193#define CONFIG_CMD_MII
 194#define CONFIG_CMD_NET
 195#define CONFIG_CMD_NFS
 196#define CONFIG_CMD_PCI
 197#define CONFIG_CMD_PING
 198#define CONFIG_CMD_REGINFO
 199#define CONFIG_CMD_EEPROM
 200#define CONFIG_CMD_SNTP
 201
 202
 203#undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 204
 205/*-----------------------------------------------------------------------
 206 * Miscellaneous configurable options
 207 *----------------------------------------------------------------------*/
 208#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 209#define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 210#if defined(CONFIG_CMD_KGDB)
 211#define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 212#else
 213#define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 214#endif
 215#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 216#define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 217#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 218
 219#define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 220#define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 221
 222#define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 223#define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 224
 225#define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 226
 227#define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 228#define CONFIG_LOOPW            1       /* enable loopw command         */
 229#define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 230#define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 231
 232/*-----------------------------------------------------------------------
 233 * PCI stuff
 234 *----------------------------------------------------------------------*/
 235/* General PCI */
 236#define CONFIG_PCI                                  /* include pci support              */
 237#define CONFIG_PCI_PNP                          /* do pci plug-and-play         */
 238#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 239#define CONFIG_SYS_PCI_TARGBASE    0x80000000  /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 240
 241/* Board-specific PCI */
 242#define CONFIG_SYS_PCI_TARGET_INIT                  /* let board init pci target    */
 243
 244#define CONFIG_DISABLE_PISE_TEST        /* disable PISE test (PCIX only)*/
 245
 246#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC */
 247#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe  /* Whatever */
 248
 249/*-----------------------------------------------------------------------
 250 * External Bus Controller (EBC) Setup
 251 *----------------------------------------------------------------------*/
 252#define CONFIG_SYS_FLASH0               0xFF800000
 253#define CONFIG_SYS_FLASH1               0xFF000000
 254#define CONFIG_SYS_FLASH2               0xFE800000
 255#define CONFIG_SYS_FLASH3               0xFE000000
 256#define CONFIG_SYS_USB                  0xF0000000
 257
 258/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization                       */
 259#define CONFIG_SYS_EBC_PB0AP            0x03050200
 260#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH0 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
 261
 262/* Memory Bank 1 (Flash Bank 1, NOR-FLASH) initialization                       */
 263#define CONFIG_SYS_EBC_PB1AP            0x03050200
 264#define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_FLASH1 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
 265
 266/* Memory Bank 2 (Flash Bank 2, NOR-FLASH) initialization                       */
 267#define CONFIG_SYS_EBC_PB2AP            0x03050200
 268#define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_FLASH2 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
 269
 270/* Memory Bank 3 (Flash Bank 3, NOR-FLASH) initialization                       */
 271#define CONFIG_SYS_EBC_PB3AP            0x03050200
 272#define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_FLASH3 | 0x7A000) /* BAS=0xFF8,BS=8MB,BU=R/W,BW=16bit */
 273
 274/* Memory Bank 7 (USB controller) initialization                                */
 275#define CONFIG_SYS_EBC_PB7AP            0x02015000
 276#define CONFIG_SYS_EBC_PB7CR            (CONFIG_SYS_USB | 0xFE000) /* BAS=0xF00,BS=128MB,BU=R/W,BW=16bit*/
 277
 278/*-----------------------------------------------------------------------
 279 * FLASH related
 280 *----------------------------------------------------------------------*/
 281#define CONFIG_SYS_FLASH_CFI                            /* The flash is CFI compatible  */
 282#define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 283
 284#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH3, CONFIG_SYS_FLASH2, CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
 285
 286#define CONFIG_SYS_MAX_FLASH_BANKS      4       /* max number of memory banks           */
 287#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 288
 289#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 290#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 291
 292#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 293#define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection        */
 294
 295#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 296#define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash        */
 297
 298#define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
 299
 300#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector          */
 301#define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 302#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 303
 304/* Address and size of Redundant Environment Sector     */
 305#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 306#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 307
 308/*
 309 * For booting Linux, the board info and command line data
 310 * have to be in the first 8 MB of memory, since this is
 311 * the maximum mapped by the Linux kernel during initialization.
 312 */
 313#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 314
 315/*
 316 * Internal Definitions
 317 *
 318 * Boot Flags
 319 */
 320#define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 321#define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 322
 323#if defined(CONFIG_CMD_KGDB)
 324#define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 325#define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 326#endif
 327#endif  /* __CONFIG_H */
 328