1/* 2 * (C) Copyright 2002 3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 4 * 5 * (C) Copyright 2002 6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 7 * Marius Groeger <mgroeger@sysgo.de> 8 * 9 * Configuration settings for the PLEB 2 board. 10 * 11 * See file CREDITS for list of people who contributed to this 12 * project. 13 * 14 * This program is free software; you can redistribute it and/or 15 * modify it under the terms of the GNU General Public License as 16 * published by the Free Software Foundation; either version 2 of 17 * the License, or (at your option) any later version. 18 * 19 * This program is distributed in the hope that it will be useful, 20 * but WITHOUT ANY WARRANTY; without even the implied warranty of 21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 22 * GNU General Public License for more details. 23 * 24 * You should have received a copy of the GNU General Public License 25 * along with this program; if not, write to the Free Software 26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 27 * MA 02111-1307 USA 28 */ 29 30#ifndef __CONFIG_H 31#define __CONFIG_H 32 33/* 34 * High Level Configuration Options 35 * (easy to change) 36 */ 37#define CONFIG_PXA250 1 /* This is an PXA255 CPU */ 38#define CONFIG_PLEB2 1 /* on an PLEB2 Board */ 39#undef CONFIG_LCD 40#undef CONFIG_MMC 41#define BOARD_LATE_INIT 1 42 43#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 44 45/* 46 * Size of malloc() pool 47 */ 48#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 49#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 50 51/* 52 * Hardware drivers 53 */ 54 55/* None - PLEB 2 doesn't have any of this. 56 #define CONFIG_DRIVER_LAN91C96 57 #define CONFIG_LAN91C96_BASE 0x0C000000 */ 58 59/* 60 * select serial console configuration 61 */ 62#define CONFIG_FFUART 1 /* we use FFUART on PLEB 2 */ 63 64/* allow to overwrite serial and ethaddr */ 65#define CONFIG_ENV_OVERWRITE 66 67#define CONFIG_BAUDRATE 115200 68 69 70/* 71 * BOOTP options 72 */ 73#define CONFIG_BOOTP_BOOTFILESIZE 74#define CONFIG_BOOTP_BOOTPATH 75#define CONFIG_BOOTP_GATEWAY 76#define CONFIG_BOOTP_HOSTNAME 77 78 79/* 80 * Command line configuration. 81 */ 82#include <config_cmd_default.h> 83 84#undef CONFIG_CMD_NET 85 86 87#define CONFIG_BOOTDELAY 3 88#define CONFIG_ETHADDR 08:00:3e:26:0a:5b 89#define CONFIG_NETMASK 255.255.0.0 90#define CONFIG_IPADDR 192.168.0.21 91#define CONFIG_SERVERIP 192.168.0.250 92#define CONFIG_BOOTCOMMAND "bootm 40000" 93#define CONFIG_BOOTARGS "root=/dev/mtdblock2 prompt_ramdisk=0 load_ramdisk=1 console=ttyS0,115200" 94 95#define CONFIG_CMDLINE_TAG 96#define CONFIG_INITRD_TAG 97#define CONFIG_SETUP_MEMORY_TAGS 98 99#if defined(CONFIG_CMD_KGDB) 100#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 101#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 102#endif 103 104/* 105 * Miscellaneous configurable options 106 */ 107#define CONFIG_SYS_HUSH_PARSER 1 108#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 109 110#define CONFIG_SYS_LONGHELP /* undef to save memory */ 111#ifdef CONFIG_SYS_HUSH_PARSER 112#define CONFIG_SYS_PROMPT "$ " /* Monitor Command Prompt */ 113#else 114#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 115#endif 116#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 117#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 118#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 119#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 120#define CONFIG_SYS_DEVICE_NULLDEV 1 121 122#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 123#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 124 125#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ 126 127#define CONFIG_SYS_LOAD_ADDR 0xa2000000 /* default load address */ 128 129#define CONFIG_SYS_HZ 1000 130#define CONFIG_SYS_CPUSPEED 0x141 /* set core clock to 200/200/100 MHz */ 131 132 /* valid baudrates */ 133#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 134 135#ifdef CONFIG_MMC 136#define CONFIG_PXA_MMC 137#define CONFIG_CMD_MMC 138#endif 139 140/* 141 * Stack sizes 142 * 143 * The stack sizes are set up in start.S using the settings below 144 */ 145#define CONFIG_STACKSIZE (128*1024) /* regular stack */ 146#ifdef CONFIG_USE_IRQ 147#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ 148#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ 149#endif 150 151/* 152 * Physical Memory Map 153 */ 154#define CONFIG_NR_DRAM_BANKS 4 /* we have 2 banks of DRAM */ 155#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 156#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ 157#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ 158#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ 159#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ 160#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ 161#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ 162#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ 163 164#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 165#define PHYS_FLASH_2 0x04000000 /* Flash Bank #2 */ 166#define PHYS_FLASH_SIZE 0x00800000 /* 4 MB */ 167 168/* Not entirely sure about this - DS/CHC */ 169#define PHYS_FLASH_BANK_SIZE 0x02000000 /* 32 MB Banks */ 170#define PHYS_FLASH_SECT_SIZE 0x00010000 /* 64 KB sectors (x2) */ 171 172#define CONFIG_SYS_DRAM_BASE PHYS_SDRAM_1 173#define CONFIG_SYS_DRAM_SIZE PHYS_SDRAM_1_SIZE 174 175#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 176#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 177 178/* 179 * GPIO settings 180 */ 181#define CONFIG_SYS_GPSR0_VAL 0x00000000 /* Don't set anything */ 182#define CONFIG_SYS_GPSR1_VAL 0x00000080 183#define CONFIG_SYS_GPSR2_VAL 0x00000000 184 185#define CONFIG_SYS_GPCR0_VAL 0x00000000 /* Don't clear anything */ 186#define CONFIG_SYS_GPCR1_VAL 0x00000000 187#define CONFIG_SYS_GPCR2_VAL 0x00000000 188 189#define CONFIG_SYS_GPDR0_VAL 0x00000000 190#define CONFIG_SYS_GPDR1_VAL 0x000007C3 191#define CONFIG_SYS_GPDR2_VAL 0x00000000 192 193/* Edge detect registers (these are set by the kernel) */ 194#define CONFIG_SYS_GRER0_VAL 0x00000000 195#define CONFIG_SYS_GRER1_VAL 0x00000000 196#define CONFIG_SYS_GRER2_VAL 0x00000000 197#define CONFIG_SYS_GFER0_VAL 0x00000000 198#define CONFIG_SYS_GFER1_VAL 0x00000000 199#define CONFIG_SYS_GFER2_VAL 0x00000000 200 201#define CONFIG_SYS_GAFR0_L_VAL 0x00000000 202#define CONFIG_SYS_GAFR0_U_VAL 0x00000000 203#define CONFIG_SYS_GAFR1_L_VAL 0x00008010 /* Use FF UART Send and Receive */ 204#define CONFIG_SYS_GAFR1_U_VAL 0x00000000 205#define CONFIG_SYS_GAFR2_L_VAL 0x00000000 206#define CONFIG_SYS_GAFR2_U_VAL 0x00000000 207 208#define CONFIG_SYS_PSSR_VAL 0x20 209#define CONFIG_SYS_CCCR_VAL 0x00000141 /* 100 MHz memory, 200 MHz CPU */ 210#define CONFIG_SYS_CKEN_VAL 0x00000060 /* FFUART and STUART enabled */ 211#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */ 212 213/* 214 * Memory settings 215 */ 216#define CONFIG_SYS_MSC0_VAL 0x00007FF0 /* Not properly calculated - FIXME (DS) */ 217#define CONFIG_SYS_MSC1_VAL 0x00000000 218#define CONFIG_SYS_MSC2_VAL 0x00000000 219 220#define CONFIG_SYS_MDCNFG_VAL 0x00000aC9 /* Memory timings for the SDRAM. 221 tRP=2, CL=2, tRCD=2, tRAS=5, tRC=8 */ 222 223#define CONFIG_SYS_MDREFR_VAL 0x00403018 /* Initial setting, individual */ 224 /* bits set in lowlevel_init.S */ 225#define CONFIG_SYS_MDMRS_VAL 0x00000000 226 227/* 228 * PCMCIA and CF Interfaces 229 */ 230#define CONFIG_SYS_MECR_VAL 0x00000000 /* Hangover from Lubbock. 231 Needs calculating. (DS/CHC) */ 232#define CONFIG_SYS_MCMEM0_VAL 0x00010504 233#define CONFIG_SYS_MCMEM1_VAL 0x00010504 234#define CONFIG_SYS_MCATT0_VAL 0x00010504 235#define CONFIG_SYS_MCATT1_VAL 0x00010504 236#define CONFIG_SYS_MCIO0_VAL 0x00004715 237#define CONFIG_SYS_MCIO1_VAL 0x00004715 238 239/* 240 * FLASH and environment organization 241 */ 242#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 243#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */ 244 245/* timeout values are in ticks */ 246/* FIXME */ 247#define CONFIG_SYS_FLASH_ERASE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 248#define CONFIG_SYS_FLASH_WRITE_TOUT (25*CONFIG_SYS_HZ) /* Timeout for Flash Write */ 249 250/* Flash protection */ 251#define CONFIG_SYS_FLASH_PROTECTION 1 252 253/* FIXME */ 254#define CONFIG_ENV_IS_IN_FLASH 1 255#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x3C000) /* Addr of Environment Sector */ 256#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment */ 257#define CONFIG_ENV_SECT_SIZE 0x20000 258 259/* Option added to get around byte ordering issues in the flash driver */ 260#define CONFIG_SYS_LITTLE_ENDIAN 1 261 262#endif /* __CONFIG_H */ 263