1/* 2 * (C) Copyright 2003 Embedded Edge, LLC 3 * Dan Malek <dan@embeddededge.com> 4 * Copied from ADS85xx. 5 * Updates for Silicon Tx GP3 8560 board. 6 * 7 * (C) Copyright 2002,2003 Motorola,Inc. 8 * Xianghua Xiao <X.Xiao@motorola.com> 9 * 10 * See file CREDITS for list of people who contributed to this 11 * project. 12 * 13 * This program is free software; you can redistribute it and/or 14 * modify it under the terms of the GNU General Public License as 15 * published by the Free Software Foundation; either version 2 of 16 * the License, or (at your option) any later version. 17 * 18 * This program is distributed in the hope that it will be useful, 19 * but WITHOUT ANY WARRANTY; without even the implied warranty of 20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 * GNU General Public License for more details. 22 * 23 * You should have received a copy of the GNU General Public License 24 * along with this program; if not, write to the Free Software 25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 26 * MA 02111-1307 USA 27 */ 28 29/* mpc8560ads board configuration file */ 30/* please refer to doc/README.mpc85xx for more info */ 31/* make sure you change the MAC address and other network params first, 32 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file 33 */ 34 35#ifndef __CONFIG_H 36#define __CONFIG_H 37 38/* High Level Configuration Options */ 39#define CONFIG_BOOKE 1 /* BOOKE */ 40#define CONFIG_E500 1 /* BOOKE e500 family */ 41#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ 42#define CONFIG_CPM2 1 /* has CPM2 */ 43#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/ 44#define CONFIG_MPC8560 1 45 46#undef CONFIG_PCI /* pci ethernet support */ 47#define CONFIG_TSEC_ENET /* tsec ethernet support*/ 48#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ 49#define CONFIG_ENV_OVERWRITE 50 51#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ 52 53/* sysclk for MPC85xx 54 */ 55 56#define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */ 57 58/* Blinkin' LEDs for Robert :-) 59*/ 60#define CONFIG_SHOW_ACTIVITY 1 61 62/* 63 * These can be toggled for performance analysis, otherwise use default. 64 */ 65#define CONFIG_L2_CACHE /* toggle L2 cache */ 66#define CONFIG_BTB /* toggle branch predition */ 67 68#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ 69 70#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ 71#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ 72#define CONFIG_SYS_MEMTEST_END 0x00400000 73 74 75/* Localbus SDRAM is an option, not all boards have it. 76 * This address, however, is used to configure a 256M local bus 77 * window that includes the Config latch below. 78 */ 79#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ 80#define CONFIG_SYS_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */ 81 82#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ 83#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */ 84 85#define CONFIG_SYS_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */ 86#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ 87#define CONFIG_SYS_MAX_FLASH_SECT 136 /* sectors per device */ 88#undef CONFIG_SYS_FLASH_CHECKSUM 89#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */ 90#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 91 92/* The configuration latch is Chip Select 1. 93 * It's an 8-bit latch in the lower 8 bits of the word. 94 */ 95#define CONFIG_SYS_BR1_PRELIM 0xfc001801 /* 32-bit port */ 96#define CONFIG_SYS_OR1_PRELIM 0xffff0ff7 /* 64K is enough */ 97#define CONFIG_SYS_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */ 98 99#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ 100 101#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 102#define CONFIG_SYS_RAMBOOT 103#else 104#undef CONFIG_SYS_RAMBOOT 105#endif 106 107#ifdef CONFIG_SYS_RAMBOOT 108#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ 109#else 110#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ 111#endif 112#define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ 113#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ 114#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ 115 116/* DDR Setup */ 117#define CONFIG_FSL_DDR1 118#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ 119#define CONFIG_DDR_SPD 120#undef CONFIG_FSL_DDR_INTERACTIVE 121 122#undef CONFIG_DDR_ECC /* only for ECC DDR module */ 123#define CONFIG_DDR_DLL /* possible DLL fix needed */ 124#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ 125 126#define CONFIG_MEM_INIT_VALUE 0xDeadBeef 127 128#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ 129#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 130 131#define CONFIG_NUM_DDR_CONTROLLERS 1 132#define CONFIG_DIMM_SLOTS_PER_CTLR 1 133#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) 134 135/* I2C addresses of SPD EEPROMs */ 136#define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */ 137 138#undef CONFIG_CLOCKS_IN_MHZ 139 140/* local bus definitions */ 141#define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ 142#define CONFIG_SYS_OR2_PRELIM 0xfc006901 143#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */ 144#define CONFIG_SYS_LBC_LBCR 0x00000000 145#define CONFIG_SYS_LBC_LSRT 0x20000000 146#define CONFIG_SYS_LBC_MRTPR 0x20000000 147#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 148#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 149#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 150#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 151#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 152 153#define CONFIG_SYS_INIT_RAM_LOCK 1 154#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ 155#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ 156 157#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ 158#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) 159#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 160 161#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ 162#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ 163 164/* Serial Port */ 165#define CONFIG_CONS_ON_SCC /* define if console on SCC */ 166#undef CONFIG_CONS_NONE /* define if console on something else */ 167#define CONFIG_CONS_INDEX 2 /* which serial channel for console */ 168 169#define CONFIG_BAUDRATE 38400 170 171#define CONFIG_SYS_BAUDRATE_TABLE \ 172 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} 173 174/* Use the HUSH parser */ 175#define CONFIG_SYS_HUSH_PARSER 176#ifdef CONFIG_SYS_HUSH_PARSER 177#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 178#endif 179 180/* 181 * I2C 182 */ 183#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ 184#define CONFIG_HARD_I2C /* I2C with hardware support*/ 185#undef CONFIG_SOFT_I2C /* I2C bit-banged */ 186#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ 187#define CONFIG_SYS_I2C_SLAVE 0x7F 188#if 0 189#define CONFIG_SYS_I2C_NOPROBES {0x00} /* Don't probe these addrs */ 190#else 191/* I did the 'if 0' so we could keep the syntax above if ever needed. */ 192#undef CONFIG_SYS_I2C_NOPROBES 193#endif 194#define CONFIG_SYS_I2C_OFFSET 0x3000 195 196/* RapdIO Map configuration, mapped 1:1. 197*/ 198#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000 199#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE 200#define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */ 201 202/* Standard 8560 PCI addressing, mapped 1:1. 203*/ 204#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 205#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE 206#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ 207#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000 208#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE 209#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16 M */ 210 211#if defined(CONFIG_PCI) /* PCI Ethernet card */ 212 213#define CONFIG_NET_MULTI 214#define CONFIG_PCI_PNP /* do pci plug-and-play */ 215 216#undef CONFIG_EEPRO100 217#undef CONFIG_TULIP 218 219#if !defined(CONFIG_PCI_PNP) 220 #define PCI_ENET0_IOADDR 0xe0000000 221 #define PCI_ENET0_MEMADDR 0xe0000000 222 #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ 223#endif 224 225#undef CONFIG_PCI_SCAN_SHOW 226#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ 227 228#endif /* CONFIG_PCI */ 229 230#if defined(CONFIG_TSEC_ENET) 231 232#ifndef CONFIG_NET_MULTI 233#define CONFIG_NET_MULTI 1 234#endif 235 236#define CONFIG_MII 1 /* MII PHY management */ 237 238#define CONFIG_TSEC1 1 239#define CONFIG_TSEC1_NAME "TSEC0" 240#define CONFIG_TSEC2 1 241#define CONFIG_TSEC2_NAME "TSEC1" 242 243#define TSEC1_PHY_ADDR 2 244#define TSEC2_PHY_ADDR 4 245#define TSEC1_PHYIDX 0 246#define TSEC2_PHYIDX 0 247#define TSEC1_FLAGS TSEC_GIGABIT 248#define TSEC2_FLAGS TSEC_GIGABIT 249#define CONFIG_ETHPRIME "TSEC0" 250 251#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ 252 253#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */ 254#undef CONFIG_ETHER_NONE /* define if ether on something else */ 255#define CONFIG_ETHER_INDEX 2 /* which channel for ether */ 256 257#if (CONFIG_ETHER_INDEX == 2) 258 /* 259 * - Rx-CLK is CLK13 260 * - Tx-CLK is CLK14 261 * - Select bus for bd/buffers 262 * - Full duplex 263 */ 264 #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 265 #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 266 #define CONFIG_SYS_CPMFCR_RAMTYPE 0 267#if 0 268 #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) 269#else 270 #define CONFIG_SYS_FCC_PSMR 0 271#endif 272 #define FETH2_RST 0x01 273#elif (CONFIG_ETHER_INDEX == 3) 274 /* need more definitions here for FE3 */ 275 #define FETH3_RST 0x80 276#endif /* CONFIG_ETHER_INDEX */ 277 278/* MDIO is done through the TSEC0 control. 279*/ 280#define CONFIG_MII /* MII PHY management */ 281#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */ 282 283#endif 284 285/* Environment */ 286/* We use the top boot sector flash, so we have some 16K sectors for env 287 */ 288#ifndef CONFIG_SYS_RAMBOOT 289 #define CONFIG_ENV_IS_IN_FLASH 1 290 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) 291 #define CONFIG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */ 292 #define CONFIG_ENV_SIZE 0x2000 293#else 294 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ 295 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ 296 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) 297 #define CONFIG_ENV_SIZE 0x2000 298#endif 299 300#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400" 301#define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000" 302#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ 303 304#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 305#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 306 307/* 308 * BOOTP options 309 */ 310#define CONFIG_BOOTP_BOOTFILESIZE 311#define CONFIG_BOOTP_BOOTPATH 312#define CONFIG_BOOTP_GATEWAY 313#define CONFIG_BOOTP_HOSTNAME 314 315 316/* 317 * Command line configuration. 318 */ 319#include <config_cmd_default.h> 320 321#define CONFIG_CMD_PING 322#define CONFIG_CMD_I2C 323 324#if defined(CONFIG_SYS_RAMBOOT) 325 #undef CONFIG_CMD_SAVEENV 326 #undef CONFIG_CMD_LOADS 327#else 328 #define CONFIG_CMD_ELF 329#endif 330 331#if defined(CONFIG_PCI) 332 #define CONFIG_CMD_PCI 333#endif 334 335#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 336 #define CONFIG_CMD_MII 337#endif 338 339 340#undef CONFIG_WATCHDOG /* watchdog disabled */ 341 342/* 343 * Miscellaneous configurable options 344 */ 345#define CONFIG_SYS_LONGHELP /* undef to save memory */ 346#define CONFIG_SYS_PROMPT "GPPP=> " /* Monitor Command Prompt */ 347#if defined(CONFIG_CMD_KGDB) 348#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 349#else 350#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 351#endif 352#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 353#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 354#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 355#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ 356#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ 357 358/* 359 * For booting Linux, the board info and command line data 360 * have to be in the first 8 MB of memory, since this is 361 * the maximum mapped by the Linux kernel during initialization. 362 */ 363#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 364 365/* 366 * Internal Definitions 367 * 368 * Boot Flags 369 */ 370#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ 371#define BOOTFLAG_WARM 0x02 /* Software reboot */ 372 373#if defined(CONFIG_CMD_KGDB) 374#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ 375#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ 376#endif 377 378/*Note: change below for your network setting!!! */ 379#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) 380#define CONFIG_HAS_ETH0 381#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a 382#define CONFIG_HAS_ETH1 383#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b 384#define CONFIG_HAS_ETH2 385#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c 386#endif 387 388#define CONFIG_SERVERIP 192.168.85.1 389#define CONFIG_IPADDR 192.168.85.60 390#define CONFIG_GATEWAYIP 192.168.85.1 391#define CONFIG_NETMASK 255.255.255.0 392#define CONFIG_HOSTNAME STX_GP3 393#define CONFIG_ROOTPATH /gppproot 394#define CONFIG_BOOTFILE uImage 395#define CONFIG_LOADADDR 0x1000000 396 397#endif /* __CONFIG_H */ 398