1/* 2 * (C) Copyright 2002 3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net 4 * 5 * (C) Copyright 2002 6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com> 7 * Marius Groeger <mgroeger@sysgo.de> 8 * 9 * See file CREDITS for list of people who contributed to this 10 * project. 11 * 12 * This program is free software; you can redistribute it and/or 13 * modify it under the terms of the GNU General Public License as 14 * published by the Free Software Foundation; either version 2 of 15 * the License, or (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 25 * MA 02111-1307 USA 26 */ 27 28#ifndef __CONFIG_H 29#define __CONFIG_H 30 31/* 32 * High Level Configuration Options 33 * (easy to change) 34 */ 35#define CONFIG_PXA250 1 /* This is an PXA250 CPU */ 36#define CONFIG_XM250 1 /* on a MicroSys XM250 Board */ 37#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ 38 39/* 40 * Size of malloc() pool; this lives below the uppermost 128 KiB which are 41 * used for the RAM copy of the uboot code 42 * 43 */ 44#define CONFIG_SYS_MALLOC_LEN (256*1024) 45#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ 46 47/* 48 * Hardware drivers 49 */ 50#define CONFIG_DRIVER_SMC91111 51#define CONFIG_SMC91111_BASE 0x04000300 52#undef CONFIG_SMC91111_EXT_PHY 53#define CONFIG_SMC_USE_32_BIT 54#undef CONFIG_SHOW_ACTIVITY 55#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */ 56 57/* 58 * I2C bus 59 */ 60#define CONFIG_HARD_I2C 1 61#define CONFIG_SYS_I2C_SPEED 50000 62#define CONFIG_SYS_I2C_SLAVE 0xfe 63 64#define CONFIG_RTC_PCF8563 1 65#define CONFIG_SYS_I2C_RTC_ADDR 0x51 66 67#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* A0 = 0 (hardwired) */ 68#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 4 bits = 16 octets */ 69#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */ 70#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* length of address */ 71#define CONFIG_SYS_EEPROM_SIZE 2048 /* size in bytes */ 72#undef CONFIG_SYS_I2C_INIT_BOARD /* board has no own init */ 73 74/* 75 * select serial console configuration 76 */ 77#define CONFIG_FFUART 1 /* we use FFUART */ 78 79/* allow to overwrite serial and ethaddr */ 80#define CONFIG_ENV_OVERWRITE 81 82#define CONFIG_BAUDRATE 115200 83 84 85/* 86 * BOOTP options 87 */ 88#define CONFIG_BOOTP_BOOTFILESIZE 89#define CONFIG_BOOTP_BOOTPATH 90#define CONFIG_BOOTP_GATEWAY 91#define CONFIG_BOOTP_HOSTNAME 92 93 94/* 95 * Command line configuration. 96 */ 97#include <config_cmd_default.h> 98 99#define CONFIG_CMD_ELF 100#define CONFIG_CMD_EEPROM 101#define CONFIG_CMD_DATE 102#define CONFIG_CMD_I2C 103 104 105#define CONFIG_BOOTDELAY 3 106 107/* 108 * Miscellaneous configurable options 109 */ 110#define CONFIG_SYS_LONGHELP /* undef to save memory */ 111#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ 112#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 113#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 114#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 115#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 116 117#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */ 118#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */ 119 120#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ 121 122#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */ 123 124#define CONFIG_SYS_HZ 1000 125#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/400/100 MHz */ 126 127 /* valid baudrates */ 128 129#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 130 131/* 132 * Definitions related to passing arguments to kernel. 133 */ 134#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */ 135#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */ 136#define CONFIG_INITRD_TAG 1 /* do not send initrd params */ 137#undef CONFIG_VFD /* do not send framebuffer setup */ 138 139/* 140 * Stack sizes 141 * 142 * The stack sizes are set up in start.S using the settings below 143 */ 144#define CONFIG_STACKSIZE (128*1024) /* regular stack */ 145#ifdef CONFIG_USE_IRQ 146#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ 147#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ 148#endif 149 150/* 151 * Physical Memory Map 152 */ 153#define CONFIG_NR_DRAM_BANKS 4 154#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */ 155#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ 156#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */ 157#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */ 158#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */ 159#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */ 160#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */ 161#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */ 162 163#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ 164#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */ 165#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */ 166#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */ 167#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */ 168 169#define CONFIG_SYS_DRAM_BASE 0xa0000000 170#define CONFIG_SYS_DRAM_SIZE 0x04000000 171 172#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 173 174/* 175 * FLASH and environment organization 176 */ 177#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 178#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ 179 180/* timeout values are in ticks */ 181#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ 182#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */ 183#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Set Lock Bit */ 184#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Clear Lock Bits */ 185#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 186 187#define CONFIG_ENV_IS_IN_FLASH 1 188#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector */ 189#define CONFIG_ENV_SIZE 0x4000 190#define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */ 191#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */ 192 193/****************************************************************************** 194 * 195 * CPU specific defines 196 * 197 ******************************************************************************/ 198 199/* 200 * GPIO settings 201 * 202 * GPIO pin assignments 203 * GPIO Name Dir Out AF 204 * 0 NC 205 * 1 NC 206 * 2 SIRQ1 I 207 * 3 SIRQ2 I 208 * 4 SIRQ3 I 209 * 5 DMAACK1 O 0 210 * 6 DMAACK2 O 0 211 * 7 DMAACK3 O 0 212 * 8 TC1 O 0 213 * 9 TC2 O 0 214 * 10 TC3 O 0 215 * 11 nDMAEN O 1 216 * 12 AENCTRL O 0 217 * 13 PLDTC O 0 218 * 14 ETHIRQ I 219 * 15 NC 220 * 16 NC 221 * 17 NC 222 * 18 RDY I 223 * 19 DMASIO I 224 * 20 ETHIRQ NC 225 * 21 NC 226 * 22 PGMEN O 1 FIXME for debug only enable flash 227 * 23 NC 228 * 24 NC 229 * 25 NC 230 * 26 NC 231 * 27 NC 232 * 28 NC 233 * 29 NC 234 * 30 NC 235 * 31 NC 236 * 32 NC 237 * 33 NC 238 * 34 FFRXD I 01 239 * 35 FFCTS I 01 240 * 36 FFDCD I 01 241 * 37 FFDSR I 01 242 * 38 FFRI I 01 243 * 39 FFTXD O 1 10 244 * 40 FFDTR O 0 10 245 * 41 FFRTS O 0 10 246 * 42 RS232FOFF O 0 00 247 * 43 NC 248 * 44 NC 249 * 45 IRSL0 O 0 250 * 46 IRRX0 I 01 251 * 47 IRTX0 O 0 10 252 * 48 NC 253 * 49 nIOWE O 0 254 * 50 NC 255 * 51 NC 256 * 52 NC 257 * 53 NC 258 * 54 NC 259 * 55 NC 260 * 56 NC 261 * 57 NC 262 * 58 DKDIRQ I 263 * 59 NC 264 * 60 NC 265 * 61 NC 266 * 62 NC 267 * 63 NC 268 * 64 COMLED O 0 269 * 65 COMLED O 0 270 * 66 COMLED O 0 271 * 67 COMLED O 0 272 * 68 COMLED O 0 273 * 69 COMLED O 0 274 * 70 COMLED O 0 275 * 71 COMLED O 0 276 * 72 NC 277 * 73 NC 278 * 74 NC 279 * 75 NC 280 * 76 NC 281 * 77 NC 282 * 78 CSIO O 1 283 * 79 NC 284 * 80 CSETH O 1 285 * 286 * NOTE: All NC's are defined to be outputs 287 * 288 */ 289/* Pin direction control */ 290#define CONFIG_SYS_GPDR0_VAL 0xd3808000 291#define CONFIG_SYS_GPDR1_VAL 0xfcffab83 292#define CONFIG_SYS_GPDR2_VAL 0x0001ffff 293/* Set and Clear registers */ 294#define CONFIG_SYS_GPSR0_VAL 0x00008000 295#define CONFIG_SYS_GPSR1_VAL 0x00ff0002 296#define CONFIG_SYS_GPSR2_VAL 0x0001c000 297#define CONFIG_SYS_GPCR0_VAL 0x00000000 298#define CONFIG_SYS_GPCR1_VAL 0x00000000 299#define CONFIG_SYS_GPCR2_VAL 0x00000000 300/* Edge detect registers (these are set by the kernel) */ 301#define CONFIG_SYS_GRER0_VAL 0x00002180 302#define CONFIG_SYS_GRER1_VAL 0x00000000 303#define CONFIG_SYS_GRER2_VAL 0x00000000 304#define CONFIG_SYS_GFER0_VAL 0x000043e0 305#define CONFIG_SYS_GFER1_VAL 0x00000000 306#define CONFIG_SYS_GFER2_VAL 0x00000000 307/* Alternate function registers */ 308#define CONFIG_SYS_GAFR0_L_VAL 0x80000004 309#define CONFIG_SYS_GAFR0_U_VAL 0x595a8010 310#define CONFIG_SYS_GAFR1_L_VAL 0x699a9559 311#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aaaa 312#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa 313#define CONFIG_SYS_GAFR2_U_VAL 0x00000002 314 315/* 316 * Clocks, power control and interrupts 317 */ 318#define CONFIG_SYS_PSSR_VAL 0x00000030 319#define CONFIG_SYS_CCCR_VAL 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */ 320#define CONFIG_SYS_CKEN_VAL 0x000141ec /* FFUART and STUART enabled */ 321#define CONFIG_SYS_ICMR_VAL 0x00000000 /* No interrupts enabled */ 322 323/* FIXME 324 * 325 * RTC settings 326 * Watchdog 327 * 328 */ 329 330/* 331 * Memory settings 332 * 333 */ 334#define CONFIG_SYS_MSC0_VAL 0x122423f0 /* FLASH / LAN (cs0)/(cS1) */ 335#define CONFIG_SYS_MSC1_VAL 0x35f4aa4c /* USB / ST3+ST5 (cs2)/(cS3) */ 336#define CONFIG_SYS_MSC2_VAL 0x35f435fc /* IDE / BCR + WatchDog (cs4)/(cS5) */ 337#define CONFIG_SYS_MDCNFG_VAL 0x000009c9 338#define CONFIG_SYS_MDMRS_VAL 0x00220022 339#define CONFIG_SYS_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in lowlevel_init.S */ 340 341/* 342 * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init) 343 */ 344#define CONFIG_SYS_MECR_VAL 0x00000000 345#define CONFIG_SYS_MCMEM0_VAL 0x00010504 346#define CONFIG_SYS_MCMEM1_VAL 0x00010504 347#define CONFIG_SYS_MCATT0_VAL 0x00010504 348#define CONFIG_SYS_MCATT1_VAL 0x00010504 349#define CONFIG_SYS_MCIO0_VAL 0x00004715 350#define CONFIG_SYS_MCIO1_VAL 0x00004715 351 352/* Board specific defines */ 353 354#ifndef __ASSEMBLY__ 355 356/* global prototypes */ 357void led_code(int code, int color); 358 359#endif 360 361#endif /* __CONFIG_H */ 362