LXR uboot/lib_ppc/bat

   1/*
   2 * (C) Copyright 2002
   3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
   4 *
   5 * See file CREDITS for list of people who contributed to this
   6 * project.
   7 *
   8 * This program is free software; you can redistribute it and/or
   9 * modify it under the terms of the GNU General Public License as
  10 * published by the Free Software Foundation; either version 2 of
  11 * the License, or (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 *
  23 */
  24
  25#include <common.h>
  26#include <asm/processor.h>
  27#include <asm/mmu.h>
  28#include <asm/io.h>
  29
  30#ifdef CONFIG_ADDR_MAP
  31#include <addr_map.h>
  32#endif
  33
  34DECLARE_GLOBAL_DATA_PTR;
  35
  36int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower)
  37{
  38        int batn = -1;
  39
  40        sync();
  41
  42        switch (bat) {
  43        case DBAT0:
  44                mtspr (DBAT0L, lower);
  45                mtspr (DBAT0U, upper);
  46                batn = 0;
  47                break;
  48        case IBAT0:
  49                mtspr (IBAT0L, lower);
  50                mtspr (IBAT0U, upper);
  51                break;
  52        case DBAT1:
  53                mtspr (DBAT1L, lower);
  54                mtspr (DBAT1U, upper);
  55                batn = 1;
  56                break;
  57        case IBAT1:
  58                mtspr (IBAT1L, lower);
  59                mtspr (IBAT1U, upper);
  60                break;
  61        case DBAT2:
  62                mtspr (DBAT2L, lower);
  63                mtspr (DBAT2U, upper);
  64                batn = 2;
  65                break;
  66        case IBAT2:
  67                mtspr (IBAT2L, lower);
  68                mtspr (IBAT2U, upper);
  69                break;
  70        case DBAT3:
  71                mtspr (DBAT3L, lower);
  72                mtspr (DBAT3U, upper);
  73                batn = 3;
  74                break;
  75        case IBAT3:
  76                mtspr (IBAT3L, lower);
  77                mtspr (IBAT3U, upper);
  78                break;
  79#ifdef CONFIG_HIGH_BATS
  80        case DBAT4:
  81                mtspr (DBAT4L, lower);
  82                mtspr (DBAT4U, upper);
  83                batn = 4;
  84                break;
  85        case IBAT4:
  86                mtspr (IBAT4L, lower);
  87                mtspr (IBAT4U, upper);
  88                break;
  89        case DBAT5:
  90                mtspr (DBAT5L, lower);
  91                mtspr (DBAT5U, upper);
  92                batn = 5;
  93                break;
  94        case IBAT5:
  95                mtspr (IBAT5L, lower);
  96                mtspr (IBAT5U, upper);
  97                break;
  98        case DBAT6:
  99                mtspr (DBAT6L, lower);
 100                mtspr (DBAT6U, upper);
 101                batn = 6;
 102                break;
 103        case IBAT6:
 104                mtspr (IBAT6L, lower);
 105                mtspr (IBAT6U, upper);
 106                break;
 107        case DBAT7:
 108                mtspr (DBAT7L, lower);
 109                mtspr (DBAT7U, upper);
 110                batn = 7;
 111                break;
 112        case IBAT7:
 113                mtspr (IBAT7L, lower);
 114                mtspr (IBAT7U, upper);
 115                break;
 116#endif
 117        default:
 118                return (-1);
 119        }
 120
 121#ifdef CONFIG_ADDR_MAP
 122        if ((gd->flags & GD_FLG_RELOC) && (batn >= 0)) {
 123                phys_size_t size;
 124                if (!BATU_VALID(upper))
 125                        size = 0;
 126                else
 127                        size = BATU_SIZE(upper);
 128                addrmap_set_entry(BATU_VADDR(upper), BATL_PADDR(lower),
 129                                  size, batn);
 130        }
 131#endif
 132
 133        sync();
 134        isync();
 135
 136        return (0);
 137}
 138
 139int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower)
 140{
 141        unsigned long register u;
 142        unsigned long register l;
 143
 144        switch (bat) {
 145        case DBAT0:
 146                l = mfspr (DBAT0L);
 147                u = mfspr (DBAT0U);
 148                break;
 149        case IBAT0:
 150                l = mfspr (IBAT0L);
 151                u = mfspr (IBAT0U);
 152                break;
 153        case DBAT1:
 154                l = mfspr (DBAT1L);
 155                u = mfspr (DBAT1U);
 156                break;
 157        case IBAT1:
 158                l = mfspr (IBAT1L);
 159                u = mfspr (IBAT1U);
 160                break;
 161        case DBAT2:
 162                l = mfspr (DBAT2L);
 163                u = mfspr (DBAT2U);
 164                break;
 165        case IBAT2:
 166                l = mfspr (IBAT2L);
 167                u = mfspr (IBAT2U);
 168                break;
 169        case DBAT3:
 170                l = mfspr (DBAT3L);
 171                u = mfspr (DBAT3U);
 172                break;
 173        case IBAT3:
 174                l = mfspr (IBAT3L);
 175                u = mfspr (IBAT3U);
 176                break;
 177#ifdef CONFIG_HIGH_BATS
 178        case DBAT4:
 179                l = mfspr (DBAT4L);
 180                u = mfspr (DBAT4U);
 181                break;
 182        case IBAT4:
 183                l = mfspr (IBAT4L);
 184                u = mfspr (IBAT4U);
 185                break;
 186        case DBAT5:
 187                l = mfspr (DBAT5L);
 188                u = mfspr (DBAT5U);
 189                break;
 190        case IBAT5:
 191                l = mfspr (IBAT5L);
 192                u = mfspr (IBAT5U);
 193                break;
 194        case DBAT6:
 195                l = mfspr (DBAT6L);
 196                u = mfspr (DBAT6U);
 197                break;
 198        case IBAT6:
 199                l = mfspr (IBAT6L);
 200                u = mfspr (IBAT6U);
 201                break;
 202        case DBAT7:
 203                l = mfspr (DBAT7L);
 204                u = mfspr (DBAT7U);
 205                break;
 206        case IBAT7:
 207                l = mfspr (IBAT7L);
 208                u = mfspr (IBAT7U);
 209                break;
 210#endif
 211        default:
 212                return (-1);
 213        }
 214
 215        *upper = u;
 216        *lower = l;
 217
 218        return (0);
 219}
 220
 221void print_bats(void)
 222{
 223        printf("BAT registers:\n");
 224
 225        printf ("\tIBAT0L = 0x%08X ", mfspr (IBAT0L));
 226        printf ("\tIBAT0U = 0x%08X\n", mfspr (IBAT0U));
 227        printf ("\tDBAT0L = 0x%08X ", mfspr (DBAT0L));
 228        printf ("\tDBAT0U = 0x%08X\n", mfspr (DBAT0U));
 229        printf ("\tIBAT1L = 0x%08X ", mfspr (IBAT1L));
 230        printf ("\tIBAT1U = 0x%08X\n", mfspr (IBAT1U));
 231        printf ("\tDBAT1L = 0x%08X ", mfspr (DBAT1L));
 232        printf ("\tDBAT1U = 0x%08X\n", mfspr (DBAT1U));
 233        printf ("\tIBAT2L = 0x%08X ", mfspr (IBAT2L));
 234        printf ("\tIBAT2U = 0x%08X\n", mfspr (IBAT2U));
 235        printf ("\tDBAT2L = 0x%08X ", mfspr (DBAT2L));
 236        printf ("\tDBAT2U = 0x%08X\n", mfspr (DBAT2U));
 237        printf ("\tIBAT3L = 0x%08X ", mfspr (IBAT3L));
 238        printf ("\tIBAT3U = 0x%08X\n", mfspr (IBAT3U));
 239        printf ("\tDBAT3L = 0x%08X ", mfspr (DBAT3L));
 240        printf ("\tDBAT3U = 0x%08X\n", mfspr (DBAT3U));
 241
 242#ifdef CONFIG_HIGH_BATS
 243        printf ("\tIBAT4L = 0x%08X ", mfspr (IBAT4L));
 244        printf ("\tIBAT4U = 0x%08X\n", mfspr (IBAT4U));
 245        printf ("\tDBAT4L = 0x%08X ", mfspr (DBAT4L));
 246        printf ("\tDBAT4U = 0x%08X\n", mfspr (DBAT4U));
 247        printf ("\tIBAT5L = 0x%08X ", mfspr (IBAT5L));
 248        printf ("\tIBAT5U = 0x%08X\n", mfspr (IBAT5U));
 249        printf ("\tDBAT5L = 0x%08X ", mfspr (DBAT5L));
 250        printf ("\tDBAT5U = 0x%08X\n", mfspr (DBAT5U));
 251        printf ("\tIBAT6L = 0x%08X ", mfspr (IBAT6L));
 252        printf ("\tIBAT6U = 0x%08X\n", mfspr (IBAT6U));
 253        printf ("\tDBAT6L = 0x%08X ", mfspr (DBAT6L));
 254        printf ("\tDBAT6U = 0x%08X\n", mfspr (DBAT6U));
 255        printf ("\tIBAT7L = 0x%08X ", mfspr (IBAT7L));
 256        printf ("\tIBAT7U = 0x%08X\n", mfspr (IBAT7U));
 257        printf ("\tDBAT7L = 0x%08X ", mfspr (DBAT7L));
 258        printf ("\tDBAT7U = 0x%08X\n", mfspr (DBAT7U));
 259#endif
 260}
 261