LXR uboot/board/ads5121/ads5121.c

   1/*
   2 * (C) Copyright 2007 DENX Software Engineering
   3 *
   4 * See file CREDITS for list of people who contributed to this
   5 * project.
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License as
   9 * published by the Free Software Foundation; either version 2 of
  10 * the License, or (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 * MA 02111-1307 USA
  21 *
  22 */
  23
  24#include <common.h>
  25#include <mpc512x.h>
  26#include <asm/bitops.h>
  27#include <command.h>
  28#include <asm/processor.h>
  29#include <fdt_support.h>
  30#ifdef CONFIG_MISC_INIT_R
  31#include <i2c.h>
  32#endif
  33
  34DECLARE_GLOBAL_DATA_PTR;
  35
  36/* Clocks in use */
  37#define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN |                           \
  38                         CLOCK_SCCR1_LPC_EN |                           \
  39                         CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) |       \
  40                         CLOCK_SCCR1_PSCFIFO_EN |                       \
  41                         CLOCK_SCCR1_DDR_EN |                           \
  42                         CLOCK_SCCR1_FEC_EN |                           \
  43                         CLOCK_SCCR1_PATA_EN |                          \
  44                         CLOCK_SCCR1_PCI_EN |                           \
  45                         CLOCK_SCCR1_TPR_EN)
  46
  47#define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN |           \
  48                         CLOCK_SCCR2_SPDIF_EN |         \
  49                         CLOCK_SCCR2_DIU_EN |           \
  50                         CLOCK_SCCR2_I2C_EN)
  51
  52#define CSAW_START(start)       ((start) & 0xFFFF0000)
  53#define CSAW_STOP(start, size)  (((start) + (size) - 1) >> 16)
  54
  55long int fixed_sdram(void);
  56
  57int board_early_init_f (void)
  58{
  59        volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  60        u32 lpcaw;
  61
  62        /*
  63         * Initialize Local Window for the CPLD registers access (CS2 selects
  64         * the CPLD chip)
  65         */
  66        im->sysconf.lpcs2aw = CSAW_START(CONFIG_SYS_CPLD_BASE) |
  67                              CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE);
  68        im->lpc.cs_cfg[2] = CONFIG_SYS_CS2_CFG;
  69
  70        /*
  71         * According to MPC5121e RM, configuring local access windows should
  72         * be followed by a dummy read of the config register that was
  73         * modified last and an isync
  74         */
  75        lpcaw = im->sysconf.lpcs2aw;
  76        __asm__ __volatile__ ("isync");
  77
  78        /*
  79         * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
  80         *
  81         * Without this the flash identification routine fails, as it needs to issue
  82         * write commands in order to establish the device ID.
  83         */
  84
  85#ifdef CONFIG_ADS5121_REV2
  86        *((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
  87#else
  88        if (*((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
  89                *((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
  90        } else {
  91                /* running from Backup flash */
  92                *((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0x32;
  93        }
  94#endif
  95        /*
  96         * Configure Flash Speed
  97         */
  98        *((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS0_CONFIG)) = CONFIG_SYS_CS0_CFG;
  99        if (SVR_MJREV (im->sysconf.spridr) >= 2) {
 100                *((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CONFIG_SYS_CS_ALETIMING;
 101        }
 102        /*
 103         * Enable clocks
 104         */
 105        im->clk.sccr[0] = SCCR1_CLOCKS_EN;
 106        im->clk.sccr[1] = SCCR2_CLOCKS_EN;
 107#if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
 108        im->clk.sccr[1] |= CLOCK_SCCR2_IIM_EN;
 109#endif
 110
 111        return 0;
 112}
 113
 114phys_size_t initdram (int board_type)
 115{
 116        u32 msize = 0;
 117
 118        msize = fixed_sdram ();
 119
 120        return msize;
 121}
 122
 123/*
 124 * fixed sdram init -- the board doesn't use memory modules that have serial presence
 125 * detect or similar mechanism for discovery of the DRAM settings
 126 */
 127long int fixed_sdram (void)
 128{
 129        volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 130        u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
 131        u32 msize_log2 = __ilog2 (msize);
 132        u32 i;
 133
 134        /* Initialize IO Control */
 135        im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR;
 136
 137        /* Initialize DDR Local Window */
 138        im->sysconf.ddrlaw.bar = CONFIG_SYS_DDR_BASE & 0xFFFFF000;
 139        im->sysconf.ddrlaw.ar = msize_log2 - 1;
 140
 141        /*
 142         * According to MPC5121e RM, configuring local access windows should
 143         * be followed by a dummy read of the config register that was
 144         * modified last and an isync
 145         */
 146        i = im->sysconf.ddrlaw.ar;
 147        __asm__ __volatile__ ("isync");
 148
 149        /* Enable DDR */
 150        im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_EN;
 151
 152        /* Initialize DDR Priority Manager */
 153        im->mddrc.prioman_config1 = CONFIG_SYS_MDDRCGRP_PM_CFG1;
 154        im->mddrc.prioman_config2 = CONFIG_SYS_MDDRCGRP_PM_CFG2;
 155        im->mddrc.hiprio_config = CONFIG_SYS_MDDRCGRP_HIPRIO_CFG;
 156        im->mddrc.lut_table0_main_upper = CONFIG_SYS_MDDRCGRP_LUT0_MU;
 157        im->mddrc.lut_table0_main_lower = CONFIG_SYS_MDDRCGRP_LUT0_ML;
 158        im->mddrc.lut_table1_main_upper = CONFIG_SYS_MDDRCGRP_LUT1_MU;
 159        im->mddrc.lut_table1_main_lower = CONFIG_SYS_MDDRCGRP_LUT1_ML;
 160        im->mddrc.lut_table2_main_upper = CONFIG_SYS_MDDRCGRP_LUT2_MU;
 161        im->mddrc.lut_table2_main_lower = CONFIG_SYS_MDDRCGRP_LUT2_ML;
 162        im->mddrc.lut_table3_main_upper = CONFIG_SYS_MDDRCGRP_LUT3_MU;
 163        im->mddrc.lut_table3_main_lower = CONFIG_SYS_MDDRCGRP_LUT3_ML;
 164        im->mddrc.lut_table4_main_upper = CONFIG_SYS_MDDRCGRP_LUT4_MU;
 165        im->mddrc.lut_table4_main_lower = CONFIG_SYS_MDDRCGRP_LUT4_ML;
 166        im->mddrc.lut_table0_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT0_AU;
 167        im->mddrc.lut_table0_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT0_AL;
 168        im->mddrc.lut_table1_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT1_AU;
 169        im->mddrc.lut_table1_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT1_AL;
 170        im->mddrc.lut_table2_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT2_AU;
 171        im->mddrc.lut_table2_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT2_AL;
 172        im->mddrc.lut_table3_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT3_AU;
 173        im->mddrc.lut_table3_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT3_AL;
 174        im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU;
 175        im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL;
 176
 177        /* Initialize MDDRC */
 178        im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG;
 179        im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0;
 180        im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1;
 181        im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2;
 182
 183        /* Initialize DDR */
 184        for (i = 0; i < 10; i++)
 185                im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
 186
 187        im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
 188        im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
 189        im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
 190        im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
 191        im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
 192        im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
 193        im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
 194        im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
 195        im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
 196        im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
 197        im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
 198        im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
 199        im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3;
 200        im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL;
 201        im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
 202        im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
 203        im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
 204        im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
 205        im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT;
 206        im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
 207        im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
 208
 209        /* Start MDDRC */
 210        im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN;
 211        im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_RUN;
 212
 213        return msize;
 214}
 215
 216int misc_init_r(void)
 217{
 218        u8 tmp_val;
 219        extern int ads5121_diu_init(void);
 220
 221        /* Using this for DIU init before the driver in linux takes over
 222         *  Enable the TFP410 Encoder (I2C address 0x38)
 223         */
 224
 225        i2c_set_bus_num(2);
 226        tmp_val = 0xBF;
 227        i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
 228        /* Verify if enabled */
 229        tmp_val = 0;
 230        i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
 231        debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
 232
 233        tmp_val = 0x10;
 234        i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
 235        /* Verify if enabled */
 236        tmp_val = 0;
 237        i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
 238        debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
 239
 240#ifdef CONFIG_FSL_DIU_FB
 241#if     !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
 242        ads5121_diu_init();
 243#endif
 244#endif
 245
 246        return 0;
 247}
 248static  iopin_t ioregs_init[] = {
 249        /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
 250        {
 251                IOCTL_SPDIF_TXCLK, 3, 0,
 252                IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 253                IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 254        },
 255        /* Set highest Slew on 9 PATA pins */
 256        {
 257                IOCTL_PATA_CE1, 9, 1,
 258                IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 259                IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 260        },
 261        /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
 262        {
 263                IOCTL_PSC0_0, 15, 0,
 264                IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 265                IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 266        },
 267        /* FUNC1=SPDIF_TXCLK */
 268        {
 269                IOCTL_LPC_CS1, 1, 0,
 270                IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 271                IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 272        },
 273        /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
 274        {
 275                IOCTL_I2C1_SCL, 2, 0,
 276                IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 277                IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 278        },
 279        /* FUNC2=DIU CLK */
 280        {
 281                IOCTL_PSC6_0, 1, 0,
 282                IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 283                IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
 284        },
 285        /* FUNC2=DIU_HSYNC */
 286        {
 287                IOCTL_PSC6_1, 1, 0,
 288                IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 289                IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 290        },
 291        /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
 292        {
 293                IOCTL_PSC6_4, 26, 0,
 294                IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
 295                IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
 296        }
 297};
 298
 299static  iopin_t rev2_silicon_pci_ioregs_init[] = {
 300        /* FUNC0=PCI Sets next 54 to PCI pads */
 301        {
 302                IOCTL_PCI_AD31, 54, 0,
 303                IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
 304        }
 305};
 306
 307int checkboard (void)
 308{
 309        ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
 310        uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
 311        volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 312
 313        printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
 314                brd_rev, cpld_rev);
 315        /* initialize function mux & slew rate IO inter alia on IO Pins  */
 316
 317        iopin_initialize(ioregs_init, sizeof(ioregs_init) / sizeof(ioregs_init[0]));
 318        if (SVR_MJREV (im->sysconf.spridr) >= 2) {
 319                iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
 320        }
 321
 322        return 0;
 323}
 324
 325#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
 326void ft_board_setup(void *blob, bd_t *bd)
 327{
 328        ft_cpu_setup(blob, bd);
 329        fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
 330}
 331#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
 332
 333#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
 334
 335void init_ide_reset (void)
 336{
 337        volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 338        debug ("init_ide_reset\n");
 339
 340        /*
 341         * Clear the reset bit to reset the interface
 342         * cf. RefMan MPC5121EE: 28.4.1 Resetting the ATA Bus
 343         */
 344        immr->pata.pata_ata_control = 0;
 345        udelay(100);
 346        /* Assert the reset bit to enable the interface */
 347        immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
 348        udelay(100);
 349
 350}
 351
 352void ide_set_reset (int idereset)
 353{
 354        volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 355        debug ("ide_set_reset(%d)\n", idereset);
 356
 357        if (idereset) {
 358                immr->pata.pata_ata_control = 0;
 359                udelay(100);
 360        } else {
 361                immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
 362                udelay(100);
 363        }
 364}
 365
 366#define CALC_TIMING(t) (t + period - 1) / period
 367
 368int ide_preinit (void)
 369{
 370        volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 371        long t;
 372        const struct {
 373                short t0;
 374                short t1;
 375                short t2_8;
 376                short t2_16;
 377                short t2i;
 378                short t4;
 379                short t9;
 380                short tA;
 381        } pio_specs = {
 382                .t0    = 600,
 383                .t1    =  70,
 384                .t2_8  = 290,
 385                .t2_16 = 165,
 386                .t2i   =   0,
 387                .t4    =  30,
 388                .t9    =  20,
 389                .tA    =  50,
 390        };
 391        union {
 392                u32 config;
 393                struct {
 394                        u8 field1;
 395                        u8 field2;
 396                        u8 field3;
 397                        u8 field4;
 398                }bytes;
 399        }cfg;
 400
 401        debug ("IDE preinit using PATA peripheral at IMMR-ADDR %08x\n",
 402                (u32)&immr->pata);
 403
 404        /* Set the reset bit to 1 to enable the interface */
 405        immr->pata.pata_ata_control = FSL_ATA_CTRL_ATA_RST_B;
 406
 407        /* Init timings : we use PIO mode 0 timings */
 408        t = 1000000000 / gd->ips_clk;   /* period in ns */
 409        cfg.bytes.field1 = 3;
 410        cfg.bytes.field2 = 3;
 411        cfg.bytes.field3 = (pio_specs.t1 + t) / t;
 412        cfg.bytes.field4 = (pio_specs.t2_8 + t) / t;
 413
 414        immr->pata.pata_time1 = cfg.config;
 415
 416        cfg.bytes.field1 = (pio_specs.t2_8 + t) / t;
 417        cfg.bytes.field2 = (pio_specs.tA + t) / t + 2;
 418        cfg.bytes.field3 = 1;
 419        cfg.bytes.field4 = (pio_specs.t4 + t) / t;
 420
 421        immr->pata.pata_time2 = cfg.config;
 422
 423        cfg.config = immr->pata.pata_time3;
 424        cfg.bytes.field1 = (pio_specs.t9 + t) / t;
 425
 426        immr->pata.pata_time3 = cfg.config;
 427        debug ("PATA preinit complete.\n");
 428
 429        return 0;
 430}
 431
 432#endif /* defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET) */
 433