LXR uboot/board/freescale/mpc8315erdb/sdram.c

   1/*
   2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
   3 *
   4 * Authors: Nick.Spence@freescale.com
   5 *          Wilson.Lo@freescale.com
   6 *          scottwood@freescale.com
   7 *
   8 * See file CREDITS for list of people who contributed to this
   9 * project.
  10 *
  11 * This program is free software; you can redistribute it and/or
  12 * modify it under the terms of the GNU General Public License as
  13 * published by the Free Software Foundation; either version 2 of
  14 * the License, or (at your option) any later version.
  15 *
  16 * This program is distributed in the hope that it will be useful,
  17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18 * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE.  See the
  19 * GNU General Public License for more details.
  20 *
  21 * You should have received a copy of the GNU General Public License
  22 * along with this program; if not, write to the Free Software
  23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24 * MA 02111-1307 USA
  25 */
  26
  27#include <common.h>
  28#include <mpc83xx.h>
  29#include <spd_sdram.h>
  30
  31#include <asm/bitops.h>
  32#include <asm/io.h>
  33
  34#include <asm/processor.h>
  35
  36DECLARE_GLOBAL_DATA_PTR;
  37
  38static void resume_from_sleep(void)
  39{
  40        u32 magic = *(u32 *)0;
  41
  42        typedef void (*func_t)(void);
  43        func_t resume = *(func_t *)4;
  44
  45        if (magic == 0xf5153ae5)
  46                resume();
  47
  48        gd->flags &= ~GD_FLG_SILENT;
  49        puts("\nResume from sleep failed: bad magic word\n");
  50}
  51
  52/* Fixed sdram init -- doesn't use serial presence detect.
  53 *
  54 * This is useful for faster booting in configs where the RAM is unlikely
  55 * to be changed, or for things like NAND booting where space is tight.
  56 */
  57static long fixed_sdram(void)
  58{
  59        volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
  60        u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
  61        u32 msize_log2 = __ilog2(msize);
  62
  63        im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000;
  64        im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
  65        im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
  66
  67        /*
  68         * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
  69         * or the DDR2 controller may fail to initialize correctly.
  70         */
  71        udelay(50000);
  72
  73        im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
  74        im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
  75
  76        /* Currently we use only one CS, so disable the other bank. */
  77        im->ddr.cs_config[1] = 0;
  78
  79        im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
  80        im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  81        im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  82        im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  83        im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  84
  85        if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
  86                im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
  87        else
  88                im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
  89
  90        im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
  91        im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
  92        im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
  93
  94        im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
  95        sync();
  96
  97        /* enable DDR controller */
  98        im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
  99        sync();
 100
 101        return msize;
 102}
 103
 104phys_size_t initdram(int board_type)
 105{
 106        volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 107        u32 msize;
 108
 109        if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
 110                return -1;
 111
 112        /* DDR SDRAM */
 113        msize = fixed_sdram();
 114
 115        if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
 116                resume_from_sleep();
 117
 118        /* return total bus SDRAM size(bytes)  -- DDR */
 119        return msize;
 120}
 121