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20#include <common.h>
21#include <ioports.h>
22#include <mpc83xx.h>
23#include <i2c.h>
24#include <miiphy.h>
25#include <asm/io.h>
26#include <asm/mmu.h>
27#include <asm/processor.h>
28#include <pci.h>
29#include <libfdt.h>
30
31#include "../common/common.h"
32
33extern void disable_addr_trans (void);
34extern void enable_addr_trans (void);
35const qe_iop_conf_t qe_iop_conf_tab[] = {
36
37
38
39 {0, 1, 3, 0, 2},
40 {0, 2, 1, 0, 1},
41
42
43 {1, 14, 1, 0, 1},
44 {1, 15, 1, 0, 1},
45 {1, 20, 2, 0, 1},
46 {1, 21, 2, 0, 1},
47 {1, 18, 1, 0, 1},
48 {1, 26, 2, 0, 1},
49 {1, 27, 2, 0, 1},
50 {1, 24, 2, 0, 1},
51 {1, 25, 2, 0, 1},
52 {2, 15, 2, 0, 1},
53 {2, 16, 2, 0, 1},
54
55
56 {5, 0, 1, 0, 2},
57 {5, 2, 1, 0, 1},
58 {5, 3, 2, 0, 2},
59 {5, 1, 2, 0, 3},
60
61
62 {0, 0, 0, 0, QE_IOP_TAB_END},
63};
64
65static int board_init_i2c_busses (void)
66{
67 I2C_MUX_DEVICE *dev = NULL;
68 uchar *buf;
69
70
71 buf = (unsigned char *) getenv ("dtt_bus");
72 if (buf != NULL)
73 dev = i2c_mux_ident_muxstring (buf);
74 if (dev == NULL) {
75 printf ("Error couldn't add Bus for DTT\n");
76 printf ("please setup dtt_bus to where your\n");
77 printf ("DTT is found.\n");
78 }
79 return 0;
80}
81
82int board_early_init_r (void)
83{
84 unsigned short svid;
85
86
87
88
89
90 svid = SVR_REV(mfspr (SVR));
91 switch (svid) {
92 case 0x0020:
93 setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
94 break;
95 case 0x0021:
96 clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
97 0x00000050, 0x000000a0);
98 break;
99 }
100
101 setbits (8, (void *)(CONFIG_SYS_PIGGY_BASE + 0x10003), 0x01);
102
103 return 0;
104}
105
106int misc_init_r (void)
107{
108
109 board_init_i2c_busses ();
110 return 0;
111}
112
113int fixed_sdram(void)
114{
115 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
116 u32 msize = 0;
117 u32 ddr_size;
118 u32 ddr_size_log2;
119
120 im->sysconf.ddrlaw[0].ar = LAWAR_EN | 0x1e;
121 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
122 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
123 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
124 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
125 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
126 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
127 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
128 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
129 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
130 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
131 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
132 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
133 udelay (200);
134 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
135
136 msize = CONFIG_SYS_DDR_SIZE << 20;
137 disable_addr_trans ();
138 msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
139 enable_addr_trans ();
140 msize /= (1024 * 1024);
141 if (CONFIG_SYS_DDR_SIZE != msize) {
142 for (ddr_size = msize << 20, ddr_size_log2 = 0;
143 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++)
144 if (ddr_size & 1)
145 return -1;
146 im->sysconf.ddrlaw[0].ar =
147 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
148 im->ddr.csbnds[0].csbnds = (((msize / 16) - 1) & 0xff);
149 }
150
151 return msize;
152}
153
154phys_size_t initdram (int board_type)
155{
156#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
157 extern void ddr_enable_ecc (unsigned int dram_size);
158#endif
159 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
160 u32 msize = 0;
161
162 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
163 return -1;
164
165
166 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
167 msize = fixed_sdram ();
168
169#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
170
171
172
173 ddr_enable_ecc (msize * 1024 * 1024);
174#endif
175
176
177 return (msize * 1024 * 1024);
178}
179
180int checkboard (void)
181{
182 puts ("Board: Keymile kmeter1");
183 if (ethernet_present ())
184 puts (" with PIGGY.");
185 puts ("\n");
186 return 0;
187}
188
189#if defined(CONFIG_OF_BOARD_SETUP)
190void ft_board_setup (void *blob, bd_t *bd)
191{
192 ft_cpu_setup (blob, bd);
193}
194#endif
195
196#if defined(CONFIG_HUSH_INIT_VAR)
197extern int ivm_read_eeprom (void);
198int hush_init_var (void)
199{
200 ivm_read_eeprom ();
201 return 0;
202}
203#endif
204