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65#include <common.h>
66#include "mip405.h"
67#include <asm/processor.h>
68#include <4xx_i2c.h>
69#include <miiphy.h>
70#include "../common/common_util.h"
71#include <i2c.h>
72#include <rtc.h>
73
74DECLARE_GLOBAL_DATA_PTR;
75
76#undef SDRAM_DEBUG
77#define ENABLE_ECC
78#define FALSE 0
79#define TRUE 1
80
81
82#ifndef __ldiv_t_defined
83typedef struct {
84 long int quot;
85 long int rem;
86} ldiv_t;
87extern ldiv_t ldiv (long int __numer, long int __denom);
88# define __ldiv_t_defined 1
89#endif
90
91
92#define PLD_PART_REG PER_PLD_ADDR + 0
93#define PLD_VERS_REG PER_PLD_ADDR + 1
94#define PLD_BOARD_CFG_REG PER_PLD_ADDR + 2
95#define PLD_IRQ_REG PER_PLD_ADDR + 3
96#define PLD_COM_MODE_REG PER_PLD_ADDR + 4
97#define PLD_EXT_CONF_REG PER_PLD_ADDR + 5
98
99#define MEGA_BYTE (1024*1024)
100
101typedef struct {
102 unsigned char boardtype;
103 unsigned char cal;
104 unsigned char trp;
105 unsigned char trcd;
106 unsigned char tras;
107 unsigned char tctp;
108 unsigned char am;
109 unsigned char sz;
110 unsigned char ecc;
111} sdram_t;
112#if defined(CONFIG_MIP405T)
113const sdram_t sdram_table[] = {
114 { 0x0F,
115 3,
116 3,
117 3,
118 6,
119 4,
120 2,
121 3,
122 0},
123 { 0xff,
124 0xff,
125 0xff,
126 0xff,
127 0xff,
128 0xff,
129 0xff,
130 0xff }
131};
132#else
133const sdram_t sdram_table[] = {
134 { 0x0f,
135 3,
136 3,
137 3,
138 6,
139 4,
140 3,
141 5,
142 1},
143 { 0x07,
144 3,
145 3,
146 3,
147 6,
148 4,
149 2,
150 4,
151 1},
152 { 0x03,
153 3,
154 3,
155 3,
156 6,
157 4,
158 3,
159 5,
160 1},
161 { 0x1f,
162 3,
163 3,
164 3,
165 6,
166 4,
167 3,
168 5,
169 1},
170 { 0x2f,
171 3,
172 3,
173 3,
174 6,
175 4,
176 3,
177 5,
178 1},
179 { 0xff,
180 0xff,
181 0xff,
182 0xff,
183 0xff,
184 0xff,
185 0xff,
186 0xff }
187};
188#endif
189void SDRAM_err (const char *s)
190{
191#ifndef SDRAM_DEBUG
192 (void) get_clocks ();
193 gd->baudrate = 9600;
194 serial_init ();
195#endif
196 serial_puts ("\n");
197 serial_puts (s);
198 serial_puts ("\n enable SDRAM_DEBUG for more info\n");
199 for (;;);
200}
201
202
203unsigned char get_board_revcfg (void)
204{
205 out8 (PER_BOARD_ADDR, 0);
206 return (in8 (PER_BOARD_ADDR));
207}
208
209
210#ifdef SDRAM_DEBUG
211
212void write_hex (unsigned char i)
213{
214 char cc;
215
216 cc = i >> 4;
217 cc &= 0xf;
218 if (cc > 9)
219 serial_putc (cc + 55);
220 else
221 serial_putc (cc + 48);
222 cc = i & 0xf;
223 if (cc > 9)
224 serial_putc (cc + 55);
225 else
226 serial_putc (cc + 48);
227}
228
229void write_4hex (unsigned long val)
230{
231 write_hex ((unsigned char) (val >> 24));
232 write_hex ((unsigned char) (val >> 16));
233 write_hex ((unsigned char) (val >> 8));
234 write_hex ((unsigned char) val);
235}
236
237#endif
238
239
240int init_sdram (void)
241{
242 unsigned long tmp, baseaddr;
243 unsigned short i;
244 unsigned char trp_clocks,
245 trcd_clocks,
246 tras_clocks,
247 trc_clocks,
248 tctp_clocks;
249 unsigned char cal_val;
250 unsigned char bc;
251 unsigned long sdram_tim, sdram_bank;
252
253
254 (void) get_clocks ();
255 gd->baudrate = 9600;
256 serial_init ();
257
258 mtdcr (ebccfga, pb7ap);
259 mtdcr (ebccfgd, PLD_AP);
260 mtdcr (ebccfga, pb7cr);
261 mtdcr (ebccfgd, PLD_CR);
262
263
264 mtdcr (ebccfga, pb5ap);
265 mtdcr (ebccfgd, BOARD_AP);
266 mtdcr (ebccfga, pb5cr);
267 mtdcr (ebccfgd, BOARD_CR);
268#ifdef SDRAM_DEBUG
269
270 serial_puts ("\nPLD Part 0x");
271 bc = in8 (PLD_PART_REG);
272 write_hex (bc);
273 serial_puts ("\nPLD Vers 0x");
274 bc = in8 (PLD_VERS_REG);
275 write_hex (bc);
276 serial_puts ("\nBoard Rev 0x");
277 bc = in8 (PLD_BOARD_CFG_REG);
278 write_hex (bc);
279 serial_puts ("\n");
280#endif
281
282 bc = in8 (PLD_PART_REG);
283#if defined(CONFIG_MIP405T)
284 if((bc & 0x80)==0)
285 SDRAM_err ("U-Boot configured for a MIP405T not for a MIP405!!!\n");
286#else
287 if((bc & 0x80)==0x80)
288 SDRAM_err ("U-Boot configured for a MIP405 not for a MIP405T!!!\n");
289#endif
290
291 mtdcr (ebccfga, pb0cr);
292 tmp = mfdcr (ebccfgd);
293 if ((tmp & 0x00002000) == 0) {
294
295 mtdcr (ebccfga, pb1ap);
296 mtdcr (ebccfgd, FLASH_AP);
297 mtdcr (ebccfga, pb1cr);
298 mtdcr (ebccfgd, FLASH_CR);
299 } else {
300
301 mtdcr (ebccfga, pb1ap);
302 mtdcr (ebccfgd, MPS_AP);
303 mtdcr (ebccfga, pb1cr);
304 mtdcr (ebccfgd, MPS_CR);
305 }
306
307 mtdcr (ebccfga, pb2ap);
308 mtdcr (ebccfgd, UART0_AP);
309 mtdcr (ebccfga, pb2cr);
310 mtdcr (ebccfgd, UART0_CR);
311 mtdcr (ebccfga, pb3ap);
312 mtdcr (ebccfgd, UART1_AP);
313 mtdcr (ebccfga, pb3cr);
314 mtdcr (ebccfgd, UART1_CR);
315 bc = in8 (PLD_BOARD_CFG_REG);
316#ifdef SDRAM_DEBUG
317 serial_puts ("\nstart SDRAM Setup\n");
318 serial_puts ("\nBoard Rev: ");
319 write_hex (bc);
320 serial_puts ("\n");
321#endif
322 i = 0;
323 baseaddr = CONFIG_SYS_SDRAM_BASE;
324 while (sdram_table[i].sz != 0xff) {
325 if (sdram_table[i].boardtype == bc)
326 break;
327 i++;
328 }
329 if (sdram_table[i].boardtype != bc)
330 SDRAM_err ("No SDRAM table found for this board!!!\n");
331#ifdef SDRAM_DEBUG
332 serial_puts (" found table ");
333 write_hex (i);
334 serial_puts (" \n");
335#endif
336
337
338
339 if (sdram_table[i].ecc)
340 serial_puts ("\nInitializing SDRAM, Please stand by");
341 cal_val = sdram_table[i].cal - 1;
342 trp_clocks = sdram_table[i].trp;
343 trcd_clocks = sdram_table[i].trcd;
344 tras_clocks = sdram_table[i].tras;
345
346 tctp_clocks = sdram_table[i].tctp;
347
348 trc_clocks = trp_clocks + tras_clocks;
349
350 mtdcr (memcfga, mem_sdtr1);
351 sdram_tim = mfdcr (memcfgd) & ~0x018FC01F;
352
353 sdram_tim |= ((unsigned long) (cal_val)) << 23;
354
355 sdram_tim |= ((unsigned long) (trp_clocks - 1)) << 18;
356
357 sdram_tim |=
358 ((unsigned long) (trc_clocks - trp_clocks -
359 trcd_clocks)) << 16;
360
361 sdram_tim |= ((unsigned long) 0x01) << 14;
362
363 sdram_tim |= ((unsigned long) (trc_clocks - 4)) << 2;
364
365 sdram_tim |= ((unsigned long) (trcd_clocks - 1)) << 0;
366
367 tmp = ((unsigned long) (sdram_table[i].am - 1) << 13);
368
369 tmp |= ((unsigned long) sdram_table[i].sz << 17);
370
371 mtdcr (memcfga, mem_mb0cf);
372 sdram_bank = mfdcr (memcfgd) & ~0xFFCEE001;
373 sdram_bank |= (baseaddr | tmp | 0x01);
374
375#ifdef SDRAM_DEBUG
376 serial_puts ("sdtr: ");
377 write_4hex (sdram_tim);
378 serial_puts ("\n");
379#endif
380
381
382 mtdcr (memcfga, mem_sdtr1);
383 mtdcr (memcfgd, sdram_tim);
384
385#ifdef SDRAM_DEBUG
386 serial_puts ("mb0cf: ");
387 write_4hex (sdram_bank);
388 serial_puts ("\n");
389#endif
390
391
392 mtdcr (memcfga, mem_mb0cf);
393 mtdcr (memcfgd, sdram_bank);
394
395 if (get_bus_freq (tmp) > 110000000) {
396
397 mtdcr (memcfga, mem_rtr);
398 tmp = mfdcr (memcfgd) & ~0x3FF80000;
399 tmp |= 0x07F00000;
400 } else {
401
402 mtdcr (memcfga, mem_rtr);
403 tmp = mfdcr (memcfgd) & ~0x3FF80000;
404 tmp |= 0x05F00000;
405 }
406
407 mtdcr (memcfga, mem_rtr);
408 mtdcr (memcfgd, tmp);
409
410#if defined(ENABLE_ECC) && !defined(CONFIG_BOOT_PCI)
411 if (sdram_table[i].ecc) {
412
413 unsigned long *p;
414#ifdef SDRAM_DEBUG
415 serial_puts ("disable ECC.. ");
416#endif
417 mtdcr (memcfga, mem_ecccf);
418 tmp = mfdcr (memcfgd);
419 tmp &= 0xff0fffff;
420 mtdcr (memcfga, mem_ecccf);
421
422#ifdef SDRAM_DEBUG
423 serial_puts ("setup SDRAM Controller.. ");
424#endif
425 mtdcr (memcfgd, tmp);
426 mtdcr (memcfga, mem_mcopt1);
427 tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x90800000;
428 mtdcr (memcfga, mem_mcopt1);
429 mtdcr (memcfgd, tmp);
430 udelay (600);
431#ifdef SDRAM_DEBUG
432 serial_puts ("fill the memory..\n");
433#endif
434 serial_puts (".");
435
436 tmp = ((4 * MEGA_BYTE) << sdram_table[i].sz);
437 p = (unsigned long) 0;
438 while ((unsigned long) p < tmp) {
439 *p++ = 0L;
440 if (!((unsigned long) p % 0x00800000))
441 serial_puts (".");
442 }
443
444 serial_puts (".");
445#ifdef SDRAM_DEBUG
446 serial_puts ("enable ECC\n");
447#endif
448 udelay (400);
449 mtdcr (memcfga, mem_ecccf);
450 tmp = mfdcr (memcfgd);
451 tmp |= 0x00800000;
452 mtdcr (memcfgd, tmp);
453 udelay (400);
454 } else
455#endif
456 {
457
458 mtdcr (memcfga, mem_mcopt1);
459 tmp = (mfdcr (memcfgd) & ~0xFFE00000) | 0x80C00000;
460 mtdcr (memcfga, mem_mcopt1);
461 mtdcr (memcfgd, tmp);
462 udelay (400);
463 }
464 serial_puts ("\n");
465 return (0);
466}
467
468int board_early_init_f (void)
469{
470 init_sdram ();
471
472
473
474
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476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491 mtdcr (uicsr, 0xFFFFFFFF);
492 mtdcr (uicer, 0x00000000);
493 mtdcr (uiccr, 0x00000000);
494 mtdcr (uicpr, 0xFFFFFF80);
495 mtdcr (uictr, 0x10000000);
496 mtdcr (uicvcr, 0x00000001);
497 mtdcr (uicsr, 0xFFFFFFFF);
498 return 0;
499}
500
501
502
503
504
505
506unsigned short get_pld_parvers (void)
507{
508 unsigned short result;
509 unsigned char rc;
510
511 rc = in8 (PLD_PART_REG);
512 result = (unsigned short) rc << 8;
513 rc = in8 (PLD_VERS_REG);
514 result |= rc;
515 return result;
516}
517
518
519void user_led0 (unsigned char on)
520{
521 if (on)
522 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x4));
523 else
524 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfb));
525}
526
527
528void ide_set_reset (int idereset)
529{
530
531 if (idereset)
532 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) | 0x1));
533 else {
534 udelay (10000);
535 out8 (PLD_COM_MODE_REG, (in8 (PLD_COM_MODE_REG) & 0xfe));
536 }
537}
538
539
540
541
542void get_pcbrev_var(unsigned char *pcbrev, unsigned char *var)
543{
544#if !defined(CONFIG_MIP405T)
545 unsigned char bc,rc,tmp;
546 int i;
547
548 bc = in8 (PLD_BOARD_CFG_REG);
549 tmp = ~bc;
550 tmp &= 0xf;
551 rc = 0;
552 for (i = 0; i < 4; i++) {
553 rc <<= 1;
554 rc += (tmp & 0x1);
555 tmp >>= 1;
556 }
557 rc++;
558 if(( (((bc>>4) & 0xf)==0x2)
559 || (((bc>>4) & 0xf)==0x1))
560 && (rc==0x1))
561 rc=3;
562 *pcbrev=(bc >> 4) & 0xf;
563 *var=rc;
564#else
565 unsigned char bc;
566 bc = in8 (PLD_BOARD_CFG_REG);
567 *pcbrev=(bc >> 4) & 0xf;
568 *var=16-(bc & 0xf);
569#endif
570}
571
572
573
574
575
576#if !defined(CONFIG_MIP405T)
577#define BOARD_NAME "MIP405"
578#else
579#define BOARD_NAME "MIP405T"
580#endif
581
582int checkboard (void)
583{
584 char s[50];
585 unsigned char bc, var;
586 int i;
587 backup_t *b = (backup_t *) s;
588
589 puts ("Board: ");
590 get_pcbrev_var(&bc,&var);
591 i = getenv_r ("serial#", (char *)s, 32);
592 if ((i == 0) || strncmp ((char *)s, BOARD_NAME,sizeof(BOARD_NAME))) {
593 get_backup_values (b);
594 if (strncmp (b->signature, "MPL\0", 4) != 0) {
595 puts ("### No HW ID - assuming " BOARD_NAME);
596 printf ("-%d Rev %c", var, 'A' + bc);
597 } else {
598 b->serial_name[sizeof(BOARD_NAME)-1] = 0;
599 printf ("%s-%d Rev %c SN: %s", b->serial_name, var,
600 'A' + bc, &b->serial_name[sizeof(BOARD_NAME)]);
601 }
602 } else {
603 s[sizeof(BOARD_NAME)-1] = 0;
604 printf ("%s-%d Rev %c SN: %s", s, var,'A' + bc,
605 &s[sizeof(BOARD_NAME)]);
606 }
607 bc = in8 (PLD_EXT_CONF_REG);
608 printf (" Boot Config: 0x%x\n", bc);
609 return (0);
610}
611
612
613
614
615
616
617
618
619
620
621static int test_dram (unsigned long ramsize);
622
623phys_size_t initdram (int board_type)
624{
625
626 unsigned long bank_reg[4], tmp, bank_size;
627 int i, ds;
628 unsigned long TotalSize;
629
630 ds = 0;
631
632
633 mtdcr (memcfga, mem_mb0cf);
634 bank_reg[0] = mfdcr (memcfgd);
635 mtdcr (memcfga, mem_mb1cf);
636 bank_reg[1] = mfdcr (memcfgd);
637 mtdcr (memcfga, mem_mb2cf);
638 bank_reg[2] = mfdcr (memcfgd);
639 mtdcr (memcfga, mem_mb3cf);
640 bank_reg[3] = mfdcr (memcfgd);
641 TotalSize = 0;
642 for (i = 0; i < 4; i++) {
643 if ((bank_reg[i] & 0x1) == 0x1) {
644 tmp = (bank_reg[i] >> 17) & 0x7;
645 bank_size = 4 << tmp;
646 TotalSize += bank_size;
647 } else
648 ds = 1;
649 }
650 mtdcr (memcfga, mem_ecccf);
651 tmp = mfdcr (memcfgd);
652
653 if (!tmp)
654 printf ("No ");
655 printf ("ECC ");
656
657 test_dram (TotalSize * MEGA_BYTE);
658 return (TotalSize * MEGA_BYTE);
659}
660
661
662
663
664static int test_dram (unsigned long ramsize)
665{
666#ifdef SDRAM_DEBUG
667 mem_test (0L, ramsize, 1);
668#endif
669
670 return (1);
671}
672
673
674static unsigned long start;
675static struct rtc_time tm;
676extern flash_info_t flash_info[];
677
678int misc_init_r (void)
679{
680
681 gd->bd->bi_flashstart=0-flash_info[0].size;
682 gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
683 gd->bd->bi_flashoffset=0;
684
685
686 rtc_get (&tm);
687 start=get_timer(0);
688
689 if (mfdcr(strap) & PSR_ROM_LOC)
690 mtspr(ccr0, (mfspr(ccr0) & ~0x80));
691
692 return (0);
693}
694
695
696void print_mip405_rev (void)
697{
698 unsigned char part, vers, pcbrev, var;
699
700 get_pcbrev_var(&pcbrev,&var);
701 part = in8 (PLD_PART_REG);
702 vers = in8 (PLD_VERS_REG);
703 printf ("Rev: " BOARD_NAME "-%d Rev %c PLD %d Vers %d\n",
704 var, pcbrev + 'A', part & 0x7F, vers);
705}
706
707
708#ifdef CONFIG_POST
709
710
711
712
713int post_hotkeys_pressed(void)
714{
715 return 0;
716}
717#endif
718
719extern void mem_test_reloc(void);
720extern int mk_date (char *, struct rtc_time *);
721
722int last_stage_init (void)
723{
724 unsigned long stop;
725 struct rtc_time newtm;
726 char *s;
727 mem_test_reloc();
728
729 if (miiphy_write("ppc_4xx_eth0", 0x1, 0x14, 0x2402) != 0) {
730 printf ("Error writing to the PHY\n");
731 }
732
733
734 if (miiphy_write("ppc_4xx_eth0", 0x1, 0x4, 0x01E1) != 0) {
735 printf ("Error writing to the PHY\n");
736 }
737 print_mip405_rev ();
738 show_stdio_dev ();
739 check_env ();
740
741 stop=get_timer(start);
742 while(stop<1200) {
743 udelay(1000);
744 stop=get_timer(start);
745 }
746 rtc_get (&newtm);
747 if(tm.tm_sec==newtm.tm_sec) {
748 s=getenv("defaultdate");
749 if(!s)
750 mk_date ("010112001970", &newtm);
751 else
752 if(mk_date (s, &newtm)!=0) {
753 printf("RTC: Bad date format in defaultdate\n");
754 return 0;
755 }
756 rtc_reset ();
757 rtc_set(&newtm);
758 }
759 return 0;
760}
761
762
763
764
765
766int overwrite_console (void)
767{
768 return ((in8 (PLD_EXT_CONF_REG) & 0x1)==0);
769}
770
771
772
773
774
775void print_mip405_info (void)
776{
777 unsigned char part, vers, cfg, irq_reg, com_mode, ext;
778
779 part = in8 (PLD_PART_REG);
780 vers = in8 (PLD_VERS_REG);
781 cfg = in8 (PLD_BOARD_CFG_REG);
782 irq_reg = in8 (PLD_IRQ_REG);
783 com_mode = in8 (PLD_COM_MODE_REG);
784 ext = in8 (PLD_EXT_CONF_REG);
785
786 printf ("PLD Part %d version %d\n", part & 0x7F, vers);
787 printf ("Board Revision %c\n", ((cfg >> 4) & 0xf) + 'A');
788 printf ("Population Options %d %d %d %d\n", (cfg) & 0x1,
789 (cfg >> 1) & 0x1, (cfg >> 2) & 0x1, (cfg >> 3) & 0x1);
790 printf ("User LED %s\n", (com_mode & 0x4) ? "on" : "off");
791 printf ("UART Clocks %d\n", (com_mode >> 4) & 0x3);
792#if !defined(CONFIG_MIP405T)
793 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
794 (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
795 (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
796 (ext >> 6) & 0x1, (ext >> 7) & 0x1);
797 printf ("SER1 uses handshakes %s\n",
798 (ext & 0x80) ? "DTR/DSR" : "RTS/CTS");
799#else
800 printf ("User Config Switch %d %d %d %d %d %d %d %d\n",
801 (ext) & 0x1, (ext >> 1) & 0x1, (ext >> 2) & 0x1,
802 (ext >> 3) & 0x1, (ext >> 4) & 0x1, (ext >> 5) & 0x1,
803 (ext >> 6) & 0x1,(ext >> 7) & 0x1);
804#endif
805 printf ("IDE Reset %s\n", (ext & 0x01) ? "asserted" : "not asserted");
806 printf ("IRQs:\n");
807 printf (" PIIX INTR: %s\n", (irq_reg & 0x80) ? "inactive" : "active");
808#if !defined(CONFIG_MIP405T)
809 printf (" UART0 IRQ: %s\n", (irq_reg & 0x40) ? "inactive" : "active");
810 printf (" UART1 IRQ: %s\n", (irq_reg & 0x20) ? "inactive" : "active");
811#endif
812 printf (" PIIX SMI: %s\n", (irq_reg & 0x10) ? "inactive" : "active");
813 printf (" PIIX INIT: %s\n", (irq_reg & 0x8) ? "inactive" : "active");
814 printf (" PIIX NMI: %s\n", (irq_reg & 0x4) ? "inactive" : "active");
815}
816