1/* 2 * Copyright (C) 2003 Travis B. Sawyer <travis.sawyer@sandburst.com> 3 * 4 * See file CREDITS for list of people who contributed to this 5 * project. 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 20 * MA 02111-1307 USA 21 */ 22 23 24#include <common.h> 25#include <asm/processor.h> 26#include <spd_sdram.h> 27#include <i2c.h> 28#include <net.h> 29 30DECLARE_GLOBAL_DATA_PTR; 31 32#define BOOT_SMALL_FLASH 32 /* 00100000 */ 33#define FLASH_ONBD_N 2 /* 00000010 */ 34#define FLASH_SRAM_SEL 1 /* 00000001 */ 35 36long int fixed_sdram (void); 37 38int board_early_init_f(void) 39{ 40 unsigned long sdrreg; 41 /* TBS: Setup the GPIO access for the user LEDs */ 42 mfsdr(sdr_pfc0, sdrreg); 43 mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00); 44 out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3)); 45 LED0_OFF(); 46 LED1_OFF(); 47 LED2_OFF(); 48 LED3_OFF(); 49 50 /*-------------------------------------------------------------------- 51 * Setup the external bus controller/chip selects 52 *-------------------------------------------------------------------*/ 53 54 /* set the bus controller */ 55 mtebc (pb0ap, 0x04055200); /* FLASH/SRAM */ 56 mtebc (pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ 57 mtebc (pb1ap, 0x04055200); /* FLASH/SRAM */ 58 mtebc (pb1cr, 0xfe098000); /* BAS=0xff8 16MB R/W 8-bit */ 59 60 /*-------------------------------------------------------------------- 61 * Setup the interrupt controller polarities, triggers, etc. 62 *-------------------------------------------------------------------*/ 63 /* 64 * Because of the interrupt handling rework to handle 440GX interrupts 65 * with the common code, we needed to change names of the UIC registers. 66 * Here the new relationship: 67 * 68 * U-Boot name 440GX name 69 * ----------------------- 70 * UIC0 UICB0 71 * UIC1 UIC0 72 * UIC2 UIC1 73 * UIC3 UIC2 74 */ 75 mtdcr (uic1sr, 0xffffffff); /* clear all */ 76 mtdcr (uic1er, 0x00000000); /* disable all */ 77 mtdcr (uic1cr, 0x00000003); /* SMI & UIC1 crit are critical */ 78 mtdcr (uic1pr, 0xfffffe00); /* per ref-board manual */ 79 mtdcr (uic1tr, 0x01c00000); /* per ref-board manual */ 80 mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ 81 mtdcr (uic1sr, 0xffffffff); /* clear all */ 82 83 mtdcr (uic2sr, 0xffffffff); /* clear all */ 84 mtdcr (uic2er, 0x00000000); /* disable all */ 85 mtdcr (uic2cr, 0x00000000); /* all non-critical */ 86 mtdcr (uic2pr, 0xffffc0ff); /* per ref-board manual */ 87 mtdcr (uic2tr, 0x00ff8000); /* per ref-board manual */ 88 mtdcr (uic2vr, 0x00000001); /* int31 highest, base=0x000 */ 89 mtdcr (uic2sr, 0xffffffff); /* clear all */ 90 91 mtdcr (uic3sr, 0xffffffff); /* clear all */ 92 mtdcr (uic3er, 0x00000000); /* disable all */ 93 mtdcr (uic3cr, 0x00000000); /* all non-critical */ 94 mtdcr (uic3pr, 0xffffffff); /* per ref-board manual */ 95 mtdcr (uic3tr, 0x00ff8c0f); /* per ref-board manual */ 96 mtdcr (uic3vr, 0x00000001); /* int31 highest, base=0x000 */ 97 mtdcr (uic3sr, 0xffffffff); /* clear all */ 98 99 mtdcr (uic0sr, 0xfc000000); /* clear all */ 100 mtdcr (uic0er, 0x00000000); /* disable all */ 101 mtdcr (uic0cr, 0x00000000); /* all non-critical */ 102 mtdcr (uic0pr, 0xfc000000); /* */ 103 mtdcr (uic0tr, 0x00000000); /* */ 104 mtdcr (uic0vr, 0x00000001); /* */ 105 106 LED0_ON(); 107 108 109 return 0; 110} 111 112int checkboard (void) 113{ 114 printf ("Board: XES XPedite1000 440GX\n"); 115 116 return (0); 117} 118 119 120phys_size_t initdram (int board_type) 121{ 122 long dram_size = 0; 123 124#if defined(CONFIG_SPD_EEPROM) 125 dram_size = spd_sdram (); 126#else 127 dram_size = fixed_sdram (); 128#endif 129 return dram_size; 130} 131 132 133#if defined(CONFIG_SYS_DRAM_TEST) 134int testdram (void) 135{ 136 uint *pstart = (uint *) 0x00000000; 137 uint *pend = (uint *) 0x08000000; 138 uint *p; 139 140 for (p = pstart; p < pend; p++) 141 *p = 0xaaaaaaaa; 142 143 for (p = pstart; p < pend; p++) { 144 if (*p != 0xaaaaaaaa) { 145 printf ("SDRAM test fails at: %08x\n", (uint) p); 146 return 1; 147 } 148 } 149 150 for (p = pstart; p < pend; p++) 151 *p = 0x55555555; 152 153 for (p = pstart; p < pend; p++) { 154 if (*p != 0x55555555) { 155 printf ("SDRAM test fails at: %08x\n", (uint) p); 156 return 1; 157 } 158 } 159 return 0; 160} 161#endif 162 163#if !defined(CONFIG_SPD_EEPROM) 164/************************************************************************* 165 * fixed sdram init -- doesn't use serial presence detect. 166 * 167 * Assumes: 128 MB, non-ECC, non-registered 168 * PLB @ 133 MHz 169 * 170 ************************************************************************/ 171long int fixed_sdram (void) 172{ 173 uint reg; 174 175 /*-------------------------------------------------------------------- 176 * Setup some default 177 *------------------------------------------------------------------*/ 178 mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ 179 mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ 180 mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ 181 mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ 182 mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ 183 184 /*-------------------------------------------------------------------- 185 * Setup for board-specific specific mem 186 *------------------------------------------------------------------*/ 187 /* 188 * Following for CAS Latency = 2.5 @ 133 MHz PLB 189 */ 190 mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ 191 mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ 192 /* RA=10 RD=3 */ 193 mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ 194 mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ 195 mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ 196 udelay (400); /* Delay 200 usecs (min) */ 197 198 /*-------------------------------------------------------------------- 199 * Enable the controller, then wait for DCEN to complete 200 *------------------------------------------------------------------*/ 201 mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ 202 for (;;) { 203 mfsdram (mem_mcsts, reg); 204 if (reg & 0x80000000) 205 break; 206 } 207 208 return (128 * 1024 * 1024); /* 128 MB */ 209} 210#endif /* !defined(CONFIG_SPD_EEPROM) */ 211 212 213/************************************************************************* 214 * pci_pre_init 215 * 216 * This routine is called just prior to registering the hose and gives 217 * the board the opportunity to check things. Returning a value of zero 218 * indicates that things are bad & PCI initialization should be aborted. 219 * 220 * Different boards may wish to customize the pci controller structure 221 * (add regions, override default access routines, etc) or perform 222 * certain pre-initialization actions. 223 * 224 ************************************************************************/ 225#if defined(CONFIG_PCI) 226int pci_pre_init(struct pci_controller * hose ) 227{ 228 unsigned long strap; 229 /* See if we're supposed to setup the pci */ 230 mfsdr(sdr_sdstp1, strap); 231 if ((strap & 0x00010000) == 0) { 232 return (0); 233 } 234 235#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV) 236 /* Setup System Device Register PCIX0_XCR */ 237 mfsdr(sdr_xcr, strap); 238 strap &= 0x0f000000; 239 mtsdr(sdr_xcr, strap); 240#endif 241 return 1; 242} 243#endif /* defined(CONFIG_PCI) */ 244 245/************************************************************************* 246 * pci_target_init 247 * 248 * The bootstrap configuration provides default settings for the pci 249 * inbound map (PIM). But the bootstrap config choices are limited and 250 * may not be sufficient for a given board. 251 * 252 ************************************************************************/ 253#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) 254void pci_target_init(struct pci_controller * hose ) 255{ 256 /*--------------------------------------------------------------------------+ 257 * Disable everything 258 *--------------------------------------------------------------------------*/ 259 out32r( PCIX0_PIM0SA, 0 ); /* disable */ 260 out32r( PCIX0_PIM1SA, 0 ); /* disable */ 261 out32r( PCIX0_PIM2SA, 0 ); /* disable */ 262 out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ 263 264 /*--------------------------------------------------------------------------+ 265 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping 266 * options to not support sizes such as 128/256 MB. 267 *--------------------------------------------------------------------------*/ 268 out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE ); 269 out32r( PCIX0_PIM0LAH, 0 ); 270 out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); 271 272 out32r( PCIX0_BAR0, 0 ); 273 274 /*--------------------------------------------------------------------------+ 275 * Program the board's subsystem id/vendor id 276 *--------------------------------------------------------------------------*/ 277 out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); 278 out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID ); 279 280 out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); 281} 282#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */ 283 284 285/************************************************************************* 286 * is_pci_host 287 * 288 * This routine is called to determine if a pci scan should be 289 * performed. With various hardware environments (especially cPCI and 290 * PPMC) it's insufficient to depend on the state of the arbiter enable 291 * bit in the strap register, or generic host/adapter assumptions. 292 * 293 * Rather than hard-code a bad assumption in the general 440 code, the 294 * 440 pci code requires the board to decide at runtime. 295 * 296 * Return 0 for adapter mode, non-zero for host (monarch) mode. 297 * 298 * 299 ************************************************************************/ 300#if defined(CONFIG_PCI) 301int is_pci_host(struct pci_controller *hose) 302{ 303 return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0); 304} 305#endif /* defined(CONFIG_PCI) */ 306 307#ifdef CONFIG_POST 308/* 309 * Returns 1 if keys pressed to start the power-on long-running tests 310 * Called from board_init_f(). 311 */ 312int post_hotkeys_pressed(void) 313{ 314 315 return (ctrlc()); 316} 317 318void post_word_store (ulong a) 319{ 320 volatile ulong *save_addr = 321 (volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR); 322 323 *save_addr = a; 324} 325 326ulong post_word_load (void) 327{ 328 volatile ulong *save_addr = 329 (volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR); 330 331 return *save_addr; 332} 333#endif 334 335/*----------------------------------------------------------------------------- 336 * board_get_enetaddr -- Read the MAC Addresses in the I2C EEPROM 337 *----------------------------------------------------------------------------- 338 */ 339static int read_i2c; 340static void board_get_enetaddr(uchar *enet) 341{ 342 int i; 343 unsigned char buff[0x100], *cp; 344 345 if (read_i2c) 346 return; 347 348 /* Initialize I2C */ 349 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 350 351 /* Read 256 bytes in EEPROM */ 352 i2c_read (0x50, 0, 1, buff, 0x100); 353 354 cp = &buff[0xF4]; 355 for (i = 0; i < 6; i++,cp++) 356 enet[i] = *cp; 357 358 printf("MAC address = %pM\n", enet); 359 read_i2c = 1; 360} 361 362int misc_init_r(void) 363{ 364 uchar enetaddr[6], i2c_enetaddr[6]; 365 366 if (!eth_getenv_enetaddr("ethaddr", enetaddr)) { 367 board_get_enetaddr(i2c_enetaddr); 368 eth_setenv_enetaddr("ethaddr", i2c_enetaddr); 369 } 370 371#ifdef CONFIG_HAS_ETH1 372 if (!eth_getenv_enetaddr("eth1addr", enetaddr)) { 373 board_get_enetaddr(i2c_enetaddr); 374 eth_setenv_enetaddr("eth1addr", i2c_enetaddr); 375 } 376#endif 377 378#ifdef CONFIG_HAS_ETH2 379 if (!eth_getenv_enetaddr("eth2addr", enetaddr)) { 380 board_get_enetaddr(i2c_enetaddr); 381 eth_setenv_enetaddr("eth2addr", i2c_enetaddr); 382 } 383#endif 384 385#ifdef CONFIG_HAS_ETH3 386 if (!eth_getenv_enetaddr("eth3addr", enetaddr)) { 387 board_get_enetaddr(i2c_enetaddr); 388 eth_setenv_enetaddr("eth3addr", i2c_enetaddr); 389 } 390#endif 391 392 return 0; 393} 394