LXR uboot/cpu/mcf5227x/cpu

   1/*
   2 *
   3 * (C) Copyright 2000-2003
   4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5 *
   6 * (C) Copyright 2004-2007 Freescale Semiconductor, Inc.
   7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   8 *
   9 * See file CREDITS for list of people who contributed to this
  10 * project.
  11 *
  12 * This program is free software; you can redistribute it and/or
  13 * modify it under the terms of the GNU General Public License as
  14 * published by the Free Software Foundation; either version 2 of
  15 * the License, or (at your option) any later version.
  16 *
  17 * This program is distributed in the hope that it will be useful,
  18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 * GNU General Public License for more details.
  21 *
  22 * You should have received a copy of the GNU General Public License
  23 * along with this program; if not, write to the Free Software
  24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25 * MA 02111-1307 USA
  26 */
  27
  28#include <common.h>
  29#include <watchdog.h>
  30
  31#include <asm/immap.h>
  32#include <asm/rtc.h>
  33
  34/*
  35 * Breath some life into the CPU...
  36 *
  37 * Set up the memory map,
  38 * initialize a bunch of registers,
  39 * initialize the UPM's
  40 */
  41void cpu_init_f(void)
  42{
  43        volatile scm1_t *scm1 = (scm1_t *) MMAP_SCM1;
  44        volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  45        volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
  46        volatile pll_t *pll = (volatile pll_t *)MMAP_PLL;
  47
  48#if !defined(CONFIG_CF_SBF)
  49        /* Workaround, must place before fbcs */
  50        pll->psr = 0x12;
  51
  52        scm1->mpr = 0x77777777;
  53        scm1->pacra = 0;
  54        scm1->pacrb = 0;
  55        scm1->pacrc = 0;
  56        scm1->pacrd = 0;
  57        scm1->pacre = 0;
  58        scm1->pacrf = 0;
  59        scm1->pacrg = 0;
  60        scm1->pacri = 0;
  61
  62#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) \
  63     && defined(CONFIG_SYS_CS0_CTRL))
  64        fbcs->csar0 = CONFIG_SYS_CS0_BASE;
  65        fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
  66        fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
  67#endif
  68#endif                          /* CONFIG_CF_SBF */
  69
  70#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) \
  71     && defined(CONFIG_SYS_CS1_CTRL))
  72        fbcs->csar1 = CONFIG_SYS_CS1_BASE;
  73        fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
  74        fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
  75#endif
  76
  77#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) \
  78     && defined(CONFIG_SYS_CS2_CTRL))
  79        fbcs->csar2 = CONFIG_SYS_CS2_BASE;
  80        fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
  81        fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
  82#endif
  83
  84#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) \
  85     && defined(CONFIG_SYS_CS3_CTRL))
  86        fbcs->csar3 = CONFIG_SYS_CS3_BASE;
  87        fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
  88        fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
  89#endif
  90
  91#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) \
  92     && defined(CONFIG_SYS_CS4_CTRL))
  93        fbcs->csar4 = CONFIG_SYS_CS4_BASE;
  94        fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
  95        fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
  96#endif
  97
  98#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) \
  99     && defined(CONFIG_SYS_CS5_CTRL))
 100        fbcs->csar5 = CONFIG_SYS_CS5_BASE;
 101        fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
 102        fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
 103#endif
 104
 105#ifdef CONFIG_FSL_I2C
 106        gpio->par_i2c = GPIO_PAR_I2C_SCL_SCL | GPIO_PAR_I2C_SDA_SDA;
 107#endif
 108
 109        icache_enable();
 110}
 111
 112/*
 113 * initialize higher level parts of CPU like timers
 114 */
 115int cpu_init_r(void)
 116{
 117#ifdef CONFIG_MCFRTC
 118        volatile rtc_t *rtc = (volatile rtc_t *)(CONFIG_SYS_MCFRTC_BASE);
 119        volatile rtcex_t *rtcex = (volatile rtcex_t *)&rtc->extended;
 120        u32 oscillator = CONFIG_SYS_RTC_OSCILLATOR;
 121
 122        rtcex->gocu = (CONFIG_SYS_RTC_OSCILLATOR >> 16) & 0xFFFF;
 123        rtcex->gocl = CONFIG_SYS_RTC_OSCILLATOR & 0xFFFF;
 124#endif
 125
 126        return (0);
 127}
 128
 129void uart_port_conf(void)
 130{
 131        volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 132
 133        /* Setup Ports: */
 134        switch (CONFIG_SYS_UART_PORT) {
 135        case 0:
 136                gpio->par_uart &=
 137                    (GPIO_PAR_UART_U0TXD_MASK & GPIO_PAR_UART_U0RXD_MASK);
 138                gpio->par_uart |=
 139                    (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD);
 140                break;
 141        case 1:
 142                gpio->par_uart &=
 143                    (GPIO_PAR_UART_U1TXD_MASK & GPIO_PAR_UART_U1RXD_MASK);
 144                gpio->par_uart |=
 145                    (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD);
 146                break;
 147        case 2:
 148                gpio->par_dspi &=
 149                    (GPIO_PAR_DSPI_SIN_MASK & GPIO_PAR_DSPI_SOUT_MASK);
 150                gpio->par_dspi =
 151                    (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD);
 152                break;
 153        }
 154}
 155