LXR uboot/cpu/mcf523x/cpu

   1/*
   2 *
   3 * (C) Copyright 2000-2003
   4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   5 *
   6 * (C) Copyright 2007 Freescale Semiconductor, Inc.
   7 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   8 *
   9 * See file CREDITS for list of people who contributed to this
  10 * project.
  11 *
  12 * This program is free software; you can redistribute it and/or
  13 * modify it under the terms of the GNU General Public License as
  14 * published by the Free Software Foundation; either version 2 of
  15 * the License, or (at your option) any later version.
  16 *
  17 * This program is distributed in the hope that it will be useful,
  18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20 * GNU General Public License for more details.
  21 *
  22 * You should have received a copy of the GNU General Public License
  23 * along with this program; if not, write to the Free Software
  24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25 * MA 02111-1307 USA
  26 */
  27
  28#include <common.h>
  29#include <watchdog.h>
  30#include <asm/immap.h>
  31
  32#if defined(CONFIG_CMD_NET)
  33#include <config.h>
  34#include <net.h>
  35#include <asm/fec.h>
  36#endif
  37
  38/*
  39 * Breath some life into the CPU...
  40 *
  41 * Set up the memory map,
  42 * initialize a bunch of registers,
  43 * initialize the UPM's
  44 */
  45void cpu_init_f(void)
  46{
  47        volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
  48        volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
  49        volatile wdog_t *wdog = (wdog_t *) MMAP_WDOG;
  50        volatile scm_t *scm = (scm_t *) MMAP_SCM;
  51
  52        /* watchdog is enabled by default - disable the watchdog */
  53#ifndef CONFIG_WATCHDOG
  54        wdog->cr = 0;
  55#endif
  56
  57        scm->rambar = (CONFIG_SYS_INIT_RAM_ADDR | SCM_RAMBAR_BDE);
  58
  59        /* Port configuration */
  60        gpio->par_cs = 0;
  61
  62#if (defined(CONFIG_SYS_CS0_BASE) && defined(CONFIG_SYS_CS0_MASK) && defined(CONFIG_SYS_CS0_CTRL))
  63        fbcs->csar0 = CONFIG_SYS_CS0_BASE;
  64        fbcs->cscr0 = CONFIG_SYS_CS0_CTRL;
  65        fbcs->csmr0 = CONFIG_SYS_CS0_MASK;
  66#endif
  67
  68#if (defined(CONFIG_SYS_CS1_BASE) && defined(CONFIG_SYS_CS1_MASK) && defined(CONFIG_SYS_CS1_CTRL))
  69        gpio->par_cs |= GPIO_PAR_CS_CS1;
  70        fbcs->csar1 = CONFIG_SYS_CS1_BASE;
  71        fbcs->cscr1 = CONFIG_SYS_CS1_CTRL;
  72        fbcs->csmr1 = CONFIG_SYS_CS1_MASK;
  73#endif
  74
  75#if (defined(CONFIG_SYS_CS2_BASE) && defined(CONFIG_SYS_CS2_MASK) && defined(CONFIG_SYS_CS2_CTRL))
  76        gpio->par_cs |= GPIO_PAR_CS_CS2;
  77        fbcs->csar2 = CONFIG_SYS_CS2_BASE;
  78        fbcs->cscr2 = CONFIG_SYS_CS2_CTRL;
  79        fbcs->csmr2 = CONFIG_SYS_CS2_MASK;
  80#endif
  81
  82#if (defined(CONFIG_SYS_CS3_BASE) && defined(CONFIG_SYS_CS3_MASK) && defined(CONFIG_SYS_CS3_CTRL))
  83        gpio->par_cs |= GPIO_PAR_CS_CS3;
  84        fbcs->csar3 = CONFIG_SYS_CS3_BASE;
  85        fbcs->cscr3 = CONFIG_SYS_CS3_CTRL;
  86        fbcs->csmr3 = CONFIG_SYS_CS3_MASK;
  87#endif
  88
  89#if (defined(CONFIG_SYS_CS4_BASE) && defined(CONFIG_SYS_CS4_MASK) && defined(CONFIG_SYS_CS4_CTRL))
  90        gpio->par_cs |= GPIO_PAR_CS_CS4;
  91        fbcs->csar4 = CONFIG_SYS_CS4_BASE;
  92        fbcs->cscr4 = CONFIG_SYS_CS4_CTRL;
  93        fbcs->csmr4 = CONFIG_SYS_CS4_MASK;
  94#endif
  95
  96#if (defined(CONFIG_SYS_CS5_BASE) && defined(CONFIG_SYS_CS5_MASK) && defined(CONFIG_SYS_CS5_CTRL))
  97        gpio->par_cs |= GPIO_PAR_CS_CS5;
  98        fbcs->csar5 = CONFIG_SYS_CS5_BASE;
  99        fbcs->cscr5 = CONFIG_SYS_CS5_CTRL;
 100        fbcs->csmr5 = CONFIG_SYS_CS5_MASK;
 101#endif
 102
 103#if (defined(CONFIG_SYS_CS6_BASE) && defined(CONFIG_SYS_CS6_MASK) && defined(CONFIG_SYS_CS6_CTRL))
 104        gpio->par_cs |= GPIO_PAR_CS_CS6;
 105        fbcs->csar6 = CONFIG_SYS_CS6_BASE;
 106        fbcs->cscr6 = CONFIG_SYS_CS6_CTRL;
 107        fbcs->csmr6 = CONFIG_SYS_CS6_MASK;
 108#endif
 109
 110#if (defined(CONFIG_SYS_CS7_BASE) && defined(CONFIG_SYS_CS7_MASK) && defined(CONFIG_SYS_CS7_CTRL))
 111        gpio->par_cs |= GPIO_PAR_CS_CS7;
 112        fbcs->csar7 = CONFIG_SYS_CS7_BASE;
 113        fbcs->cscr7 = CONFIG_SYS_CS7_CTRL;
 114        fbcs->csmr7 = CONFIG_SYS_CS7_MASK;
 115#endif
 116
 117#ifdef CONFIG_FSL_I2C
 118        CONFIG_SYS_I2C_PINMUX_REG &= CONFIG_SYS_I2C_PINMUX_CLR;
 119        CONFIG_SYS_I2C_PINMUX_REG |= CONFIG_SYS_I2C_PINMUX_SET;
 120#endif
 121
 122        icache_enable();
 123}
 124
 125/*
 126 * initialize higher level parts of CPU like timers
 127 */
 128int cpu_init_r(void)
 129{
 130        return (0);
 131}
 132
 133void uart_port_conf(void)
 134{
 135        volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 136
 137        /* Setup Ports: */
 138        switch (CONFIG_SYS_UART_PORT) {
 139        case 0:
 140                gpio->par_uart = (GPIO_PAR_UART_U0RXD | GPIO_PAR_UART_U0TXD);
 141                break;
 142        case 1:
 143                gpio->par_uart =
 144                        (GPIO_PAR_UART_U1RXD_U1RXD | GPIO_PAR_UART_U1TXD_U1TXD);
 145                break;
 146        case 2:
 147                gpio->par_timer = (GPIO_PAR_UART_U2RXD | GPIO_PAR_UART_U2TXD);
 148                break;
 149        }
 150}
 151
 152#if defined(CONFIG_CMD_NET)
 153int fecpin_setclear(struct eth_device *dev, int setclear)
 154{
 155        volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 156
 157        if (setclear) {
 158                gpio->par_feci2c |=
 159                    (GPIO_PAR_FECI2C_EMDC_FECEMDC | GPIO_PAR_FECI2C_EMDIO_FECEMDIO);
 160        } else {
 161                gpio->par_feci2c &=
 162                    ~(GPIO_PAR_FECI2C_EMDC_MASK | GPIO_PAR_FECI2C_EMDIO_MASK);
 163        }
 164
 165        return 0;
 166}
 167#endif
 168