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27#include <common.h>
28
29#include <command.h>
30#include <pci.h>
31#include <asm/processor.h>
32#include <asm/errno.h>
33#include <asm/io.h>
34#include <malloc.h>
35#include <scsi.h>
36#include <ata.h>
37#include <linux/ctype.h>
38#include <ahci.h>
39
40struct ahci_probe_ent *probe_ent = NULL;
41hd_driveid_t *ataid[AHCI_MAX_PORTS];
42
43#define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
44
45
46static inline u32 ahci_port_base(u32 base, u32 port)
47{
48 return base + 0x100 + (port * 0x80);
49}
50
51
52static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
53 unsigned int port_idx)
54{
55 base = ahci_port_base(base, port_idx);
56
57 port->cmd_addr = base;
58 port->scr_addr = base + PORT_SCR;
59}
60
61
62#define msleep(a) udelay(a * 1000)
63#define ssleep(a) msleep(a * 1000)
64
65static int waiting_for_cmd_completed(volatile u8 *offset,
66 int timeout_msec,
67 u32 sign)
68{
69 int i;
70 u32 status;
71
72 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
73 msleep(1);
74
75 return (i < timeout_msec) ? 0 : -1;
76}
77
78
79static int ahci_host_init(struct ahci_probe_ent *probe_ent)
80{
81 pci_dev_t pdev = probe_ent->dev;
82 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
83 u32 tmp, cap_save;
84 u16 tmp16;
85 int i, j;
86 volatile u8 *port_mmio;
87 unsigned short vendor;
88
89 cap_save = readl(mmio + HOST_CAP);
90 cap_save &= ((1 << 28) | (1 << 17));
91 cap_save |= (1 << 27);
92
93
94 tmp = readl(mmio + HOST_CTL);
95 if ((tmp & HOST_RESET) == 0)
96 writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
97
98
99
100
101 ssleep(1);
102
103 tmp = readl(mmio + HOST_CTL);
104 if (tmp & HOST_RESET) {
105 debug("controller reset failed (0x%x)\n", tmp);
106 return -1;
107 }
108
109 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
110 writel(cap_save, mmio + HOST_CAP);
111 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
112
113 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
114
115 if (vendor == PCI_VENDOR_ID_INTEL) {
116 u16 tmp16;
117 pci_read_config_word(pdev, 0x92, &tmp16);
118 tmp16 |= 0xf;
119 pci_write_config_word(pdev, 0x92, tmp16);
120 }
121
122 probe_ent->cap = readl(mmio + HOST_CAP);
123 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
124 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
125
126 debug("cap 0x%x port_map 0x%x n_ports %d\n",
127 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
128
129 for (i = 0; i < probe_ent->n_ports; i++) {
130 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
131 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
132 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
133
134
135 tmp = readl(port_mmio + PORT_CMD);
136 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
137 PORT_CMD_FIS_RX | PORT_CMD_START)) {
138 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
139 PORT_CMD_FIS_RX | PORT_CMD_START);
140 writel_with_flush(tmp, port_mmio + PORT_CMD);
141
142
143
144
145 msleep(500);
146 }
147
148 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
149
150 j = 0;
151 while (j < 100) {
152 msleep(10);
153 tmp = readl(port_mmio + PORT_SCR_STAT);
154 if ((tmp & 0xf) == 0x3)
155 break;
156 j++;
157 }
158
159 tmp = readl(port_mmio + PORT_SCR_ERR);
160 debug("PORT_SCR_ERR 0x%x\n", tmp);
161 writel(tmp, port_mmio + PORT_SCR_ERR);
162
163
164 tmp = readl(port_mmio + PORT_IRQ_STAT);
165 debug("PORT_IRQ_STAT 0x%x\n", tmp);
166 if (tmp)
167 writel(tmp, port_mmio + PORT_IRQ_STAT);
168
169 writel(1 << i, mmio + HOST_IRQ_STAT);
170
171
172 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
173
174
175 tmp = readl(port_mmio + PORT_SCR_STAT);
176 debug("Port %d status: 0x%x\n", i, tmp);
177 if ((tmp & 0xf) == 0x03)
178 probe_ent->link_port_map |= (0x01 << i);
179 }
180
181 tmp = readl(mmio + HOST_CTL);
182 debug("HOST_CTL 0x%x\n", tmp);
183 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
184 tmp = readl(mmio + HOST_CTL);
185 debug("HOST_CTL 0x%x\n", tmp);
186
187 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
188 tmp |= PCI_COMMAND_MASTER;
189 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
190
191 return 0;
192}
193
194
195static void ahci_print_info(struct ahci_probe_ent *probe_ent)
196{
197 pci_dev_t pdev = probe_ent->dev;
198 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
199 u32 vers, cap, impl, speed;
200 const char *speed_s;
201 u16 cc;
202 const char *scc_s;
203
204 vers = readl(mmio + HOST_VERSION);
205 cap = probe_ent->cap;
206 impl = probe_ent->port_map;
207
208 speed = (cap >> 20) & 0xf;
209 if (speed == 1)
210 speed_s = "1.5";
211 else if (speed == 2)
212 speed_s = "3";
213 else
214 speed_s = "?";
215
216 pci_read_config_word(pdev, 0x0a, &cc);
217 if (cc == 0x0101)
218 scc_s = "IDE";
219 else if (cc == 0x0106)
220 scc_s = "SATA";
221 else if (cc == 0x0104)
222 scc_s = "RAID";
223 else
224 scc_s = "unknown";
225
226 printf("AHCI %02x%02x.%02x%02x "
227 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
228 (vers >> 24) & 0xff,
229 (vers >> 16) & 0xff,
230 (vers >> 8) & 0xff,
231 vers & 0xff,
232 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
233
234 printf("flags: "
235 "%s%s%s%s%s%s"
236 "%s%s%s%s%s%s%s\n",
237 cap & (1 << 31) ? "64bit " : "",
238 cap & (1 << 30) ? "ncq " : "",
239 cap & (1 << 28) ? "ilck " : "",
240 cap & (1 << 27) ? "stag " : "",
241 cap & (1 << 26) ? "pm " : "",
242 cap & (1 << 25) ? "led " : "",
243 cap & (1 << 24) ? "clo " : "",
244 cap & (1 << 19) ? "nz " : "",
245 cap & (1 << 18) ? "only " : "",
246 cap & (1 << 17) ? "pmp " : "",
247 cap & (1 << 15) ? "pio " : "",
248 cap & (1 << 14) ? "slum " : "",
249 cap & (1 << 13) ? "part " : "");
250}
251
252static int ahci_init_one(pci_dev_t pdev)
253{
254 u16 vendor;
255 int rc;
256
257 memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
258
259 probe_ent = malloc(sizeof(struct ahci_probe_ent));
260 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
261 probe_ent->dev = pdev;
262
263 probe_ent->host_flags = ATA_FLAG_SATA
264 | ATA_FLAG_NO_LEGACY
265 | ATA_FLAG_MMIO
266 | ATA_FLAG_PIO_DMA
267 | ATA_FLAG_NO_ATAPI;
268 probe_ent->pio_mask = 0x1f;
269 probe_ent->udma_mask = 0x7f;
270
271 probe_ent->mmio_base = (u32)pci_map_bar(pdev, AHCI_PCI_BAR,
272 PCI_REGION_MEM);
273
274
275
276
277
278 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
279 if (vendor == 0x197b)
280 pci_write_config_byte(pdev, 0x41, 0xa1);
281
282
283 rc = ahci_host_init(probe_ent);
284 if (rc)
285 goto err_out;
286
287 ahci_print_info(probe_ent);
288
289 return 0;
290
291 err_out:
292 return rc;
293}
294
295
296#define MAX_DATA_BYTE_COUNT (4*1024*1024)
297
298static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
299{
300 struct ahci_ioports *pp = &(probe_ent->port[port]);
301 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
302 u32 sg_count;
303 int i;
304
305 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
306 if (sg_count > AHCI_MAX_SG) {
307 printf("Error:Too much sg!\n");
308 return -1;
309 }
310
311 for (i = 0; i < sg_count; i++) {
312 ahci_sg->addr =
313 cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
314 ahci_sg->addr_hi = 0;
315 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
316 (buf_len < MAX_DATA_BYTE_COUNT
317 ? (buf_len - 1)
318 : (MAX_DATA_BYTE_COUNT - 1)));
319 ahci_sg++;
320 buf_len -= MAX_DATA_BYTE_COUNT;
321 }
322
323 return sg_count;
324}
325
326
327static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
328{
329 pp->cmd_slot->opts = cpu_to_le32(opts);
330 pp->cmd_slot->status = 0;
331 pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
332 pp->cmd_slot->tbl_addr_hi = 0;
333}
334
335
336static void ahci_set_feature(u8 port)
337{
338 struct ahci_ioports *pp = &(probe_ent->port[port]);
339 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
340 u32 cmd_fis_len = 5;
341 u8 fis[20];
342
343
344 memset(fis, 0, 20);
345 fis[0] = 0x27;
346 fis[1] = 1 << 7;
347 fis[2] = ATA_CMD_SETF;
348 fis[3] = SETFEATURES_XFER;
349 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
350
351 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
352 ahci_fill_cmd_slot(pp, cmd_fis_len);
353 writel(1, port_mmio + PORT_CMD_ISSUE);
354 readl(port_mmio + PORT_CMD_ISSUE);
355
356 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
357 printf("set feature error!\n");
358 }
359}
360
361
362static int ahci_port_start(u8 port)
363{
364 struct ahci_ioports *pp = &(probe_ent->port[port]);
365 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
366 u32 port_status;
367 u32 mem;
368
369 debug("Enter start port: %d\n", port);
370 port_status = readl(port_mmio + PORT_SCR_STAT);
371 debug("Port %d status: %x\n", port, port_status);
372 if ((port_status & 0xf) != 0x03) {
373 printf("No Link on this port!\n");
374 return -1;
375 }
376
377 mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
378 if (!mem) {
379 free(pp);
380 printf("No mem for table!\n");
381 return -ENOMEM;
382 }
383
384 mem = (mem + 0x800) & (~0x7ff);
385 memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
386
387
388
389
390
391 pp->cmd_slot = (struct ahci_cmd_hdr *)mem;
392 debug("cmd_slot = 0x%x\n", pp->cmd_slot);
393 mem += (AHCI_CMD_SLOT_SZ + 224);
394
395
396
397
398 pp->rx_fis = mem;
399 mem += AHCI_RX_FIS_SZ;
400
401
402
403
404
405 pp->cmd_tbl = mem;
406 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
407
408 mem += AHCI_CMD_TBL_HDR;
409 pp->cmd_tbl_sg = (struct ahci_sg *)mem;
410
411 writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
412
413 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
414
415 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
416 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
417 PORT_CMD_START, port_mmio + PORT_CMD);
418
419 debug("Exit start port %d\n", port);
420
421 return 0;
422}
423
424
425static int get_ahci_device_data(u8 port, u8 *fis, int fis_len, u8 *buf,
426 int buf_len)
427{
428
429 struct ahci_ioports *pp = &(probe_ent->port[port]);
430 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
431 u32 opts;
432 u32 port_status;
433 int sg_count;
434
435 debug("Enter get_ahci_device_data: for port %d\n", port);
436
437 if (port > probe_ent->n_ports) {
438 printf("Invaild port number %d\n", port);
439 return -1;
440 }
441
442 port_status = readl(port_mmio + PORT_SCR_STAT);
443 if ((port_status & 0xf) != 0x03) {
444 debug("No Link on port %d!\n", port);
445 return -1;
446 }
447
448 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
449
450 sg_count = ahci_fill_sg(port, buf, buf_len);
451 opts = (fis_len >> 2) | (sg_count << 16);
452 ahci_fill_cmd_slot(pp, opts);
453
454 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
455
456 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 150, 0x1)) {
457 printf("timeout exit!\n");
458 return -1;
459 }
460 debug("get_ahci_device_data: %d byte transferred.\n",
461 pp->cmd_slot->status);
462
463 return 0;
464}
465
466
467static char *ata_id_strcpy(u16 *target, u16 *src, int len)
468{
469 int i;
470 for (i = 0; i < len / 2; i++)
471 target[i] = le16_to_cpu(src[i]);
472 return (char *)target;
473}
474
475
476static void dump_ataid(hd_driveid_t *ataid)
477{
478 debug("(49)ataid->capability = 0x%x\n", ataid->capability);
479 debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
480 debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
481 debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
482 debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
483 debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
484 debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
485 debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
486 debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
487 debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
488 debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
489 debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
490 debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
491 debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
492 debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
493}
494
495
496
497
498
499static int ata_scsiop_inquiry(ccb *pccb)
500{
501 u8 hdr[] = {
502 0,
503 0,
504 0x5,
505 2,
506 95 - 4,
507 };
508 u8 fis[20];
509 u8 *tmpid;
510 u8 port;
511
512
513 memset(pccb->pdata, 0, pccb->datalen);
514
515 memcpy(pccb->pdata, hdr, sizeof(hdr));
516
517 if (pccb->datalen <= 35)
518 return 0;
519
520 memset(fis, 0, 20);
521
522 fis[0] = 0x27;
523 fis[1] = 1 << 7;
524 fis[2] = ATA_CMD_IDENT;
525
526
527 port = pccb->target;
528 if (!(tmpid = malloc(sizeof(hd_driveid_t))))
529 return -ENOMEM;
530
531 if (get_ahci_device_data(port, (u8 *) & fis, 20,
532 tmpid, sizeof(hd_driveid_t))) {
533 debug("scsi_ahci: SCSI inquiry command failure.\n");
534 return -EIO;
535 }
536
537 if (ataid[port])
538 free(ataid[port]);
539 ataid[port] = (hd_driveid_t *) tmpid;
540
541 memcpy(&pccb->pdata[8], "ATA ", 8);
542 ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
543 ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
544
545 dump_ataid(ataid[port]);
546 return 0;
547}
548
549
550
551
552
553static int ata_scsiop_read10(ccb * pccb)
554{
555 u64 lba = 0;
556 u32 len = 0;
557 u8 fis[20];
558
559 lba = (((u64) pccb->cmd[2]) << 24) | (((u64) pccb->cmd[3]) << 16)
560 | (((u64) pccb->cmd[4]) << 8) | ((u64) pccb->cmd[5]);
561 len = (((u32) pccb->cmd[7]) << 8) | ((u32) pccb->cmd[8]);
562
563
564
565
566
567
568
569
570 if (!len)
571 return 0;
572 memset(fis, 0, 20);
573
574
575 fis[0] = 0x27;
576 fis[1] = 1 << 7;
577 fis[2] = ATA_CMD_RD_DMA;
578
579
580 fis[4] = pccb->cmd[5];
581 fis[5] = pccb->cmd[4];
582 fis[6] = pccb->cmd[3];
583 fis[7] = (pccb->cmd[2] & 0x0f) | 0xe0;
584
585
586 fis[12] = pccb->cmd[8];
587 fis[13] = pccb->cmd[7];
588
589
590 if (get_ahci_device_data(pccb->target, (u8 *) & fis, 20,
591 pccb->pdata, pccb->datalen)) {
592 debug("scsi_ahci: SCSI READ10 command failure.\n");
593 return -EIO;
594 }
595
596 return 0;
597}
598
599
600
601
602
603static int ata_scsiop_read_capacity10(ccb *pccb)
604{
605 u8 buf[8];
606
607 if (!ataid[pccb->target]) {
608 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
609 "\tNo ATA info!\n"
610 "\tPlease run SCSI commmand INQUIRY firstly!\n");
611 return -EPERM;
612 }
613
614 memset(buf, 0, 8);
615
616 *(u32 *) buf = le32_to_cpu(ataid[pccb->target]->lba_capacity);
617
618 buf[6] = 512 >> 8;
619 buf[7] = 512 & 0xff;
620
621 memcpy(pccb->pdata, buf, 8);
622
623 return 0;
624}
625
626
627
628
629
630static int ata_scsiop_test_unit_ready(ccb *pccb)
631{
632 return (ataid[pccb->target]) ? 0 : -EPERM;
633}
634
635
636int scsi_exec(ccb *pccb)
637{
638 int ret;
639
640 switch (pccb->cmd[0]) {
641 case SCSI_READ10:
642 ret = ata_scsiop_read10(pccb);
643 break;
644 case SCSI_RD_CAPAC:
645 ret = ata_scsiop_read_capacity10(pccb);
646 break;
647 case SCSI_TST_U_RDY:
648 ret = ata_scsiop_test_unit_ready(pccb);
649 break;
650 case SCSI_INQUIRY:
651 ret = ata_scsiop_inquiry(pccb);
652 break;
653 default:
654 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
655 return FALSE;
656 }
657
658 if (ret) {
659 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
660 return FALSE;
661 }
662 return TRUE;
663
664}
665
666
667void scsi_low_level_init(int busdevfunc)
668{
669 int i;
670 u32 linkmap;
671
672 ahci_init_one(busdevfunc);
673
674 linkmap = probe_ent->link_port_map;
675
676 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
677 if (((linkmap >> i) & 0x01)) {
678 if (ahci_port_start((u8) i)) {
679 printf("Can not start port %d\n", i);
680 continue;
681 }
682 ahci_set_feature((u8) i);
683 }
684 }
685}
686
687
688void scsi_bus_reset(void)
689{
690
691}
692
693
694void scsi_print_error(ccb * pccb)
695{
696
697}
698