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74#include <common.h>
75#include <malloc.h>
76#include <net.h>
77#include <netdev.h>
78#include <asm/io.h>
79#include <pci.h>
80
81#define RTL_TIMEOUT 100000
82
83#define ETH_FRAME_LEN 1514
84#define ETH_ALEN 6
85#define ETH_ZLEN 60
86
87
88
89#define TX_FIFO_THRESH 256
90#define RX_FIFO_THRESH 4
91#define RX_DMA_BURST 4
92#define TX_DMA_BURST 4
93#define NUM_TX_DESC 4
94#define TX_BUF_SIZE ETH_FRAME_LEN
95#define RX_BUF_LEN_IDX 0
96#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
97
98#undef DEBUG_TX
99#undef DEBUG_RX
100
101#define currticks() get_timer(0)
102#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
103#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
104
105
106enum RTL8139_registers {
107 MAC0=0,
108 MAR0=8,
109 TxStatus0=0x10,
110 TxAddr0=0x20,
111 RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
112 ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
113 IntrMask=0x3C, IntrStatus=0x3E,
114 TxConfig=0x40, RxConfig=0x44,
115 Timer=0x48,
116 RxMissed=0x4C,
117 Cfg9346=0x50, Config0=0x51, Config1=0x52,
118 TimerIntrReg=0x54,
119 MediaStatus=0x58,
120 Config3=0x59,
121 MultiIntr=0x5C,
122 RevisionID=0x5E,
123 TxSummary=0x60,
124 MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
125 NWayExpansion=0x6A,
126 DisconnectCnt=0x6C, FalseCarrierCnt=0x6E,
127 NWayTestReg=0x70,
128 RxCnt=0x72,
129 CSCR=0x74,
130 PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80,
131
132
133};
134
135enum ChipCmdBits {
136 CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };
137
138
139enum IntrStatusBits {
140 PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000,
141 RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
142 TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
143};
144enum TxStatusBits {
145 TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
146 TxOutOfWindow=0x20000000, TxAborted=0x40000000,
147 TxCarrierLost=0x80000000,
148};
149enum RxStatusBits {
150 RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
151 RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
152 RxBadAlign=0x0002, RxStatusOK=0x0001,
153};
154
155enum MediaStatusBits {
156 MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08,
157 MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01,
158};
159
160enum MIIBMCRBits {
161 BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000,
162 BMCRRestartNWay=0x0200, BMCRDuplex=0x0100,
163};
164
165enum CSCRBits {
166 CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
167 CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
168 CSCR_LinkDownCmd=0x0f3c0,
169};
170
171
172enum rx_mode_bits {
173 RxCfgWrap=0x80,
174 AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
175 AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
176};
177
178static int ioaddr;
179static unsigned int cur_rx,cur_tx;
180
181
182static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4)));
183static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));
184
185static int rtl8139_probe(struct eth_device *dev, bd_t *bis);
186static int read_eeprom(int location, int addr_len);
187static void rtl_reset(struct eth_device *dev);
188static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length);
189static int rtl_poll(struct eth_device *dev);
190static void rtl_disable(struct eth_device *dev);
191#ifdef CONFIG_MCAST_TFTP
192static int rtl_bcast_addr (struct eth_device *dev, u8 bcast_mac, u8 set)
193{
194 return (0);
195}
196#endif
197
198static struct pci_device_id supported[] = {
199 {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
200 {PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_8139},
201 {}
202};
203
204int rtl8139_initialize(bd_t *bis)
205{
206 pci_dev_t devno;
207 int card_number = 0;
208 struct eth_device *dev;
209 u32 iobase;
210 int idx=0;
211
212 while(1){
213
214 if ((devno = pci_find_devices(supported, idx++)) < 0)
215 break;
216
217 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
218 iobase &= ~0xf;
219
220 debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
221
222 dev = (struct eth_device *)malloc(sizeof *dev);
223
224 sprintf (dev->name, "RTL8139#%d", card_number);
225
226 dev->priv = (void *) devno;
227 dev->iobase = (int)bus_to_phys(iobase);
228 dev->init = rtl8139_probe;
229 dev->halt = rtl_disable;
230 dev->send = rtl_transmit;
231 dev->recv = rtl_poll;
232#ifdef CONFIG_MCAST_TFTP
233 dev->mcast = rtl_bcast_addr;
234#endif
235
236 eth_register (dev);
237
238 card_number++;
239
240 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
241
242 udelay (10 * 1000);
243 }
244
245 return card_number;
246}
247
248static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
249{
250 int i;
251 int speed10, fullduplex;
252 int addr_len;
253 unsigned short *ap = (unsigned short *)dev->enetaddr;
254
255 ioaddr = dev->iobase;
256
257
258 outb(0x00, ioaddr + Config1);
259
260 addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
261 for (i = 0; i < 3; i++)
262 *ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len));
263
264 speed10 = inb(ioaddr + MediaStatus) & MSRSpeed10;
265 fullduplex = inw(ioaddr + MII_BMCR) & BMCRDuplex;
266
267 rtl_reset(dev);
268
269 if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
270 printf("Cable not connected or other link failure\n");
271 return -1 ;
272 }
273
274 return 0;
275}
276
277
278
279
280#define EE_SHIFT_CLK 0x04
281#define EE_CS 0x08
282#define EE_DATA_WRITE 0x02
283#define EE_WRITE_0 0x00
284#define EE_WRITE_1 0x02
285#define EE_DATA_READ 0x01
286#define EE_ENB (0x80 | EE_CS)
287
288
289
290
291
292
293#define eeprom_delay() inl(ee_addr)
294
295
296#define EE_WRITE_CMD (5)
297#define EE_READ_CMD (6)
298#define EE_ERASE_CMD (7)
299
300static int read_eeprom(int location, int addr_len)
301{
302 int i;
303 unsigned int retval = 0;
304 long ee_addr = ioaddr + Cfg9346;
305 int read_cmd = location | (EE_READ_CMD << addr_len);
306
307 outb(EE_ENB & ~EE_CS, ee_addr);
308 outb(EE_ENB, ee_addr);
309 eeprom_delay();
310
311
312 for (i = 4 + addr_len; i >= 0; i--) {
313 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
314 outb(EE_ENB | dataval, ee_addr);
315 eeprom_delay();
316 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
317 eeprom_delay();
318 }
319 outb(EE_ENB, ee_addr);
320 eeprom_delay();
321
322 for (i = 16; i > 0; i--) {
323 outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
324 eeprom_delay();
325 retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
326 outb(EE_ENB, ee_addr);
327 eeprom_delay();
328 }
329
330
331 outb(~EE_CS, ee_addr);
332 eeprom_delay();
333 return retval;
334}
335
336static const unsigned int rtl8139_rx_config =
337 (RX_BUF_LEN_IDX << 11) |
338 (RX_FIFO_THRESH << 13) |
339 (RX_DMA_BURST << 8);
340
341static void set_rx_mode(struct eth_device *dev) {
342 unsigned int mc_filter[2];
343 int rx_mode;
344
345 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
346 mc_filter[1] = mc_filter[0] = 0xffffffff;
347
348 outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig);
349
350 outl(mc_filter[0], ioaddr + MAR0 + 0);
351 outl(mc_filter[1], ioaddr + MAR0 + 4);
352}
353
354static void rtl_reset(struct eth_device *dev)
355{
356 int i;
357
358 outb(CmdReset, ioaddr + ChipCmd);
359
360 cur_rx = 0;
361 cur_tx = 0;
362
363
364 for (i=0; i<100; ++i){
365 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
366 udelay (100);
367 }
368
369
370 for (i = 0; i < ETH_ALEN; i++)
371 outb(dev->enetaddr[i], ioaddr + MAC0 + i);
372
373
374 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
375 outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8),
376 ioaddr + RxConfig);
377 outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig);
378
379
380
381
382
383
384
385
386
387#ifdef DEBUG_RX
388 printf("rx ring address is %X\n",(unsigned long)rx_ring);
389#endif
390 flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
391 outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf);
392
393
394
395
396
397 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
398
399 outl(rtl8139_rx_config, ioaddr + RxConfig);
400
401
402 outl(0, ioaddr + RxMissed);
403
404
405 set_rx_mode(dev);
406
407
408 outw(0, ioaddr + IntrMask);
409}
410
411static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length)
412{
413 unsigned int status;
414 unsigned long txstatus;
415 unsigned int len = length;
416 int i = 0;
417
418 ioaddr = dev->iobase;
419
420 memcpy((char *)tx_buffer, (char *)packet, (int)length);
421
422#ifdef DEBUG_TX
423 printf("sending %d bytes\n", len);
424#endif
425
426
427
428 while (len < ETH_ZLEN) {
429 tx_buffer[len++] = '\0';
430 }
431
432 flush_cache((unsigned long)tx_buffer, length);
433 outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4);
434 outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
435 ioaddr + TxStatus0 + cur_tx*4);
436
437 do {
438 status = inw(ioaddr + IntrStatus);
439
440
441
442 outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
443 if ((status & (TxOK | TxErr | PCIErr)) != 0) break;
444 udelay(10);
445 } while (i++ < RTL_TIMEOUT);
446
447 txstatus = inl(ioaddr + TxStatus0 + cur_tx*4);
448
449 if (status & TxOK) {
450 cur_tx = (cur_tx + 1) % NUM_TX_DESC;
451#ifdef DEBUG_TX
452 printf("tx done (%d ticks), status %hX txstatus %X\n",
453 to-currticks(), status, txstatus);
454#endif
455 return length;
456 } else {
457#ifdef DEBUG_TX
458 printf("tx timeout/error (%d usecs), status %hX txstatus %X\n",
459 10*i, status, txstatus);
460#endif
461 rtl_reset(dev);
462
463 return 0;
464 }
465}
466
467static int rtl_poll(struct eth_device *dev)
468{
469 unsigned int status;
470 unsigned int ring_offs;
471 unsigned int rx_size, rx_status;
472 int length=0;
473
474 ioaddr = dev->iobase;
475
476 if (inb(ioaddr + ChipCmd) & RxBufEmpty) {
477 return 0;
478 }
479
480 status = inw(ioaddr + IntrStatus);
481
482 outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
483
484#ifdef DEBUG_RX
485 printf("rtl_poll: int %hX ", status);
486#endif
487
488 ring_offs = cur_rx % RX_BUF_LEN;
489
490 rx_status = le32_to_cpu(*(unsigned int *)(rx_ring + ring_offs));
491 rx_size = rx_status >> 16;
492 rx_status &= 0xffff;
493
494 if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) ||
495 (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) {
496 printf("rx error %hX\n", rx_status);
497 rtl_reset(dev);
498 return 0;
499 }
500
501
502 length = rx_size - 4;
503 if (ring_offs+4+rx_size-4 > RX_BUF_LEN) {
504 int semi_count = RX_BUF_LEN - ring_offs - 4;
505 unsigned char rxdata[RX_BUF_LEN];
506
507 memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
508 memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count);
509
510 NetReceive(rxdata, length);
511#ifdef DEBUG_RX
512 printf("rx packet %d+%d bytes", semi_count,rx_size-4-semi_count);
513#endif
514 } else {
515 NetReceive(rx_ring + ring_offs + 4, length);
516#ifdef DEBUG_RX
517 printf("rx packet %d bytes", rx_size-4);
518#endif
519 }
520 flush_cache((unsigned long)rx_ring, RX_BUF_LEN);
521
522 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
523 outw(cur_rx - 16, ioaddr + RxBufPtr);
524
525
526
527 outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
528 return length;
529}
530
531static void rtl_disable(struct eth_device *dev)
532{
533 int i;
534
535 ioaddr = dev->iobase;
536
537
538 outb(CmdReset, ioaddr + ChipCmd);
539
540
541 for (i=0; i<100; ++i){
542 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
543 udelay (100);
544 }
545}
546