LXR uboot/drivers/spi/atmel_dataflash

   1/*
   2 * Driver for ATMEL DataFlash support
   3 * Author : Hamid Ikdoumi (Atmel)
   4 *
   5 * This program is free software; you can redistribute it and/or
   6 * modify it under the terms of the GNU General Public License as
   7 * published by the Free Software Foundation; either version 2 of
   8 * the License, or (at your option) any later version.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18 * MA 02111-1307 USA
  19 *
  20 */
  21
  22#include <common.h>
  23#include <asm/arch/hardware.h>
  24#include <asm/arch/clk.h>
  25#include <asm/arch/gpio.h>
  26#include <asm/arch/io.h>
  27#include <asm/arch/at91_pio.h>
  28#include <asm/arch/at91_spi.h>
  29
  30#include <dataflash.h>
  31
  32#define AT91_SPI_PCS0_DATAFLASH_CARD    0xE     /* Chip Select 0: NPCS0%1110 */
  33#define AT91_SPI_PCS1_DATAFLASH_CARD    0xD     /* Chip Select 0: NPCS0%1101 */
  34#define AT91_SPI_PCS3_DATAFLASH_CARD    0x7     /* Chip Select 3: NPCS3%0111 */
  35
  36void AT91F_SpiInit(void)
  37{
  38        /* Reset the SPI */
  39        writel(AT91_SPI_SWRST, AT91_BASE_SPI + AT91_SPI_CR);
  40
  41        /* Configure SPI in Master Mode with No CS selected !!! */
  42        writel(AT91_SPI_MSTR | AT91_SPI_MODFDIS | AT91_SPI_PCS,
  43               AT91_BASE_SPI + AT91_SPI_MR);
  44
  45        /* Configure CS0 */
  46        writel(AT91_SPI_NCPHA |
  47               (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
  48               (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
  49               ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
  50               AT91_BASE_SPI + AT91_SPI_CSR(0));
  51
  52#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1
  53        /* Configure CS1 */
  54        writel(AT91_SPI_NCPHA |
  55               (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
  56               (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
  57               ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
  58               AT91_BASE_SPI + AT91_SPI_CSR(1));
  59#endif
  60
  61#ifdef CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3
  62        /* Configure CS3 */
  63        writel(AT91_SPI_NCPHA |
  64               (AT91_SPI_DLYBS & DATAFLASH_TCSS) |
  65               (AT91_SPI_DLYBCT & DATAFLASH_TCHS) |
  66               ((get_mck_clk_rate() / AT91_SPI_CLK) << 8),
  67               AT91_BASE_SPI + AT91_SPI_CSR(3));
  68#endif
  69
  70        /* SPI_Enable */
  71        writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
  72
  73        while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_SPIENS));
  74
  75        /*
  76         * Add tempo to get SPI in a safe state.
  77         * Should not be needed for new silicon (Rev B)
  78         */
  79        udelay(500000);
  80        readl(AT91_BASE_SPI + AT91_SPI_SR);
  81        readl(AT91_BASE_SPI + AT91_SPI_RDR);
  82
  83}
  84
  85void AT91F_SpiEnable(int cs)
  86{
  87        unsigned long mode;
  88
  89        switch (cs) {
  90        case 0: /* Configure SPI CS0 for Serial DataFlash AT45DBxx */
  91                mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
  92                mode &= 0xFFF0FFFF;
  93                writel(mode | ((AT91_SPI_PCS0_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
  94                       AT91_BASE_SPI + AT91_SPI_MR);
  95                break;
  96        case 1: /* Configure SPI CS1 for Serial DataFlash AT45DBxx */
  97                mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
  98                mode &= 0xFFF0FFFF;
  99                writel(mode | ((AT91_SPI_PCS1_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
 100                       AT91_BASE_SPI + AT91_SPI_MR);
 101                break;
 102        case 3:
 103                mode = readl(AT91_BASE_SPI + AT91_SPI_MR);
 104                mode &= 0xFFF0FFFF;
 105                writel(mode | ((AT91_SPI_PCS3_DATAFLASH_CARD<<16) & AT91_SPI_PCS),
 106                       AT91_BASE_SPI + AT91_SPI_MR);
 107                break;
 108        }
 109
 110        /* SPI_Enable */
 111        writel(AT91_SPI_SPIEN, AT91_BASE_SPI + AT91_SPI_CR);
 112}
 113
 114unsigned int AT91F_SpiWrite1(AT91PS_DataflashDesc pDesc);
 115
 116unsigned int AT91F_SpiWrite(AT91PS_DataflashDesc pDesc)
 117{
 118        unsigned int timeout;
 119
 120        pDesc->state = BUSY;
 121
 122        writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
 123
 124        /* Initialize the Transmit and Receive Pointer */
 125        writel((unsigned int)pDesc->rx_cmd_pt, AT91_BASE_SPI + AT91_SPI_RPR);
 126        writel((unsigned int)pDesc->tx_cmd_pt, AT91_BASE_SPI + AT91_SPI_TPR);
 127
 128        /* Intialize the Transmit and Receive Counters */
 129        writel(pDesc->rx_cmd_size, AT91_BASE_SPI + AT91_SPI_RCR);
 130        writel(pDesc->tx_cmd_size, AT91_BASE_SPI + AT91_SPI_TCR);
 131
 132        if (pDesc->tx_data_size != 0) {
 133                /* Initialize the Next Transmit and Next Receive Pointer */
 134                writel((unsigned int)pDesc->rx_data_pt, AT91_BASE_SPI + AT91_SPI_RNPR);
 135                writel((unsigned int)pDesc->tx_data_pt, AT91_BASE_SPI + AT91_SPI_TNPR);
 136
 137                /* Intialize the Next Transmit and Next Receive Counters */
 138                writel(pDesc->rx_data_size, AT91_BASE_SPI + AT91_SPI_RNCR);
 139                writel(pDesc->tx_data_size, AT91_BASE_SPI + AT91_SPI_TNCR);
 140        }
 141
 142        /* arm simple, non interrupt dependent timer */
 143        reset_timer_masked();
 144        timeout = 0;
 145
 146        writel(AT91_SPI_TXTEN + AT91_SPI_RXTEN, AT91_BASE_SPI + AT91_SPI_PTCR);
 147        while (!(readl(AT91_BASE_SPI + AT91_SPI_SR) & AT91_SPI_RXBUFF) &&
 148                ((timeout = get_timer_masked()) < CONFIG_SYS_SPI_WRITE_TOUT));
 149        writel(AT91_SPI_TXTDIS + AT91_SPI_RXTDIS, AT91_BASE_SPI + AT91_SPI_PTCR);
 150        pDesc->state = IDLE;
 151
 152        if (timeout >= CONFIG_SYS_SPI_WRITE_TOUT) {
 153                printf("Error Timeout\n\r");
 154                return DATAFLASH_ERROR;
 155        }
 156
 157        return DATAFLASH_OK;
 158}
 159