1/* (C) Copyright 2007 Freescale Semiconductor, Inc. 2 * 3 * This program is free software; you can redistribute it and/or 4 * modify it under the terms of the GNU General Public License as 5 * published by the Free Software Foundation; either version 2 of 6 * the License, or (at your option) any later version. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, write to the Free Software 15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 16 * MA 02111-1307 USA 17 * 18 */ 19 20#ifndef __FSL_PCI_H_ 21#define __FSL_PCI_H_ 22 23int fsl_pci_setup_inbound_windows(struct pci_region *r); 24void fsl_pci_init(struct pci_controller *hose); 25void fsl_pci_config_unlock(struct pci_controller *hose); 26void ft_fsl_pci_setup(void *blob, const char *pci_alias, 27 struct pci_controller *hose); 28 29/* 30 * Common PCI/PCIE Register structure for mpc85xx and mpc86xx 31 */ 32 33/* 34 * PCI Translation Registers 35 */ 36typedef struct pci_outbound_window { 37 u32 potar; /* 0x00 - Address */ 38 u32 potear; /* 0x04 - Address Extended */ 39 u32 powbar; /* 0x08 - Window Base Address */ 40 u32 res1; 41 u32 powar; /* 0x10 - Window Attributes */ 42#define POWAR_EN 0x80000000 43#define POWAR_IO_READ 0x00080000 44#define POWAR_MEM_READ 0x00040000 45#define POWAR_IO_WRITE 0x00008000 46#define POWAR_MEM_WRITE 0x00004000 47 u32 res2[3]; 48} pot_t; 49 50typedef struct pci_inbound_window { 51 u32 pitar; /* 0x00 - Address */ 52 u32 res1; 53 u32 piwbar; /* 0x08 - Window Base Address */ 54 u32 piwbear; /* 0x0c - Window Base Address Extended */ 55 u32 piwar; /* 0x10 - Window Attributes */ 56#define PIWAR_EN 0x80000000 57#define PIWAR_PF 0x20000000 58#define PIWAR_LOCAL 0x00f00000 59#define PIWAR_READ_SNOOP 0x00050000 60#define PIWAR_WRITE_SNOOP 0x00005000 61 u32 res2[3]; 62} pit_t; 63 64/* PCI/PCI Express Registers */ 65typedef struct ccsr_pci { 66 u32 cfg_addr; /* 0x000 - PCI Configuration Address Register */ 67 u32 cfg_data; /* 0x004 - PCI Configuration Data Register */ 68 u32 int_ack; /* 0x008 - PCI Interrupt Acknowledge Register */ 69 u32 out_comp_to; /* 0x00C - PCI Outbound Completion Timeout Register */ 70 u32 out_conf_to; /* 0x010 - PCI Configuration Timeout Register */ 71 u32 config; /* 0x014 - PCIE CONFIG Register */ 72 char res2[8]; 73 u32 pme_msg_det; /* 0x020 - PCIE PME & message detect register */ 74 u32 pme_msg_dis; /* 0x024 - PCIE PME & message disable register */ 75 u32 pme_msg_int_en; /* 0x028 - PCIE PME & message interrupt enable register */ 76 u32 pm_command; /* 0x02c - PCIE PM Command register */ 77 char res4[3016]; /* (- #xbf8 #x30)3016 */ 78 u32 block_rev1; /* 0xbf8 - PCIE Block Revision register 1 */ 79 u32 block_rev2; /* 0xbfc - PCIE Block Revision register 2 */ 80 81 pot_t pot[5]; /* 0xc00 - 0xc9f Outbound ATMU's 0, 1, 2, 3, and 4 */ 82 u32 res5[64]; 83 pit_t pit[3]; /* 0xda0 - 0xdff Inbound ATMU's 3, 2, and 1 */ 84#define PIT3 0 85#define PIT2 1 86#define PIT1 2 87 88#if 0 89 u32 potar0; /* 0xc00 - PCI Outbound Transaction Address Register 0 */ 90 u32 potear0; /* 0xc04 - PCI Outbound Translation Extended Address Register 0 */ 91 char res5[8]; 92 u32 powar0; /* 0xc10 - PCI Outbound Window Attributes Register 0 */ 93 char res6[12]; 94 u32 potar1; /* 0xc20 - PCI Outbound Transaction Address Register 1 */ 95 u32 potear1; /* 0xc24 - PCI Outbound Translation Extended Address Register 1 */ 96 u32 powbar1; /* 0xc28 - PCI Outbound Window Base Address Register 1 */ 97 char res7[4]; 98 u32 powar1; /* 0xc30 - PCI Outbound Window Attributes Register 1 */ 99 char res8[12]; 100 u32 potar2; /* 0xc40 - PCI Outbound Transaction Address Register 2 */ 101 u32 potear2; /* 0xc44 - PCI Outbound Translation Extended Address Register 2 */ 102 u32 powbar2; /* 0xc48 - PCI Outbound Window Base Address Register 2 */ 103 char res9[4]; 104 u32 powar2; /* 0xc50 - PCI Outbound Window Attributes Register 2 */ 105 char res10[12]; 106 u32 potar3; /* 0xc60 - PCI Outbound Transaction Address Register 3 */ 107 u32 potear3; /* 0xc64 - PCI Outbound Translation Extended Address Register 3 */ 108 u32 powbar3; /* 0xc68 - PCI Outbound Window Base Address Register 3 */ 109 char res11[4]; 110 u32 powar3; /* 0xc70 - PCI Outbound Window Attributes Register 3 */ 111 char res12[12]; 112 u32 potar4; /* 0xc80 - PCI Outbound Transaction Address Register 4 */ 113 u32 potear4; /* 0xc84 - PCI Outbound Translation Extended Address Register 4 */ 114 u32 powbar4; /* 0xc88 - PCI Outbound Window Base Address Register 4 */ 115 char res13[4]; 116 u32 powar4; /* 0xc90 - PCI Outbound Window Attributes Register 4 */ 117 char res14[268]; 118 u32 pitar3; /* 0xda0 - PCI Inbound Translation Address Register 3 */ 119 char res15[4]; 120 u32 piwbar3; /* 0xda8 - PCI Inbound Window Base Address Register 3 */ 121 u32 piwbear3; /* 0xdac - PCI Inbound Window Base Extended Address Register 3 */ 122 u32 piwar3; /* 0xdb0 - PCI Inbound Window Attributes Register 3 */ 123 char res16[12]; 124 u32 pitar2; /* 0xdc0 - PCI Inbound Translation Address Register 2 */ 125 char res17[4]; 126 u32 piwbar2; /* 0xdc8 - PCI Inbound Window Base Address Register 2 */ 127 u32 piwbear2; /* 0xdcc - PCI Inbound Window Base Extended Address Register 2 */ 128 u32 piwar2; /* 0xdd0 - PCI Inbound Window Attributes Register 2 */ 129 char res18[12]; 130 u32 pitar1; /* 0xde0 - PCI Inbound Translation Address Register 1 */ 131 char res19[4]; 132 u32 piwbar1; /* 0xde8 - PCI Inbound Window Base Address Register 1 */ 133 char res20[4]; 134 u32 piwar1; /* 0xdf0 - PCI Inbound Window Attributes Register 1 */ 135 char res21[12]; 136#endif 137 u32 pedr; /* 0xe00 - PCI Error Detect Register */ 138 u32 pecdr; /* 0xe04 - PCI Error Capture Disable Register */ 139 u32 peer; /* 0xe08 - PCI Error Interrupt Enable Register */ 140 u32 peattrcr; /* 0xe0c - PCI Error Attributes Capture Register */ 141 u32 peaddrcr; /* 0xe10 - PCI Error Address Capture Register */ 142/* u32 perr_disr * 0xe10 - PCIE Erorr Disable Register */ 143 u32 peextaddrcr; /* 0xe14 - PCI Error Extended Address Capture Register */ 144 u32 pedlcr; /* 0xe18 - PCI Error Data Low Capture Register */ 145 u32 pedhcr; /* 0xe1c - PCI Error Error Data High Capture Register */ 146 u32 gas_timr; /* 0xe20 - PCI Gasket Timer Register */ 147/* u32 perr_cap_stat; * 0xe20 - PCIE Error Capture Status Register */ 148 char res22[4]; 149 u32 perr_cap0; /* 0xe28 - PCIE Error Capture Register 0 */ 150 u32 perr_cap1; /* 0xe2c - PCIE Error Capture Register 1 */ 151 u32 perr_cap2; /* 0xe30 - PCIE Error Capture Register 2 */ 152 u32 perr_cap3; /* 0xe34 - PCIE Error Capture Register 3 */ 153 char res23[200]; 154 u32 pdb_stat; /* 0xf00 - PCIE Debug Status */ 155 char res24[252]; 156} ccsr_fsl_pci_t; 157 158#endif 159