1/* 2 * MPC85xx Internal Memory Map 3 * 4 * Copyright 2007 Freescale Semiconductor. 5 * 6 * Copyright(c) 2002,2003 Motorola Inc. 7 * Xianghua Xiao (x.xiao@motorola.com) 8 * 9 */ 10 11#ifndef __IMMAP_85xx__ 12#define __IMMAP_85xx__ 13 14#include <asm/types.h> 15#include <asm/fsl_i2c.h> 16#include <asm/fsl_lbc.h> 17 18/* 19 * Local-Access Registers and ECM Registers(0x0000-0x2000) 20 */ 21typedef struct ccsr_local_ecm { 22 uint ccsrbar; /* 0x0 - Control Configuration Status Registers Base Address Register */ 23 char res1[4]; 24 uint altcbar; /* 0x8 - Alternate Configuration Base Address Register */ 25 char res2[4]; 26 uint altcar; /* 0x10 - Alternate Configuration Attribute Register */ 27 char res3[12]; 28 uint bptr; /* 0x20 - Boot Page Translation Register */ 29 char res4[3044]; 30 uint lawbar0; /* 0xc08 - Local Access Window 0 Base Address Register */ 31 char res5[4]; 32 uint lawar0; /* 0xc10 - Local Access Window 0 Attributes Register */ 33 char res6[20]; 34 uint lawbar1; /* 0xc28 - Local Access Window 1 Base Address Register */ 35 char res7[4]; 36 uint lawar1; /* 0xc30 - Local Access Window 1 Attributes Register */ 37 char res8[20]; 38 uint lawbar2; /* 0xc48 - Local Access Window 2 Base Address Register */ 39 char res9[4]; 40 uint lawar2; /* 0xc50 - Local Access Window 2 Attributes Register */ 41 char res10[20]; 42 uint lawbar3; /* 0xc68 - Local Access Window 3 Base Address Register */ 43 char res11[4]; 44 uint lawar3; /* 0xc70 - Local Access Window 3 Attributes Register */ 45 char res12[20]; 46 uint lawbar4; /* 0xc88 - Local Access Window 4 Base Address Register */ 47 char res13[4]; 48 uint lawar4; /* 0xc90 - Local Access Window 4 Attributes Register */ 49 char res14[20]; 50 uint lawbar5; /* 0xca8 - Local Access Window 5 Base Address Register */ 51 char res15[4]; 52 uint lawar5; /* 0xcb0 - Local Access Window 5 Attributes Register */ 53 char res16[20]; 54 uint lawbar6; /* 0xcc8 - Local Access Window 6 Base Address Register */ 55 char res17[4]; 56 uint lawar6; /* 0xcd0 - Local Access Window 6 Attributes Register */ 57 char res18[20]; 58 uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */ 59 char res19[4]; 60 uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */ 61 char res19_8a[20]; 62 uint lawbar8; /* 0xd08 - Local Access Window 8 Base Address Register */ 63 char res19_8b[4]; 64 uint lawar8; /* 0xd10 - Local Access Window 8 Attributes Register */ 65 char res19_9a[20]; 66 uint lawbar9; /* 0xd28 - Local Access Window 9 Base Address Register */ 67 char res19_9b[4]; 68 uint lawar9; /* 0xd30 - Local Access Window 9 Attributes Register */ 69 char res19_10a[20]; 70 uint lawbar10; /* 0xd48 - Local Access Window 10 Base Address Register */ 71 char res19_10b[4]; 72 uint lawar10; /* 0xd50 - Local Access Window 10 Attributes Register */ 73 char res19_11a[20]; 74 uint lawbar11; /* 0xd68 - Local Access Window 11 Base Address Register */ 75 char res19_11b[4]; 76 uint lawar11; /* 0xd70 - Local Access Window 11 Attributes Register */ 77 char res20[652]; 78 uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */ 79 char res21[12]; 80 uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */ 81 char res22[3564]; 82 uint eedr; /* 0x1e00 - ECM Error Detect Register */ 83 char res23[4]; 84 uint eeer; /* 0x1e08 - ECM Error Enable Register */ 85 uint eeatr; /* 0x1e0c - ECM Error Attributes Capture Register */ 86 uint eeadr; /* 0x1e10 - ECM Error Address Capture Register */ 87 char res24[492]; 88} ccsr_local_ecm_t; 89 90/* 91 * DDR memory controller registers(0x2000-0x3000) 92 */ 93typedef struct ccsr_ddr { 94 uint cs0_bnds; /* 0x2000 - DDR Chip Select 0 Memory Bounds */ 95 char res1[4]; 96 uint cs1_bnds; /* 0x2008 - DDR Chip Select 1 Memory Bounds */ 97 char res2[4]; 98 uint cs2_bnds; /* 0x2010 - DDR Chip Select 2 Memory Bounds */ 99 char res3[4]; 100 uint cs3_bnds; /* 0x2018 - DDR Chip Select 3 Memory Bounds */ 101 char res4[100]; 102 uint cs0_config; /* 0x2080 - DDR Chip Select Configuration */ 103 uint cs1_config; /* 0x2084 - DDR Chip Select Configuration */ 104 uint cs2_config; /* 0x2088 - DDR Chip Select Configuration */ 105 uint cs3_config; /* 0x208c - DDR Chip Select Configuration */ 106 char res4a[48]; 107 uint cs0_config_2; /* 0x20c0 - DDR Chip Select Configuration 2 */ 108 uint cs1_config_2; /* 0x20c4 - DDR Chip Select Configuration 2 */ 109 uint cs2_config_2; /* 0x20c8 - DDR Chip Select Configuration 2 */ 110 uint cs3_config_2; /* 0x20cc - DDR Chip Select Configuration 2 */ 111 char res5[48]; 112 uint timing_cfg_3; /* 0x2100 - DDR SDRAM Timing Configuration Register 3 */ 113 uint timing_cfg_0; /* 0x2104 - DDR SDRAM Timing Configuration Register 0 */ 114 uint timing_cfg_1; /* 0x2108 - DDR SDRAM Timing Configuration Register 1 */ 115 uint timing_cfg_2; /* 0x210c - DDR SDRAM Timing Configuration Register 2 */ 116 uint sdram_cfg; /* 0x2110 - DDR SDRAM Control Configuration */ 117 uint sdram_cfg_2; /* 0x2114 - DDR SDRAM Control Configuration 2 */ 118 uint sdram_mode; /* 0x2118 - DDR SDRAM Mode Configuration */ 119 uint sdram_mode_2; /* 0x211c - DDR SDRAM Mode Configuration 2*/ 120 uint sdram_md_cntl; /* 0x2120 - DDR SDRAM Mode Control */ 121 uint sdram_interval; /* 0x2124 - DDR SDRAM Interval Configuration */ 122 uint sdram_data_init; /* 0x2128 - DDR SDRAM Data initialization */ 123 char res6[4]; 124 uint sdram_clk_cntl; /* 0x2130 - DDR SDRAM Clock Control */ 125 char res7[20]; 126 uint init_addr; /* 0x2148 - DDR training initialization address */ 127 uint init_ext_addr; /* 0x214C - DDR training initialization extended address */ 128 char res8_1[16]; 129 uint timing_cfg_4; /* 0x2160 - DDR SDRAM Timing Configuration Register 4 */ 130 uint timing_cfg_5; /* 0x2164 - DDR SDRAM Timing Configuration Register 5 */ 131 char reg8_1a[8]; 132 uint ddr_zq_cntl; /* 0x2170 - DDR ZQ calibration control*/ 133 uint ddr_wrlvl_cntl; /* 0x2174 - DDR write leveling control*/ 134 uint ddr_pd_cntl; /* 0x2178 - DDR pre-drive conditioning control*/ 135 uint ddr_sr_cntr; /* 0x217C - DDR self refresh counter */ 136 uint ddr_sdram_rcw_1; /* 0x2180 - DDR Register Control Words 1 */ 137 uint ddr_sdram_rcw_2; /* 0x2184 - DDR Register Control Words 2 */ 138 char res8_1b[2456]; 139 uint ddr_dsr1; /* 0x2B20 - DDR Debug Status Register 1 */ 140 uint ddr_dsr2; /* 0x2B24 - DDR Debug Status Register 2 */ 141 uint ddr_cdr1; /* 0x2B28 - DDR Control Driver Register 1 */ 142 uint ddr_cdr2; /* 0x2B2C - DDR Control Driver Register 2 */ 143 char res8_1c[200]; 144 uint ip_rev1; /* 0x2BF8 - DDR IP Block Revision 1 */ 145 uint ip_rev2; /* 0x2BFC - DDR IP Block Revision 2 */ 146 char res8_2[512]; 147 uint data_err_inject_hi; /* 0x2e00 - DDR Memory Data Path Error Injection Mask High */ 148 uint data_err_inject_lo; /* 0x2e04 - DDR Memory Data Path Error Injection Mask Low */ 149 uint ecc_err_inject; /* 0x2e08 - DDR Memory Data Path Error Injection Mask ECC */ 150 char res9[20]; 151 uint capture_data_hi; /* 0x2e20 - DDR Memory Data Path Read Capture High */ 152 uint capture_data_lo; /* 0x2e24 - DDR Memory Data Path Read Capture Low */ 153 uint capture_ecc; /* 0x2e28 - DDR Memory Data Path Read Capture ECC */ 154 char res10[20]; 155 uint err_detect; /* 0x2e40 - DDR Memory Error Detect */ 156 uint err_disable; /* 0x2e44 - DDR Memory Error Disable */ 157 uint err_int_en; /* 0x2e48 - DDR */ 158 uint capture_attributes; /* 0x2e4c - DDR Memory Error Attributes Capture */ 159 uint capture_address; /* 0x2e50 - DDR Memory Error Address Capture */ 160 uint capture_ext_address; /* 0x2e54 - DDR Memory Error Extended Address Capture */ 161 uint err_sbe; /* 0x2e58 - DDR Memory Single-Bit ECC Error Management */ 162 char res11[164]; 163 uint debug_1; /* 0x2f00 */ 164 uint debug_2; 165 uint debug_3; 166 uint debug_4; 167 char res12[240]; 168} ccsr_ddr_t; 169 170/* 171 * I2C Registers(0x3000-0x4000) 172 */ 173typedef struct ccsr_i2c { 174 struct fsl_i2c i2c[1]; 175 u8 res[4096 - 1 * sizeof(struct fsl_i2c)]; 176} ccsr_i2c_t; 177 178#if defined(CONFIG_MPC8540) \ 179 || defined(CONFIG_MPC8541) \ 180 || defined(CONFIG_MPC8548) \ 181 || defined(CONFIG_MPC8555) 182/* DUART Registers(0x4000-0x5000) */ 183typedef struct ccsr_duart { 184 char res1[1280]; 185 u_char urbr1_uthr1_udlb1;/* 0x4500 - URBR1, UTHR1, UDLB1 with the same address offset of 0x04500 */ 186 u_char uier1_udmb1; /* 0x4501 - UIER1, UDMB1 with the same address offset of 0x04501 */ 187 u_char uiir1_ufcr1_uafr1;/* 0x4502 - UIIR1, UFCR1, UAFR1 with the same address offset of 0x04502 */ 188 u_char ulcr1; /* 0x4503 - UART1 Line Control Register */ 189 u_char umcr1; /* 0x4504 - UART1 Modem Control Register */ 190 u_char ulsr1; /* 0x4505 - UART1 Line Status Register */ 191 u_char umsr1; /* 0x4506 - UART1 Modem Status Register */ 192 u_char uscr1; /* 0x4507 - UART1 Scratch Register */ 193 char res2[8]; 194 u_char udsr1; /* 0x4510 - UART1 DMA Status Register */ 195 char res3[239]; 196 u_char urbr2_uthr2_udlb2;/* 0x4600 - URBR2, UTHR2, UDLB2 with the same address offset of 0x04600 */ 197 u_char uier2_udmb2; /* 0x4601 - UIER2, UDMB2 with the same address offset of 0x04601 */ 198 u_char uiir2_ufcr2_uafr2;/* 0x4602 - UIIR2, UFCR2, UAFR2 with the same address offset of 0x04602 */ 199 u_char ulcr2; /* 0x4603 - UART2 Line Control Register */ 200 u_char umcr2; /* 0x4604 - UART2 Modem Control Register */ 201 u_char ulsr2; /* 0x4605 - UART2 Line Status Register */ 202 u_char umsr2; /* 0x4606 - UART2 Modem Status Register */ 203 u_char uscr2; /* 0x4607 - UART2 Scratch Register */ 204 char res4[8]; 205 u_char udsr2; /* 0x4610 - UART2 DMA Status Register */ 206 char res5[2543]; 207} ccsr_duart_t; 208#else /* MPC8560 uses UART on its CPM */ 209typedef struct ccsr_duart { 210 char res[4096]; 211} ccsr_duart_t; 212#endif 213 214/* Local Bus Controller Registers(0x5000-0x6000) */ 215/* Omitting OCeaN(0x6000) and Reserved(0x7000) block */ 216 217typedef struct ccsr_lbc { 218 uint br0; /* 0x5000 - LBC Base Register 0 */ 219 uint or0; /* 0x5004 - LBC Options Register 0 */ 220 uint br1; /* 0x5008 - LBC Base Register 1 */ 221 uint or1; /* 0x500c - LBC Options Register 1 */ 222 uint br2; /* 0x5010 - LBC Base Register 2 */ 223 uint or2; /* 0x5014 - LBC Options Register 2 */ 224 uint br3; /* 0x5018 - LBC Base Register 3 */ 225 uint or3; /* 0x501c - LBC Options Register 3 */ 226 uint br4; /* 0x5020 - LBC Base Register 4 */ 227 uint or4; /* 0x5024 - LBC Options Register 4 */ 228 uint br5; /* 0x5028 - LBC Base Register 5 */ 229 uint or5; /* 0x502c - LBC Options Register 5 */ 230 uint br6; /* 0x5030 - LBC Base Register 6 */ 231 uint or6; /* 0x5034 - LBC Options Register 6 */ 232 uint br7; /* 0x5038 - LBC Base Register 7 */ 233 uint or7; /* 0x503c - LBC Options Register 7 */ 234 char res1[40]; 235 uint mar; /* 0x5068 - LBC UPM Address Register */ 236 char res2[4]; 237 uint mamr; /* 0x5070 - LBC UPMA Mode Register */ 238 uint mbmr; /* 0x5074 - LBC UPMB Mode Register */ 239 uint mcmr; /* 0x5078 - LBC UPMC Mode Register */ 240 char res3[8]; 241 uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */ 242 uint mdr; /* 0x5088 - LBC UPM Data Register */ 243 char res4[8]; 244 uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */ 245 char res5[8]; 246 uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */ 247 uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */ 248 char res6[8]; 249 uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */ 250 uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */ 251 uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */ 252 uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */ 253 uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */ 254 char res7[12]; 255 uint lbcr; /* 0x50d0 - LBC Configuration Register */ 256 uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */ 257 char res8[3880]; 258} ccsr_lbc_t; 259 260/* 261 * eSPI Registers(0x7000-0x8000) 262 */ 263typedef struct ccsr_espi { 264 uint mode; /* 0x00 - eSPI mode register */ 265 uint event; /* 0x04 - eSPI event register */ 266 uint mask; /* 0x08 - eSPI mask register */ 267 uint com; /* 0x0c - eSPI command register */ 268 uint tx; /* 0x10 - eSPI transmit FIFO access register */ 269 uint rx; /* 0x14 - eSPI receive FIFO access register */ 270 char res1[8]; /* reserved */ 271 uint csmode[4]; /* 0x20 - 0x2c: sSPI CS0/1/2/3 mode register */ 272 char res2[4048]; /* fill up to 0x1000 */ 273} ccsr_espi_t; 274 275/* 276 * PCI Registers(0x8000-0x9000) 277 */ 278typedef struct ccsr_pcix { 279 uint cfg_addr; /* 0x8000 - PCIX Configuration Address Register */ 280 uint cfg_data; /* 0x8004 - PCIX Configuration Data Register */ 281 uint int_ack; /* 0x8008 - PCIX Interrupt Acknowledge Register */ 282 char res1[3060]; 283 uint potar0; /* 0x8c00 - PCIX Outbound Transaction Address Register 0 */ 284 uint potear0; /* 0x8c04 - PCIX Outbound Translation Extended Address Register 0 */ 285 uint powbar0; /* 0x8c08 - PCIX Outbound Window Base Address Register 0 */ 286 uint powbear0; /* 0x8c0c - PCIX Outbound Window Base Extended Address Register 0 */ 287 uint powar0; /* 0x8c10 - PCIX Outbound Window Attributes Register 0 */ 288 char res2[12]; 289 uint potar1; /* 0x8c20 - PCIX Outbound Transaction Address Register 1 */ 290 uint potear1; /* 0x8c24 - PCIX Outbound Translation Extended Address Register 1 */ 291 uint powbar1; /* 0x8c28 - PCIX Outbound Window Base Address Register 1 */ 292 uint powbear1; /* 0x8c2c - PCIX Outbound Window Base Extended Address Register 1 */ 293 uint powar1; /* 0x8c30 - PCIX Outbound Window Attributes Register 1 */ 294 char res3[12]; 295 uint potar2; /* 0x8c40 - PCIX Outbound Transaction Address Register 2 */ 296 uint potear2; /* 0x8c44 - PCIX Outbound Translation Extended Address Register 2 */ 297 uint powbar2; /* 0x8c48 - PCIX Outbound Window Base Address Register 2 */ 298 uint powbear2; /* 0x8c4c - PCIX Outbound Window Base Extended Address Register 2 */ 299 uint powar2; /* 0x8c50 - PCIX Outbound Window Attributes Register 2 */ 300 char res4[12]; 301 uint potar3; /* 0x8c60 - PCIX Outbound Transaction Address Register 3 */ 302 uint potear3; /* 0x8c64 - PCIX Outbound Translation Extended Address Register 3 */ 303 uint powbar3; /* 0x8c68 - PCIX Outbound Window Base Address Register 3 */ 304 uint powbear3; /* 0x8c6c - PCIX Outbound Window Base Extended Address Register 3 */ 305 uint powar3; /* 0x8c70 - PCIX Outbound Window Attributes Register 3 */ 306 char res5[12]; 307 uint potar4; /* 0x8c80 - PCIX Outbound Transaction Address Register 4 */ 308 uint potear4; /* 0x8c84 - PCIX Outbound Translation Extended Address Register 4 */ 309 uint powbar4; /* 0x8c88 - PCIX Outbound Window Base Address Register 4 */ 310 uint powbear4; /* 0x8c8c - PCIX Outbound Window Base Extended Address Register 4 */ 311 uint powar4; /* 0x8c90 - PCIX Outbound Window Attributes Register 4 */ 312 char res6[268]; 313 uint pitar3; /* 0x8da0 - PCIX Inbound Translation Address Register 3 */ 314 uint pitear3; /* 0x8da4 - PCIX Inbound Translation Extended Address Register 3 */ 315 uint piwbar3; /* 0x8da8 - PCIX Inbound Window Base Address Register 3 */ 316 uint piwbear3; /* 0x8dac - PCIX Inbound Window Base Extended Address Register 3 */ 317 uint piwar3; /* 0x8db0 - PCIX Inbound Window Attributes Register 3 */ 318 char res7[12]; 319 uint pitar2; /* 0x8dc0 - PCIX Inbound Translation Address Register 2 */ 320 uint pitear2; /* 0x8dc4 - PCIX Inbound Translation Extended Address Register 2 */ 321 uint piwbar2; /* 0x8dc8 - PCIX Inbound Window Base Address Register 2 */ 322 uint piwbear2; /* 0x8dcc - PCIX Inbound Window Base Extended Address Register 2 */ 323 uint piwar2; /* 0x8dd0 - PCIX Inbound Window Attributes Register 2 */ 324 char res8[12]; 325 uint pitar1; /* 0x8de0 - PCIX Inbound Translation Address Register 1 */ 326 uint pitear1; /* 0x8de4 - PCIX Inbound Translation Extended Address Register 1 */ 327 uint piwbar1; /* 0x8de8 - PCIX Inbound Window Base Address Register 1 */ 328 char res9[4]; 329 uint piwar1; /* 0x8df0 - PCIX Inbound Window Attributes Register 1 */ 330 char res10[12]; 331 uint pedr; /* 0x8e00 - PCIX Error Detect Register */ 332 uint pecdr; /* 0x8e04 - PCIX Error Capture Disable Register */ 333 uint peer; /* 0x8e08 - PCIX Error Enable Register */ 334 uint peattrcr; /* 0x8e0c - PCIX Error Attributes Capture Register */ 335 uint peaddrcr; /* 0x8e10 - PCIX Error Address Capture Register */ 336 uint peextaddrcr; /* 0x8e14 - PCIX Error Extended Address Capture Register */ 337 uint pedlcr; /* 0x8e18 - PCIX Error Data Low Capture Register */ 338 uint pedhcr; /* 0x8e1c - PCIX Error Error Data High Capture Register */ 339 uint gas_timr; /* 0x8e20 - PCIX Gasket Timer Register */ 340 char res11[476]; 341} ccsr_pcix_t; 342 343#define PCIX_COMMAND 0x62 344#define POWAR_EN 0x80000000 345#define POWAR_IO_READ 0x00080000 346#define POWAR_MEM_READ 0x00040000 347#define POWAR_IO_WRITE 0x00008000 348#define POWAR_MEM_WRITE 0x00004000 349#define POWAR_MEM_512M 0x0000001c 350#define POWAR_IO_1M 0x00000013 351 352#define PIWAR_EN 0x80000000 353#define PIWAR_PF 0x20000000 354#define PIWAR_LOCAL 0x00f00000 355#define PIWAR_READ_SNOOP 0x00050000 356#define PIWAR_WRITE_SNOOP 0x00005000 357#define PIWAR_MEM_2G 0x0000001e 358 359 360/* 361 * L2 Cache Registers(0x2_0000-0x2_1000) 362 */ 363typedef struct ccsr_l2cache { 364 uint l2ctl; /* 0x20000 - L2 configuration register 0 */ 365 char res1[12]; 366 uint l2cewar0; /* 0x20010 - L2 cache external write address register 0 */ 367 char res2[4]; 368 uint l2cewcr0; /* 0x20018 - L2 cache external write control register 0 */ 369 char res3[4]; 370 uint l2cewar1; /* 0x20020 - L2 cache external write address register 1 */ 371 char res4[4]; 372 uint l2cewcr1; /* 0x20028 - L2 cache external write control register 1 */ 373 char res5[4]; 374 uint l2cewar2; /* 0x20030 - L2 cache external write address register 2 */ 375 char res6[4]; 376 uint l2cewcr2; /* 0x20038 - L2 cache external write control register 2 */ 377 char res7[4]; 378 uint l2cewar3; /* 0x20040 - L2 cache external write address register 3 */ 379 char res8[4]; 380 uint l2cewcr3; /* 0x20048 - L2 cache external write control register 3 */ 381 char res9[180]; 382 uint l2srbar0; /* 0x20100 - L2 memory-mapped SRAM base address register 0 */ 383 char res10[4]; 384 uint l2srbar1; /* 0x20108 - L2 memory-mapped SRAM base address register 1 */ 385 char res11[3316]; 386 uint l2errinjhi; /* 0x20e00 - L2 error injection mask high register */ 387 uint l2errinjlo; /* 0x20e04 - L2 error injection mask low register */ 388 uint l2errinjctl; /* 0x20e08 - L2 error injection tag/ECC control register */ 389 char res12[20]; 390 uint l2captdatahi; /* 0x20e20 - L2 error data high capture register */ 391 uint l2captdatalo; /* 0x20e24 - L2 error data low capture register */ 392 uint l2captecc; /* 0x20e28 - L2 error ECC capture register */ 393 char res13[20]; 394 uint l2errdet; /* 0x20e40 - L2 error detect register */ 395 uint l2errdis; /* 0x20e44 - L2 error disable register */ 396 uint l2errinten; /* 0x20e48 - L2 error interrupt enable register */ 397 uint l2errattr; /* 0x20e4c - L2 error attributes capture register */ 398 uint l2erraddr; /* 0x20e50 - L2 error address capture register */ 399 char res14[4]; 400 uint l2errctl; /* 0x20e58 - L2 error control register */ 401 char res15[420]; 402} ccsr_l2cache_t; 403 404/* 405 * DMA Registers(0x2_1000-0x2_2000) 406 */ 407typedef struct ccsr_dma { 408 char res1[256]; 409 uint mr0; /* 0x21100 - DMA 0 Mode Register */ 410 uint sr0; /* 0x21104 - DMA 0 Status Register */ 411 char res2[4]; 412 uint clndar0; /* 0x2110c - DMA 0 Current Link Descriptor Address Register */ 413 uint satr0; /* 0x21110 - DMA 0 Source Attributes Register */ 414 uint sar0; /* 0x21114 - DMA 0 Source Address Register */ 415 uint datr0; /* 0x21118 - DMA 0 Destination Attributes Register */ 416 uint dar0; /* 0x2111c - DMA 0 Destination Address Register */ 417 uint bcr0; /* 0x21120 - DMA 0 Byte Count Register */ 418 char res3[4]; 419 uint nlndar0; /* 0x21128 - DMA 0 Next Link Descriptor Address Register */ 420 char res4[8]; 421 uint clabdar0; /* 0x21134 - DMA 0 Current List - Alternate Base Descriptor Address Register */ 422 char res5[4]; 423 uint nlsdar0; /* 0x2113c - DMA 0 Next List Descriptor Address Register */ 424 uint ssr0; /* 0x21140 - DMA 0 Source Stride Register */ 425 uint dsr0; /* 0x21144 - DMA 0 Destination Stride Register */ 426 char res6[56]; 427 uint mr1; /* 0x21180 - DMA 1 Mode Register */ 428 uint sr1; /* 0x21184 - DMA 1 Status Register */ 429 char res7[4]; 430 uint clndar1; /* 0x2118c - DMA 1 Current Link Descriptor Address Register */ 431 uint satr1; /* 0x21190 - DMA 1 Source Attributes Register */ 432 uint sar1; /* 0x21194 - DMA 1 Source Address Register */ 433 uint datr1; /* 0x21198 - DMA 1 Destination Attributes Register */ 434 uint dar1; /* 0x2119c - DMA 1 Destination Address Register */ 435 uint bcr1; /* 0x211a0 - DMA 1 Byte Count Register */ 436 char res8[4]; 437 uint nlndar1; /* 0x211a8 - DMA 1 Next Link Descriptor Address Register */ 438 char res9[8]; 439 uint clabdar1; /* 0x211b4 - DMA 1 Current List - Alternate Base Descriptor Address Register */ 440 char res10[4]; 441 uint nlsdar1; /* 0x211bc - DMA 1 Next List Descriptor Address Register */ 442 uint ssr1; /* 0x211c0 - DMA 1 Source Stride Register */ 443 uint dsr1; /* 0x211c4 - DMA 1 Destination Stride Register */ 444 char res11[56]; 445 uint mr2; /* 0x21200 - DMA 2 Mode Register */ 446 uint sr2; /* 0x21204 - DMA 2 Status Register */ 447 char res12[4]; 448 uint clndar2; /* 0x2120c - DMA 2 Current Link Descriptor Address Register */ 449 uint satr2; /* 0x21210 - DMA 2 Source Attributes Register */ 450 uint sar2; /* 0x21214 - DMA 2 Source Address Register */ 451 uint datr2; /* 0x21218 - DMA 2 Destination Attributes Register */ 452 uint dar2; /* 0x2121c - DMA 2 Destination Address Register */ 453 uint bcr2; /* 0x21220 - DMA 2 Byte Count Register */ 454 char res13[4]; 455 uint nlndar2; /* 0x21228 - DMA 2 Next Link Descriptor Address Register */ 456 char res14[8]; 457 uint clabdar2; /* 0x21234 - DMA 2 Current List - Alternate Base Descriptor Address Register */ 458 char res15[4]; 459 uint nlsdar2; /* 0x2123c - DMA 2 Next List Descriptor Address Register */ 460 uint ssr2; /* 0x21240 - DMA 2 Source Stride Register */ 461 uint dsr2; /* 0x21244 - DMA 2 Destination Stride Register */ 462 char res16[56]; 463 uint mr3; /* 0x21280 - DMA 3 Mode Register */ 464 uint sr3; /* 0x21284 - DMA 3 Status Register */ 465 char res17[4]; 466 uint clndar3; /* 0x2128c - DMA 3 Current Link Descriptor Address Register */ 467 uint satr3; /* 0x21290 - DMA 3 Source Attributes Register */ 468 uint sar3; /* 0x21294 - DMA 3 Source Address Register */ 469 uint datr3; /* 0x21298 - DMA 3 Destination Attributes Register */ 470 uint dar3; /* 0x2129c - DMA 3 Destination Address Register */ 471 uint bcr3; /* 0x212a0 - DMA 3 Byte Count Register */ 472 char res18[4]; 473 uint nlndar3; /* 0x212a8 - DMA 3 Next Link Descriptor Address Register */ 474 char res19[8]; 475 uint clabdar3; /* 0x212b4 - DMA 3 Current List - Alternate Base Descriptor Address Register */ 476 char res20[4]; 477 uint nlsdar3; /* 0x212bc - DMA 3 Next List Descriptor Address Register */ 478 uint ssr3; /* 0x212c0 - DMA 3 Source Stride Register */ 479 uint dsr3; /* 0x212c4 - DMA 3 Destination Stride Register */ 480 char res21[56]; 481 uint dgsr; /* 0x21300 - DMA General Status Register */ 482 char res22[11516]; 483} ccsr_dma_t; 484 485/* 486 * tsec1 tsec2: 24000-26000 487 */ 488typedef struct ccsr_tsec { 489 char res1[16]; 490 uint ievent; /* 0x24010 - Interrupt Event Register */ 491 uint imask; /* 0x24014 - Interrupt Mask Register */ 492 uint edis; /* 0x24018 - Error Disabled Register */ 493 char res2[4]; 494 uint ecntrl; /* 0x24020 - Ethernet Control Register */ 495 uint minflr; /* 0x24024 - Minimum Frame Length Register */ 496 uint ptv; /* 0x24028 - Pause Time Value Register */ 497 uint dmactrl; /* 0x2402c - DMA Control Register */ 498 uint tbipa; /* 0x24030 - TBI PHY Address Register */ 499 char res3[88]; 500 uint fifo_tx_thr; /* 0x2408c - FIFO transmit threshold register */ 501 char res4[8]; 502 uint fifo_tx_starve; /* 0x24098 - FIFO transmit starve register */ 503 uint fifo_tx_starve_shutoff; /* 0x2409c - FIFO transmit starve shutoff register */ 504 char res5[96]; 505 uint tctrl; /* 0x24100 - Transmit Control Register */ 506 uint tstat; /* 0x24104 - Transmit Status Register */ 507 char res6[4]; 508 uint tbdlen; /* 0x2410c - Transmit Buffer Descriptor Data Length Register */ 509 char res7[16]; 510 uint ctbptrh; /* 0x24120 - Current Transmit Buffer Descriptor Pointer High Register */ 511 uint ctbptr; /* 0x24124 - Current Transmit Buffer Descriptor Pointer Register */ 512 char res8[88]; 513 uint tbptrh; /* 0x24180 - Transmit Buffer Descriptor Pointer High Register */ 514 uint tbptr; /* 0x24184 - Transmit Buffer Descriptor Pointer Low Register */ 515 char res9[120]; 516 uint tbaseh; /* 0x24200 - Transmit Descriptor Base Address High Register */ 517 uint tbase; /* 0x24204 - Transmit Descriptor Base Address Register */ 518 char res10[168]; 519 uint ostbd; /* 0x242b0 - Out-of-Sequence Transmit Buffer Descriptor Register */ 520 uint ostbdp; /* 0x242b4 - Out-of-Sequence Transmit Data Buffer Pointer Register */ 521 uint os32tbdp; /* 0x242b8 - Out-of-Sequence 32 Bytes Transmit Data Buffer Pointer Low Register */ 522 uint os32iptrh; /* 0x242bc - Out-of-Sequence 32 Bytes Transmit Insert Pointer High Register */ 523 uint os32iptrl; /* 0x242c0 - Out-of-Sequence 32 Bytes Transmit Insert Pointer Low Register */ 524 uint os32tbdr; /* 0x242c4 - Out-of-Sequence 32 Bytes Transmit Reserved Register */ 525 uint os32iil; /* 0x242c8 - Out-of-Sequence 32 Bytes Transmit Insert Index/Length Register */ 526 char res11[52]; 527 uint rctrl; /* 0x24300 - Receive Control Register */ 528 uint rstat; /* 0x24304 - Receive Status Register */ 529 char res12[4]; 530 uint rbdlen; /* 0x2430c - RxBD Data Length Register */ 531 char res13[16]; 532 uint crbptrh; /* 0x24320 - Current Receive Buffer Descriptor Pointer High */ 533 uint crbptr; /* 0x24324 - Current Receive Buffer Descriptor Pointer */ 534 char res14[24]; 535 uint mrblr; /* 0x24340 - Maximum Receive Buffer Length Register */ 536 uint mrblr2r3; /* 0x24344 - Maximum Receive Buffer Length R2R3 Register */ 537 char res15[56]; 538 uint rbptrh; /* 0x24380 - Receive Buffer Descriptor Pointer High 0 */ 539 uint rbptr; /* 0x24384 - Receive Buffer Descriptor Pointer */ 540 uint rbptrh1; /* 0x24388 - Receive Buffer Descriptor Pointer High 1 */ 541 uint rbptrl1; /* 0x2438c - Receive Buffer Descriptor Pointer Low 1 */ 542 uint rbptrh2; /* 0x24390 - Receive Buffer Descriptor Pointer High 2 */ 543 uint rbptrl2; /* 0x24394 - Receive Buffer Descriptor Pointer Low 2 */ 544 uint rbptrh3; /* 0x24398 - Receive Buffer Descriptor Pointer High 3 */ 545 uint rbptrl3; /* 0x2439c - Receive Buffer Descriptor Pointer Low 3 */ 546 char res16[96]; 547 uint rbaseh; /* 0x24400 - Receive Descriptor Base Address High 0 */ 548 uint rbase; /* 0x24404 - Receive Descriptor Base Address */ 549 uint rbaseh1; /* 0x24408 - Receive Descriptor Base Address High 1 */ 550 uint rbasel1; /* 0x2440c - Receive Descriptor Base Address Low 1 */ 551 uint rbaseh2; /* 0x24410 - Receive Descriptor Base Address High 2 */ 552 uint rbasel2; /* 0x24414 - Receive Descriptor Base Address Low 2 */ 553 uint rbaseh3; /* 0x24418 - Receive Descriptor Base Address High 3 */ 554 uint rbasel3; /* 0x2441c - Receive Descriptor Base Address Low 3 */ 555 char res17[224]; 556 uint maccfg1; /* 0x24500 - MAC Configuration 1 Register */ 557 uint maccfg2; /* 0x24504 - MAC Configuration 2 Register */ 558 uint ipgifg; /* 0x24508 - Inter Packet Gap/Inter Frame Gap Register */ 559 uint hafdup; /* 0x2450c - Half Duplex Register */ 560 uint maxfrm; /* 0x24510 - Maximum Frame Length Register */ 561 char res18[12]; 562 uint miimcfg; /* 0x24520 - MII Management Configuration Register */ 563 uint miimcom; /* 0x24524 - MII Management Command Register */ 564 uint miimadd; /* 0x24528 - MII Management Address Register */ 565 uint miimcon; /* 0x2452c - MII Management Control Register */ 566 uint miimstat; /* 0x24530 - MII Management Status Register */ 567 uint miimind; /* 0x24534 - MII Management Indicator Register */ 568 char res19[4]; 569 uint ifstat; /* 0x2453c - Interface Status Register */ 570 uint macstnaddr1; /* 0x24540 - Station Address Part 1 Register */ 571 uint macstnaddr2; /* 0x24544 - Station Address Part 2 Register */ 572 char res20[312]; 573 uint tr64; /* 0x24680 - Transmit and Receive 64-byte Frame Counter */ 574 uint tr127; /* 0x24684 - Transmit and Receive 65-127 byte Frame Counter */ 575 uint tr255; /* 0x24688 - Transmit and Receive 128-255 byte Frame Counter */ 576 uint tr511; /* 0x2468c - Transmit and Receive 256-511 byte Frame Counter */ 577 uint tr1k; /* 0x24690 - Transmit and Receive 512-1023 byte Frame Counter */ 578 uint trmax; /* 0x24694 - Transmit and Receive 1024-1518 byte Frame Counter */ 579 uint trmgv; /* 0x24698 - Transmit and Receive 1519-1522 byte Good VLAN Frame */ 580 uint rbyt; /* 0x2469c - Receive Byte Counter */ 581 uint rpkt; /* 0x246a0 - Receive Packet Counter */ 582 uint rfcs; /* 0x246a4 - Receive FCS Error Counter */ 583 uint rmca; /* 0x246a8 - Receive Multicast Packet Counter */ 584 uint rbca; /* 0x246ac - Receive Broadcast Packet Counter */ 585 uint rxcf; /* 0x246b0 - Receive Control Frame Packet Counter */ 586 uint rxpf; /* 0x246b4 - Receive Pause Frame Packet Counter */ 587 uint rxuo; /* 0x246b8 - Receive Unknown OP Code Counter */ 588 uint raln; /* 0x246bc - Receive Alignment Error Counter */ 589 uint rflr; /* 0x246c0 - Receive Frame Length Error Counter */ 590 uint rcde; /* 0x246c4 - Receive Code Error Counter */ 591 uint rcse; /* 0x246c8 - Receive Carrier Sense Error Counter */ 592 uint rund; /* 0x246cc - Receive Undersize Packet Counter */ 593 uint rovr; /* 0x246d0 - Receive Oversize Packet Counter */ 594 uint rfrg; /* 0x246d4 - Receive Fragments Counter */ 595 uint rjbr; /* 0x246d8 - Receive Jabber Counter */ 596 uint rdrp; /* 0x246dc - Receive Drop Counter */ 597 uint tbyt; /* 0x246e0 - Transmit Byte Counter Counter */ 598 uint tpkt; /* 0x246e4 - Transmit Packet Counter */ 599 uint tmca; /* 0x246e8 - Transmit Multicast Packet Counter */ 600 uint tbca; /* 0x246ec - Transmit Broadcast Packet Counter */ 601 uint txpf; /* 0x246f0 - Transmit Pause Control Frame Counter */ 602 uint tdfr; /* 0x246f4 - Transmit Deferral Packet Counter */ 603 uint tedf; /* 0x246f8 - Transmit Excessive Deferral Packet Counter */ 604 uint tscl; /* 0x246fc - Transmit Single Collision Packet Counter */ 605 uint tmcl; /* 0x24700 - Transmit Multiple Collision Packet Counter */ 606 uint tlcl; /* 0x24704 - Transmit Late Collision Packet Counter */ 607 uint txcl; /* 0x24708 - Transmit Excessive Collision Packet Counter */ 608 uint tncl; /* 0x2470c - Transmit Total Collision Counter */ 609 char res21[4]; 610 uint tdrp; /* 0x24714 - Transmit Drop Frame Counter */ 611 uint tjbr; /* 0x24718 - Transmit Jabber Frame Counter */ 612 uint tfcs; /* 0x2471c - Transmit FCS Error Counter */ 613 uint txcf; /* 0x24720 - Transmit Control Frame Counter */ 614 uint tovr; /* 0x24724 - Transmit Oversize Frame Counter */ 615 uint tund; /* 0x24728 - Transmit Undersize Frame Counter */ 616 uint tfrg; /* 0x2472c - Transmit Fragments Frame Counter */ 617 uint car1; /* 0x24730 - Carry Register One */ 618 uint car2; /* 0x24734 - Carry Register Two */ 619 uint cam1; /* 0x24738 - Carry Mask Register One */ 620 uint cam2; /* 0x2473c - Carry Mask Register Two */ 621 char res22[192]; 622 uint iaddr0; /* 0x24800 - Indivdual address register 0 */ 623 uint iaddr1; /* 0x24804 - Indivdual address register 1 */ 624 uint iaddr2; /* 0x24808 - Indivdual address register 2 */ 625 uint iaddr3; /* 0x2480c - Indivdual address register 3 */ 626 uint iaddr4; /* 0x24810 - Indivdual address register 4 */ 627 uint iaddr5; /* 0x24814 - Indivdual address register 5 */ 628 uint iaddr6; /* 0x24818 - Indivdual address register 6 */ 629 uint iaddr7; /* 0x2481c - Indivdual address register 7 */ 630 char res23[96]; 631 uint gaddr0; /* 0x24880 - Global address register 0 */ 632 uint gaddr1; /* 0x24884 - Global address register 1 */ 633 uint gaddr2; /* 0x24888 - Global address register 2 */ 634 uint gaddr3; /* 0x2488c - Global address register 3 */ 635 uint gaddr4; /* 0x24890 - Global address register 4 */ 636 uint gaddr5; /* 0x24894 - Global address register 5 */ 637 uint gaddr6; /* 0x24898 - Global address register 6 */ 638 uint gaddr7; /* 0x2489c - Global address register 7 */ 639 char res24[96]; 640 uint pmd0; /* 0x24900 - Pattern Match Data Register */ 641 char res25[4]; 642 uint pmask0; /* 0x24908 - Pattern Mask Register */ 643 char res26[4]; 644 uint pcntrl0; /* 0x24910 - Pattern Match Control Register */ 645 char res27[4]; 646 uint pattrb0; /* 0x24918 - Pattern Match Attributes Register */ 647 uint pattrbeli0; /* 0x2491c - Pattern Match Attributes Extract Length and Extract Index Register */ 648 uint pmd1; /* 0x24920 - Pattern Match Data Register */ 649 char res28[4]; 650 uint pmask1; /* 0x24928 - Pattern Mask Register */ 651 char res29[4]; 652 uint pcntrl1; /* 0x24930 - Pattern Match Control Register */ 653 char res30[4]; 654 uint pattrb1; /* 0x24938 - Pattern Match Attributes Register */ 655 uint pattrbeli1; /* 0x2493c - Pattern Match Attributes Extract Length and Extract Index Register */ 656 uint pmd2; /* 0x24940 - Pattern Match Data Register */ 657 char res31[4]; 658 uint pmask2; /* 0x24948 - Pattern Mask Register */ 659 char res32[4]; 660 uint pcntrl2; /* 0x24950 - Pattern Match Control Register */ 661 char res33[4]; 662 uint pattrb2; /* 0x24958 - Pattern Match Attributes Register */ 663 uint pattrbeli2; /* 0x2495c - Pattern Match Attributes Extract Length and Extract Index Register */ 664 uint pmd3; /* 0x24960 - Pattern Match Data Register */ 665 char res34[4]; 666 uint pmask3; /* 0x24968 - Pattern Mask Register */ 667 char res35[4]; 668 uint pcntrl3; /* 0x24970 - Pattern Match Control Register */ 669 char res36[4]; 670 uint pattrb3; /* 0x24978 - Pattern Match Attributes Register */ 671 uint pattrbeli3; /* 0x2497c - Pattern Match Attributes Extract Length and Extract Index Register */ 672 uint pmd4; /* 0x24980 - Pattern Match Data Register */ 673 char res37[4]; 674 uint pmask4; /* 0x24988 - Pattern Mask Register */ 675 char res38[4]; 676 uint pcntrl4; /* 0x24990 - Pattern Match Control Register */ 677 char res39[4]; 678 uint pattrb4; /* 0x24998 - Pattern Match Attributes Register */ 679 uint pattrbeli4; /* 0x2499c - Pattern Match Attributes Extract Length and Extract Index Register */ 680 uint pmd5; /* 0x249a0 - Pattern Match Data Register */ 681 char res40[4]; 682 uint pmask5; /* 0x249a8 - Pattern Mask Register */ 683 char res41[4]; 684 uint pcntrl5; /* 0x249b0 - Pattern Match Control Register */ 685 char res42[4]; 686 uint pattrb5; /* 0x249b8 - Pattern Match Attributes Register */ 687 uint pattrbeli5; /* 0x249bc - Pattern Match Attributes Extract Length and Extract Index Register */ 688 uint pmd6; /* 0x249c0 - Pattern Match Data Register */ 689 char res43[4]; 690 uint pmask6; /* 0x249c8 - Pattern Mask Register */ 691 char res44[4]; 692 uint pcntrl6; /* 0x249d0 - Pattern Match Control Register */ 693 char res45[4]; 694 uint pattrb6; /* 0x249d8 - Pattern Match Attributes Register */ 695 uint pattrbeli6; /* 0x249dc - Pattern Match Attributes Extract Length and Extract Index Register */ 696 uint pmd7; /* 0x249e0 - Pattern Match Data Register */ 697 char res46[4]; 698 uint pmask7; /* 0x249e8 - Pattern Mask Register */ 699 char res47[4]; 700 uint pcntrl7; /* 0x249f0 - Pattern Match Control Register */ 701 char res48[4]; 702 uint pattrb7; /* 0x249f8 - Pattern Match Attributes Register */ 703 uint pattrbeli7; /* 0x249fc - Pattern Match Attributes Extract Length and Extract Index Register */ 704 uint pmd8; /* 0x24a00 - Pattern Match Data Register */ 705 char res49[4]; 706 uint pmask8; /* 0x24a08 - Pattern Mask Register */ 707 char res50[4]; 708 uint pcntrl8; /* 0x24a10 - Pattern Match Control Register */ 709 char res51[4]; 710 uint pattrb8; /* 0x24a18 - Pattern Match Attributes Register */ 711 uint pattrbeli8; /* 0x24a1c - Pattern Match Attributes Extract Length and Extract Index Register */ 712 uint pmd9; /* 0x24a20 - Pattern Match Data Register */ 713 char res52[4]; 714 uint pmask9; /* 0x24a28 - Pattern Mask Register */ 715 char res53[4]; 716 uint pcntrl9; /* 0x24a30 - Pattern Match Control Register */ 717 char res54[4]; 718 uint pattrb9; /* 0x24a38 - Pattern Match Attributes Register */ 719 uint pattrbeli9; /* 0x24a3c - Pattern Match Attributes Extract Length and Extract Index Register */ 720 uint pmd10; /* 0x24a40 - Pattern Match Data Register */ 721 char res55[4]; 722 uint pmask10; /* 0x24a48 - Pattern Mask Register */ 723 char res56[4]; 724 uint pcntrl10; /* 0x24a50 - Pattern Match Control Register */ 725 char res57[4]; 726 uint pattrb10; /* 0x24a58 - Pattern Match Attributes Register */ 727 uint pattrbeli10; /* 0x24a5c - Pattern Match Attributes Extract Length and Extract Index Register */ 728 uint pmd11; /* 0x24a60 - Pattern Match Data Register */ 729 char res58[4]; 730 uint pmask11; /* 0x24a68 - Pattern Mask Register */ 731 char res59[4]; 732 uint pcntrl11; /* 0x24a70 - Pattern Match Control Register */ 733 char res60[4]; 734 uint pattrb11; /* 0x24a78 - Pattern Match Attributes Register */ 735 uint pattrbeli11; /* 0x24a7c - Pattern Match Attributes Extract Length and Extract Index Register */ 736 uint pmd12; /* 0x24a80 - Pattern Match Data Register */ 737 char res61[4]; 738 uint pmask12; /* 0x24a88 - Pattern Mask Register */ 739 char res62[4]; 740 uint pcntrl12; /* 0x24a90 - Pattern Match Control Register */ 741 char res63[4]; 742 uint pattrb12; /* 0x24a98 - Pattern Match Attributes Register */ 743 uint pattrbeli12; /* 0x24a9c - Pattern Match Attributes Extract Length and Extract Index Register */ 744 uint pmd13; /* 0x24aa0 - Pattern Match Data Register */ 745 char res64[4]; 746 uint pmask13; /* 0x24aa8 - Pattern Mask Register */ 747 char res65[4]; 748 uint pcntrl13; /* 0x24ab0 - Pattern Match Control Register */ 749 char res66[4]; 750 uint pattrb13; /* 0x24ab8 - Pattern Match Attributes Register */ 751 uint pattrbeli13; /* 0x24abc - Pattern Match Attributes Extract Length and Extract Index Register */ 752 uint pmd14; /* 0x24ac0 - Pattern Match Data Register */ 753 char res67[4]; 754 uint pmask14; /* 0x24ac8 - Pattern Mask Register */ 755 char res68[4]; 756 uint pcntrl14; /* 0x24ad0 - Pattern Match Control Register */ 757 char res69[4]; 758 uint pattrb14; /* 0x24ad8 - Pattern Match Attributes Register */ 759 uint pattrbeli14; /* 0x24adc - Pattern Match Attributes Extract Length and Extract Index Register */ 760 uint pmd15; /* 0x24ae0 - Pattern Match Data Register */ 761 char res70[4]; 762 uint pmask15; /* 0x24ae8 - Pattern Mask Register */ 763 char res71[4]; 764 uint pcntrl15; /* 0x24af0 - Pattern Match Control Register */ 765 char res72[4]; 766 uint pattrb15; /* 0x24af8 - Pattern Match Attributes Register */ 767 uint pattrbeli15; /* 0x24afc - Pattern Match Attributes Extract Length and Extract Index Register */ 768 char res73[248]; 769 uint attr; /* 0x24bf8 - Attributes Register */ 770 uint attreli; /* 0x24bfc - Attributes Extract Length and Extract Index Register */ 771 char res74[1024]; 772} ccsr_tsec_t; 773 774/* 775 * PIC Registers(0x4_0000-0x8_0000) 776 */ 777typedef struct ccsr_pic { 778 char res1[64]; /* 0x40000 */ 779 uint ipidr0; /* 0x40040 - Interprocessor Interrupt Dispatch Register 0 */ 780 char res2[12]; 781 uint ipidr1; /* 0x40050 - Interprocessor Interrupt Dispatch Register 1 */ 782 char res3[12]; 783 uint ipidr2; /* 0x40060 - Interprocessor Interrupt Dispatch Register 2 */ 784 char res4[12]; 785 uint ipidr3; /* 0x40070 - Interprocessor Interrupt Dispatch Register 3 */ 786 char res5[12]; 787 uint ctpr; /* 0x40080 - Current Task Priority Register */ 788 char res6[12]; 789 uint whoami; /* 0x40090 - Who Am I Register */ 790 char res7[12]; 791 uint iack; /* 0x400a0 - Interrupt Acknowledge Register */ 792 char res8[12]; 793 uint eoi; /* 0x400b0 - End Of Interrupt Register */ 794 char res9[3916]; 795 uint frr; /* 0x41000 - Feature Reporting Register */ 796 char res10[28]; 797 uint gcr; /* 0x41020 - Global Configuration Register */ 798#define MPC85xx_PICGCR_RST 0x80000000 799#define MPC85xx_PICGCR_M 0x20000000 800 char res11[92]; 801 uint vir; /* 0x41080 - Vendor Identification Register */ 802 char res12[12]; 803 uint pir; /* 0x41090 - Processor Initialization Register */ 804 char res13[12]; 805 uint ipivpr0; /* 0x410a0 - IPI Vector/Priority Register 0 */ 806 char res14[12]; 807 uint ipivpr1; /* 0x410b0 - IPI Vector/Priority Register 1 */ 808 char res15[12]; 809 uint ipivpr2; /* 0x410c0 - IPI Vector/Priority Register 2 */ 810 char res16[12]; 811 uint ipivpr3; /* 0x410d0 - IPI Vector/Priority Register 3 */ 812 char res17[12]; 813 uint svr; /* 0x410e0 - Spurious Vector Register */ 814 char res18[12]; 815 uint tfrr; /* 0x410f0 - Timer Frequency Reporting Register */ 816 char res19[12]; 817 uint gtccr0; /* 0x41100 - Global Timer Current Count Register 0 */ 818 char res20[12]; 819 uint gtbcr0; /* 0x41110 - Global Timer Base Count Register 0 */ 820 char res21[12]; 821 uint gtvpr0; /* 0x41120 - Global Timer Vector/Priority Register 0 */ 822 char res22[12]; 823 uint gtdr0; /* 0x41130 - Global Timer Destination Register 0 */ 824 char res23[12]; 825 uint gtccr1; /* 0x41140 - Global Timer Current Count Register 1 */ 826 char res24[12]; 827 uint gtbcr1; /* 0x41150 - Global Timer Base Count Register 1 */ 828 char res25[12]; 829 uint gtvpr1; /* 0x41160 - Global Timer Vector/Priority Register 1 */ 830 char res26[12]; 831 uint gtdr1; /* 0x41170 - Global Timer Destination Register 1 */ 832 char res27[12]; 833 uint gtccr2; /* 0x41180 - Global Timer Current Count Register 2 */ 834 char res28[12]; 835 uint gtbcr2; /* 0x41190 - Global Timer Base Count Register 2 */ 836 char res29[12]; 837 uint gtvpr2; /* 0x411a0 - Global Timer Vector/Priority Register 2 */ 838 char res30[12]; 839 uint gtdr2; /* 0x411b0 - Global Timer Destination Register 2 */ 840 char res31[12]; 841 uint gtccr3; /* 0x411c0 - Global Timer Current Count Register 3 */ 842 char res32[12]; 843 uint gtbcr3; /* 0x411d0 - Global Timer Base Count Register 3 */ 844 char res33[12]; 845 uint gtvpr3; /* 0x411e0 - Global Timer Vector/Priority Register 3 */ 846 char res34[12]; 847 uint gtdr3; /* 0x411f0 - Global Timer Destination Register 3 */ 848 char res35[268]; 849 uint tcr; /* 0x41300 - Timer Control Register */ 850 char res36[12]; 851 uint irqsr0; /* 0x41310 - IRQ_OUT Summary Register 0 */ 852 char res37[12]; 853 uint irqsr1; /* 0x41320 - IRQ_OUT Summary Register 1 */ 854 char res38[12]; 855 uint cisr0; /* 0x41330 - Critical Interrupt Summary Register 0 */ 856 char res39[12]; 857 uint cisr1; /* 0x41340 - Critical Interrupt Summary Register 1 */ 858 char res40[188]; 859 uint msgr0; /* 0x41400 - Message Register 0 */ 860 char res41[12]; 861 uint msgr1; /* 0x41410 - Message Register 1 */ 862 char res42[12]; 863 uint msgr2; /* 0x41420 - Message Register 2 */ 864 char res43[12]; 865 uint msgr3; /* 0x41430 - Message Register 3 */ 866 char res44[204]; 867 uint mer; /* 0x41500 - Message Enable Register */ 868 char res45[12]; 869 uint msr; /* 0x41510 - Message Status Register */ 870 char res46[60140]; 871 uint eivpr0; /* 0x50000 - External Interrupt Vector/Priority Register 0 */ 872 char res47[12]; 873 uint eidr0; /* 0x50010 - External Interrupt Destination Register 0 */ 874 char res48[12]; 875 uint eivpr1; /* 0x50020 - External Interrupt Vector/Priority Register 1 */ 876 char res49[12]; 877 uint eidr1; /* 0x50030 - External Interrupt Destination Register 1 */ 878 char res50[12]; 879 uint eivpr2; /* 0x50040 - External Interrupt Vector/Priority Register 2 */ 880 char res51[12]; 881 uint eidr2; /* 0x50050 - External Interrupt Destination Register 2 */ 882 char res52[12]; 883 uint eivpr3; /* 0x50060 - External Interrupt Vector/Priority Register 3 */ 884 char res53[12]; 885 uint eidr3; /* 0x50070 - External Interrupt Destination Register 3 */ 886 char res54[12]; 887 uint eivpr4; /* 0x50080 - External Interrupt Vector/Priority Register 4 */ 888 char res55[12]; 889 uint eidr4; /* 0x50090 - External Interrupt Destination Register 4 */ 890 char res56[12]; 891 uint eivpr5; /* 0x500a0 - External Interrupt Vector/Priority Register 5 */ 892 char res57[12]; 893 uint eidr5; /* 0x500b0 - External Interrupt Destination Register 5 */ 894 char res58[12]; 895 uint eivpr6; /* 0x500c0 - External Interrupt Vector/Priority Register 6 */ 896 char res59[12]; 897 uint eidr6; /* 0x500d0 - External Interrupt Destination Register 6 */ 898 char res60[12]; 899 uint eivpr7; /* 0x500e0 - External Interrupt Vector/Priority Register 7 */ 900 char res61[12]; 901 uint eidr7; /* 0x500f0 - External Interrupt Destination Register 7 */ 902 char res62[12]; 903 uint eivpr8; /* 0x50100 - External Interrupt Vector/Priority Register 8 */ 904 char res63[12]; 905 uint eidr8; /* 0x50110 - External Interrupt Destination Register 8 */ 906 char res64[12]; 907 uint eivpr9; /* 0x50120 - External Interrupt Vector/Priority Register 9 */ 908 char res65[12]; 909 uint eidr9; /* 0x50130 - External Interrupt Destination Register 9 */ 910 char res66[12]; 911 uint eivpr10; /* 0x50140 - External Interrupt Vector/Priority Register 10 */ 912 char res67[12]; 913 uint eidr10; /* 0x50150 - External Interrupt Destination Register 10 */ 914 char res68[12]; 915 uint eivpr11; /* 0x50160 - External Interrupt Vector/Priority Register 11 */ 916 char res69[12]; 917 uint eidr11; /* 0x50170 - External Interrupt Destination Register 11 */ 918 char res70[140]; 919 uint iivpr0; /* 0x50200 - Internal Interrupt Vector/Priority Register 0 */ 920 char res71[12]; 921 uint iidr0; /* 0x50210 - Internal Interrupt Destination Register 0 */ 922 char res72[12]; 923 uint iivpr1; /* 0x50220 - Internal Interrupt Vector/Priority Register 1 */ 924 char res73[12]; 925 uint iidr1; /* 0x50230 - Internal Interrupt Destination Register 1 */ 926 char res74[12]; 927 uint iivpr2; /* 0x50240 - Internal Interrupt Vector/Priority Register 2 */ 928 char res75[12]; 929 uint iidr2; /* 0x50250 - Internal Interrupt Destination Register 2 */ 930 char res76[12]; 931 uint iivpr3; /* 0x50260 - Internal Interrupt Vector/Priority Register 3 */ 932 char res77[12]; 933 uint iidr3; /* 0x50270 - Internal Interrupt Destination Register 3 */ 934 char res78[12]; 935 uint iivpr4; /* 0x50280 - Internal Interrupt Vector/Priority Register 4 */ 936 char res79[12]; 937 uint iidr4; /* 0x50290 - Internal Interrupt Destination Register 4 */ 938 char res80[12]; 939 uint iivpr5; /* 0x502a0 - Internal Interrupt Vector/Priority Register 5 */ 940 char res81[12]; 941 uint iidr5; /* 0x502b0 - Internal Interrupt Destination Register 5 */ 942 char res82[12]; 943 uint iivpr6; /* 0x502c0 - Internal Interrupt Vector/Priority Register 6 */ 944 char res83[12]; 945 uint iidr6; /* 0x502d0 - Internal Interrupt Destination Register 6 */ 946 char res84[12]; 947 uint iivpr7; /* 0x502e0 - Internal Interrupt Vector/Priority Register 7 */ 948 char res85[12]; 949 uint iidr7; /* 0x502f0 - Internal Interrupt Destination Register 7 */ 950 char res86[12]; 951 uint iivpr8; /* 0x50300 - Internal Interrupt Vector/Priority Register 8 */ 952 char res87[12]; 953 uint iidr8; /* 0x50310 - Internal Interrupt Destination Register 8 */ 954 char res88[12]; 955 uint iivpr9; /* 0x50320 - Internal Interrupt Vector/Priority Register 9 */ 956 char res89[12]; 957 uint iidr9; /* 0x50330 - Internal Interrupt Destination Register 9 */ 958 char res90[12]; 959 uint iivpr10; /* 0x50340 - Internal Interrupt Vector/Priority Register 10 */ 960 char res91[12]; 961 uint iidr10; /* 0x50350 - Internal Interrupt Destination Register 10 */ 962 char res92[12]; 963 uint iivpr11; /* 0x50360 - Internal Interrupt Vector/Priority Register 11 */ 964 char res93[12]; 965 uint iidr11; /* 0x50370 - Internal Interrupt Destination Register 11 */ 966 char res94[12]; 967 uint iivpr12; /* 0x50380 - Internal Interrupt Vector/Priority Register 12 */ 968 char res95[12]; 969 uint iidr12; /* 0x50390 - Internal Interrupt Destination Register 12 */ 970 char res96[12]; 971 uint iivpr13; /* 0x503a0 - Internal Interrupt Vector/Priority Register 13 */ 972 char res97[12]; 973 uint iidr13; /* 0x503b0 - Internal Interrupt Destination Register 13 */ 974 char res98[12]; 975 uint iivpr14; /* 0x503c0 - Internal Interrupt Vector/Priority Register 14 */ 976 char res99[12]; 977 uint iidr14; /* 0x503d0 - Internal Interrupt Destination Register 14 */ 978 char res100[12]; 979 uint iivpr15; /* 0x503e0 - Internal Interrupt Vector/Priority Register 15 */ 980 char res101[12]; 981 uint iidr15; /* 0x503f0 - Internal Interrupt Destination Register 15 */ 982 char res102[12]; 983 uint iivpr16; /* 0x50400 - Internal Interrupt Vector/Priority Register 16 */ 984 char res103[12]; 985 uint iidr16; /* 0x50410 - Internal Interrupt Destination Register 16 */ 986 char res104[12]; 987 uint iivpr17; /* 0x50420 - Internal Interrupt Vector/Priority Register 17 */ 988 char res105[12]; 989 uint iidr17; /* 0x50430 - Internal Interrupt Destination Register 17 */ 990 char res106[12]; 991 uint iivpr18; /* 0x50440 - Internal Interrupt Vector/Priority Register 18 */ 992 char res107[12]; 993 uint iidr18; /* 0x50450 - Internal Interrupt Destination Register 18 */ 994 char res108[12]; 995 uint iivpr19; /* 0x50460 - Internal Interrupt Vector/Priority Register 19 */ 996 char res109[12]; 997 uint iidr19; /* 0x50470 - Internal Interrupt Destination Register 19 */ 998 char res110[12]; 999 uint iivpr20; /* 0x50480 - Internal Interrupt Vector/Priority Register 20 */ 1000 char res111[12];
1001 uint iidr20; /* 0x50490 - Internal Interrupt Destination Register 20 */ 1002 char res112[12]; 1003 uint iivpr21; /* 0x504a0 - Internal Interrupt Vector/Priority Register 21 */ 1004 char res113[12]; 1005 uint iidr21; /* 0x504b0 - Internal Interrupt Destination Register 21 */ 1006 char res114[12]; 1007 uint iivpr22; /* 0x504c0 - Internal Interrupt Vector/Priority Register 22 */ 1008 char res115[12]; 1009 uint iidr22; /* 0x504d0 - Internal Interrupt Destination Register 22 */ 1010 char res116[12]; 1011 uint iivpr23; /* 0x504e0 - Internal Interrupt Vector/Priority Register 23 */ 1012 char res117[12]; 1013 uint iidr23; /* 0x504f0 - Internal Interrupt Destination Register 23 */ 1014 char res118[12]; 1015 uint iivpr24; /* 0x50500 - Internal Interrupt Vector/Priority Register 24 */ 1016 char res119[12]; 1017 uint iidr24; /* 0x50510 - Internal Interrupt Destination Register 24 */ 1018 char res120[12]; 1019 uint iivpr25; /* 0x50520 - Internal Interrupt Vector/Priority Register 25 */ 1020 char res121[12]; 1021 uint iidr25; /* 0x50530 - Internal Interrupt Destination Register 25 */ 1022 char res122[12]; 1023 uint iivpr26; /* 0x50540 - Internal Interrupt Vector/Priority Register 26 */ 1024 char res123[12]; 1025 uint iidr26; /* 0x50550 - Internal Interrupt Destination Register 26 */ 1026 char res124[12]; 1027 uint iivpr27; /* 0x50560 - Internal Interrupt Vector/Priority Register 27 */ 1028 char res125[12]; 1029 uint iidr27; /* 0x50570 - Internal Interrupt Destination Register 27 */ 1030 char res126[12]; 1031 uint iivpr28; /* 0x50580 - Internal Interrupt Vector/Priority Register 28 */ 1032 char res127[12]; 1033 uint iidr28; /* 0x50590 - Internal Interrupt Destination Register 28 */ 1034 char res128[12]; 1035 uint iivpr29; /* 0x505a0 - Internal Interrupt Vector/Priority Register 29 */ 1036 char res129[12]; 1037 uint iidr29; /* 0x505b0 - Internal Interrupt Destination Register 29 */ 1038 char res130[12]; 1039 uint iivpr30; /* 0x505c0 - Internal Interrupt Vector/Priority Register 30 */ 1040 char res131[12]; 1041 uint iidr30; /* 0x505d0 - Internal Interrupt Destination Register 30 */ 1042 char res132[12]; 1043 uint iivpr31; /* 0x505e0 - Internal Interrupt Vector/Priority Register 31 */ 1044 char res133[12]; 1045 uint iidr31; /* 0x505f0 - Internal Interrupt Destination Register 31 */ 1046 char res134[4108]; 1047 uint mivpr0; /* 0x51600 - Messaging Interrupt Vector/Priority Register 0 */ 1048 char res135[12]; 1049 uint midr0; /* 0x51610 - Messaging Interrupt Destination Register 0 */ 1050 char res136[12]; 1051 uint mivpr1; /* 0x51620 - Messaging Interrupt Vector/Priority Register 1 */ 1052 char res137[12]; 1053 uint midr1; /* 0x51630 - Messaging Interrupt Destination Register 1 */ 1054 char res138[12]; 1055 uint mivpr2; /* 0x51640 - Messaging Interrupt Vector/Priority Register 2 */ 1056 char res139[12]; 1057 uint midr2; /* 0x51650 - Messaging Interrupt Destination Register 2 */ 1058 char res140[12]; 1059 uint mivpr3; /* 0x51660 - Messaging Interrupt Vector/Priority Register 3 */ 1060 char res141[12]; 1061 uint midr3; /* 0x51670 - Messaging Interrupt Destination Register 3 */ 1062 char res142[59852]; 1063 uint ipi0dr0; /* 0x60040 - Processor 0 Interprocessor Interrupt Dispatch Register 0 */ 1064 char res143[12]; 1065 uint ipi0dr1; /* 0x60050 - Processor 0 Interprocessor Interrupt Dispatch Register 1 */ 1066 char res144[12]; 1067 uint ipi0dr2; /* 0x60060 - Processor 0 Interprocessor Interrupt Dispatch Register 2 */ 1068 char res145[12]; 1069 uint ipi0dr3; /* 0x60070 - Processor 0 Interprocessor Interrupt Dispatch Register 3 */ 1070 char res146[12]; 1071 uint ctpr0; /* 0x60080 - Current Task Priority Register for Processor 0 */ 1072 char res147[12]; 1073 uint whoami0; /* 0x60090 - Who Am I Register for Processor 0 */ 1074 char res148[12]; 1075 uint iack0; /* 0x600a0 - Interrupt Acknowledge Register for Processor 0 */ 1076 char res149[12]; 1077 uint eoi0; /* 0x600b0 - End Of Interrupt Register for Processor 0 */ 1078 char res150[130892]; 1079} ccsr_pic_t; 1080 1081/* 1082 * CPM Block(0x8_0000-0xc_0000) 1083 */ 1084#ifndef CONFIG_CPM2 1085typedef struct ccsr_cpm { 1086 char res[262144]; 1087} ccsr_cpm_t; 1088#else 1089/* 1090 * 0x8000-0x8ffff:DPARM 1091 * 0x9000-0x90bff: General SIU 1092 */ 1093typedef struct ccsr_cpm_siu { 1094 char res1[80]; 1095 uint smaer; 1096 uint smser; 1097 uint smevr; 1098 char res2[4]; 1099 uint lmaer; 1100 uint lmser; 1101 uint lmevr; 1102 char res3[2964]; 1103} ccsr_cpm_siu_t; 1104 1105/* 0x90c00-0x90cff: Interrupt Controller */ 1106typedef struct ccsr_cpm_intctl { 1107 ushort sicr; 1108 char res1[2]; 1109 uint sivec; 1110 uint sipnrh; 1111 uint sipnrl; 1112 uint siprr; 1113 uint scprrh; 1114 uint scprrl; 1115 uint simrh; 1116 uint simrl; 1117 uint siexr; 1118 char res2[88]; 1119 uint sccr; 1120 char res3[124]; 1121} ccsr_cpm_intctl_t; 1122 1123/* 0x90d00-0x90d7f: input/output port */ 1124typedef struct ccsr_cpm_iop { 1125 uint pdira; 1126 uint ppara; 1127 uint psora; 1128 uint podra; 1129 uint pdata; 1130 char res1[12]; 1131 uint pdirb; 1132 uint pparb; 1133 uint psorb; 1134 uint podrb; 1135 uint pdatb; 1136 char res2[12]; 1137 uint pdirc; 1138 uint pparc; 1139 uint psorc; 1140 uint podrc; 1141 uint pdatc; 1142 char res3[12]; 1143 uint pdird; 1144 uint ppard; 1145 uint psord; 1146 uint podrd; 1147 uint pdatd; 1148 char res4[12]; 1149} ccsr_cpm_iop_t; 1150 1151/* 0x90d80-0x91017: CPM timers */ 1152typedef struct ccsr_cpm_timer { 1153 u_char tgcr1; 1154 char res1[3]; 1155 u_char tgcr2; 1156 char res2[11]; 1157 ushort tmr1; 1158 ushort tmr2; 1159 ushort trr1; 1160 ushort trr2; 1161 ushort tcr1; 1162 ushort tcr2; 1163 ushort tcn1; 1164 ushort tcn2; 1165 ushort tmr3; 1166 ushort tmr4; 1167 ushort trr3; 1168 ushort trr4; 1169 ushort tcr3; 1170 ushort tcr4; 1171 ushort tcn3; 1172 ushort tcn4; 1173 ushort ter1; 1174 ushort ter2; 1175 ushort ter3; 1176 ushort ter4; 1177 char res3[608]; 1178} ccsr_cpm_timer_t; 1179 1180/* 0x91018-0x912ff: SDMA */ 1181typedef struct ccsr_cpm_sdma { 1182 uchar sdsr; 1183 char res1[3]; 1184 uchar sdmr; 1185 char res2[739]; 1186} ccsr_cpm_sdma_t; 1187 1188/* 0x91300-0x9131f: FCC1 */ 1189typedef struct ccsr_cpm_fcc1 { 1190 uint gfmr; 1191 uint fpsmr; 1192 ushort ftodr; 1193 char res1[2]; 1194 ushort fdsr; 1195 char res2[2]; 1196 ushort fcce; 1197 char res3[2]; 1198 ushort fccm; 1199 char res4[2]; 1200 u_char fccs; 1201 char res5[3]; 1202 u_char ftirr_phy[4]; 1203} ccsr_cpm_fcc1_t; 1204 1205/* 0x91320-0x9133f: FCC2 */ 1206typedef struct ccsr_cpm_fcc2 { 1207 uint gfmr; 1208 uint fpsmr; 1209 ushort ftodr; 1210 char res1[2]; 1211 ushort fdsr; 1212 char res2[2]; 1213 ushort fcce; 1214 char res3[2]; 1215 ushort fccm; 1216 char res4[2]; 1217 u_char fccs; 1218 char res5[3]; 1219 u_char ftirr_phy[4]; 1220} ccsr_cpm_fcc2_t; 1221 1222/* 0x91340-0x9137f: FCC3 */ 1223typedef struct ccsr_cpm_fcc3 { 1224 uint gfmr; 1225 uint fpsmr; 1226 ushort ftodr; 1227 char res1[2]; 1228 ushort fdsr; 1229 char res2[2]; 1230 ushort fcce; 1231 char res3[2]; 1232 ushort fccm; 1233 char res4[2]; 1234 u_char fccs; 1235 char res5[3]; 1236 char res[36]; 1237} ccsr_cpm_fcc3_t; 1238 1239/* 0x91380-0x9139f: FCC1 extended */ 1240typedef struct ccsr_cpm_fcc1_ext { 1241 uint firper; 1242 uint firer; 1243 uint firsr_h; 1244 uint firsr_l; 1245 u_char gfemr; 1246 char res[15]; 1247 1248} ccsr_cpm_fcc1_ext_t; 1249 1250/* 0x913a0-0x913cf: FCC2 extended */ 1251typedef struct ccsr_cpm_fcc2_ext { 1252 uint firper; 1253 uint firer; 1254 uint firsr_h; 1255 uint firsr_l; 1256 u_char gfemr; 1257 char res[31]; 1258} ccsr_cpm_fcc2_ext_t; 1259 1260/* 0x913d0-0x913ff: FCC3 extended */ 1261typedef struct ccsr_cpm_fcc3_ext { 1262 u_char gfemr; 1263 char res[47]; 1264} ccsr_cpm_fcc3_ext_t; 1265 1266/* 0x91400-0x915ef: TC layers */ 1267typedef struct ccsr_cpm_tmp1 { 1268 char res[496]; 1269} ccsr_cpm_tmp1_t; 1270 1271/* 0x915f0-0x9185f: BRGs:5,6,7,8 */ 1272typedef struct ccsr_cpm_brg2 { 1273 uint brgc5; 1274 uint brgc6; 1275 uint brgc7; 1276 uint brgc8; 1277 char res[608]; 1278} ccsr_cpm_brg2_t; 1279 1280/* 0x91860-0x919bf: I2C */ 1281typedef struct ccsr_cpm_i2c { 1282 u_char i2mod; 1283 char res1[3]; 1284 u_char i2add; 1285 char res2[3]; 1286 u_char i2brg; 1287 char res3[3]; 1288 u_char i2com; 1289 char res4[3]; 1290 u_char i2cer; 1291 char res5[3]; 1292 u_char i2cmr; 1293 char res6[331]; 1294} ccsr_cpm_i2c_t; 1295 1296/* 0x919c0-0x919ef: CPM core */ 1297typedef struct ccsr_cpm_cp { 1298 uint cpcr; 1299 uint rccr; 1300 char res1[14]; 1301 ushort rter; 1302 char res2[2]; 1303 ushort rtmr; 1304 ushort rtscr; 1305 char res3[2]; 1306 uint rtsr; 1307 char res4[12]; 1308} ccsr_cpm_cp_t; 1309 1310/* 0x919f0-0x919ff: BRGs:1,2,3,4 */ 1311typedef struct ccsr_cpm_brg1 { 1312 uint brgc1; 1313 uint brgc2; 1314 uint brgc3; 1315 uint brgc4; 1316} ccsr_cpm_brg1_t; 1317 1318/* 0x91a00-0x91a9f: SCC1-SCC4 */ 1319typedef struct ccsr_cpm_scc { 1320 uint gsmrl; 1321 uint gsmrh; 1322 ushort psmr; 1323 char res1[2]; 1324 ushort todr; 1325 ushort dsr; 1326 ushort scce; 1327 char res2[2]; 1328 ushort sccm; 1329 char res3; 1330 u_char sccs; 1331 char res4[8]; 1332} ccsr_cpm_scc_t; 1333 1334/* 0x91a80-0x91a9f */ 1335typedef struct ccsr_cpm_tmp2 { 1336 char res[32]; 1337} ccsr_cpm_tmp2_t; 1338 1339/* 0x91aa0-0x91aff: SPI */ 1340typedef struct ccsr_cpm_spi { 1341 ushort spmode; 1342 char res1[4]; 1343 u_char spie; 1344 char res2[3]; 1345 u_char spim; 1346 char res3[2]; 1347 u_char spcom; 1348 char res4[82]; 1349} ccsr_cpm_spi_t; 1350 1351/* 0x91b00-0x91b1f: CPM MUX */ 1352typedef struct ccsr_cpm_mux { 1353 u_char cmxsi1cr; 1354 char res1; 1355 u_char cmxsi2cr; 1356 char res2; 1357 uint cmxfcr; 1358 uint cmxscr; 1359 char res3[2]; 1360 ushort cmxuar; 1361 char res4[16]; 1362} ccsr_cpm_mux_t; 1363 1364/* 0x91b20-0xbffff: SI,MCC,etc */ 1365typedef struct ccsr_cpm_tmp3 { 1366 char res[58592]; 1367} ccsr_cpm_tmp3_t; 1368 1369typedef struct ccsr_cpm_iram { 1370 unsigned long iram[8192]; 1371 char res[98304]; 1372} ccsr_cpm_iram_t; 1373 1374typedef struct ccsr_cpm { 1375 /* Some references are into the unique and known dpram spaces, 1376 * others are from the generic base. 1377 */ 1378#define im_dprambase im_dpram1 1379 u_char im_dpram1[16*1024]; 1380 char res1[16*1024]; 1381 u_char im_dpram2[16*1024]; 1382 char res2[16*1024]; 1383 ccsr_cpm_siu_t im_cpm_siu; /* SIU Configuration */ 1384 ccsr_cpm_intctl_t im_cpm_intctl; /* Interrupt Controller */ 1385 ccsr_cpm_iop_t im_cpm_iop; /* IO Port control/status */ 1386 ccsr_cpm_timer_t im_cpm_timer; /* CPM timers */ 1387 ccsr_cpm_sdma_t im_cpm_sdma; /* SDMA control/status */ 1388 ccsr_cpm_fcc1_t im_cpm_fcc1; 1389 ccsr_cpm_fcc2_t im_cpm_fcc2; 1390 ccsr_cpm_fcc3_t im_cpm_fcc3; 1391 ccsr_cpm_fcc1_ext_t im_cpm_fcc1_ext; 1392 ccsr_cpm_fcc2_ext_t im_cpm_fcc2_ext; 1393 ccsr_cpm_fcc3_ext_t im_cpm_fcc3_ext; 1394 ccsr_cpm_tmp1_t im_cpm_tmp1; 1395 ccsr_cpm_brg2_t im_cpm_brg2; 1396 ccsr_cpm_i2c_t im_cpm_i2c; 1397 ccsr_cpm_cp_t im_cpm_cp; 1398 ccsr_cpm_brg1_t im_cpm_brg1; 1399 ccsr_cpm_scc_t im_cpm_scc[4]; 1400 ccsr_cpm_tmp2_t im_cpm_tmp2; 1401 ccsr_cpm_spi_t im_cpm_spi; 1402 ccsr_cpm_mux_t im_cpm_mux; 1403 ccsr_cpm_tmp3_t im_cpm_tmp3; 1404 ccsr_cpm_iram_t im_cpm_iram; 1405} ccsr_cpm_t; 1406#endif 1407 1408/* 1409 * RapidIO Registers(0xc_0000-0xe_0000) 1410 */ 1411typedef struct ccsr_rio { 1412 uint didcar; /* 0xc0000 - Device Identity Capability Register */ 1413 uint dicar; /* 0xc0004 - Device Information Capability Register */ 1414 uint aidcar; /* 0xc0008 - Assembly Identity Capability Register */ 1415 uint aicar; /* 0xc000c - Assembly Information Capability Register */ 1416 uint pefcar; /* 0xc0010 - Processing Element Features Capability Register */ 1417 uint spicar; /* 0xc0014 - Switch Port Information Capability Register */ 1418 uint socar; /* 0xc0018 - Source Operations Capability Register */ 1419 uint docar; /* 0xc001c - Destination Operations Capability Register */ 1420 char res1[32]; 1421 uint msr; /* 0xc0040 - Mailbox Command And Status Register */ 1422 uint pwdcsr; /* 0xc0044 - Port-Write and Doorbell Command And Status Register */ 1423 char res2[4]; 1424 uint pellccsr; /* 0xc004c - Processing Element Logic Layer Control Command and Status Register */ 1425 char res3[12]; 1426 uint lcsbacsr; /* 0xc005c - Local Configuration Space Base Address Command and Status Register */ 1427 uint bdidcsr; /* 0xc0060 - Base Device ID Command and Status Register */ 1428 char res4[4]; 1429 uint hbdidlcsr; /* 0xc0068 - Host Base Device ID Lock Command and Status Register */ 1430 uint ctcsr; /* 0xc006c - Component Tag Command and Status Register */ 1431 char res5[144]; 1432 uint pmbh0csr; /* 0xc0100 - 8/16 LP-LVDS Port Maintenance Block Header 0 Command and Status Register */ 1433 char res6[28]; 1434 uint pltoccsr; /* 0xc0120 - Port Link Time-out Control Command and Status Register */ 1435 uint prtoccsr; /* 0xc0124 - Port Response Time-out Control Command and Status Register */ 1436 char res7[20]; 1437 uint pgccsr; /* 0xc013c - Port General Command and Status Register */ 1438 uint plmreqcsr; /* 0xc0140 - Port Link Maintenance Request Command and Status Register */ 1439 uint plmrespcsr; /* 0xc0144 - Port Link Maintenance Response Command and Status Register */ 1440 uint plascsr; /* 0xc0148 - Port Local Ackid Status Command and Status Register */ 1441 char res8[12]; 1442 uint pescsr; /* 0xc0158 - Port Error and Status Command and Status Register */ 1443 uint pccsr; /* 0xc015c - Port Control Command and Status Register */ 1444 char res9[65184]; 1445 uint cr; /* 0xd0000 - Port Control Command and Status Register */ 1446 char res10[12]; 1447 uint pcr; /* 0xd0010 - Port Configuration Register */ 1448 uint peir; /* 0xd0014 - Port Error Injection Register */ 1449 char res11[3048]; 1450 uint rowtar0; /* 0xd0c00 - RapidIO Outbound Window Translation Address Register 0 */ 1451 char res12[12]; 1452 uint rowar0; /* 0xd0c10 - RapidIO Outbound Attributes Register 0 */ 1453 char res13[12]; 1454 uint rowtar1; /* 0xd0c20 - RapidIO Outbound Window Translation Address Register 1 */ 1455 char res14[4]; 1456 uint rowbar1; /* 0xd0c28 - RapidIO Outbound Window Base Address Register 1 */ 1457 char res15[4]; 1458 uint rowar1; /* 0xd0c30 - RapidIO Outbound Attributes Register 1 */ 1459 char res16[12]; 1460 uint rowtar2; /* 0xd0c40 - RapidIO Outbound Window Translation Address Register 2 */ 1461 char res17[4]; 1462 uint rowbar2; /* 0xd0c48 - RapidIO Outbound Window Base Address Register 2 */ 1463 char res18[4]; 1464 uint rowar2; /* 0xd0c50 - RapidIO Outbound Attributes Register 2 */ 1465 char res19[12]; 1466 uint rowtar3; /* 0xd0c60 - RapidIO Outbound Window Translation Address Register 3 */ 1467 char res20[4]; 1468 uint rowbar3; /* 0xd0c68 - RapidIO Outbound Window Base Address Register 3 */ 1469 char res21[4]; 1470 uint rowar3; /* 0xd0c70 - RapidIO Outbound Attributes Register 3 */ 1471 char res22[12]; 1472 uint rowtar4; /* 0xd0c80 - RapidIO Outbound Window Translation Address Register 4 */ 1473 char res23[4]; 1474 uint rowbar4; /* 0xd0c88 - RapidIO Outbound Window Base Address Register 4 */ 1475 char res24[4]; 1476 uint rowar4; /* 0xd0c90 - RapidIO Outbound Attributes Register 4 */ 1477 char res25[12]; 1478 uint rowtar5; /* 0xd0ca0 - RapidIO Outbound Window Translation Address Register 5 */ 1479 char res26[4]; 1480 uint rowbar5; /* 0xd0ca8 - RapidIO Outbound Window Base Address Register 5 */ 1481 char res27[4]; 1482 uint rowar5; /* 0xd0cb0 - RapidIO Outbound Attributes Register 5 */ 1483 char res28[12]; 1484 uint rowtar6; /* 0xd0cc0 - RapidIO Outbound Window Translation Address Register 6 */ 1485 char res29[4]; 1486 uint rowbar6; /* 0xd0cc8 - RapidIO Outbound Window Base Address Register 6 */ 1487 char res30[4]; 1488 uint rowar6; /* 0xd0cd0 - RapidIO Outbound Attributes Register 6 */ 1489 char res31[12]; 1490 uint rowtar7; /* 0xd0ce0 - RapidIO Outbound Window Translation Address Register 7 */ 1491 char res32[4]; 1492 uint rowbar7; /* 0xd0ce8 - RapidIO Outbound Window Base Address Register 7 */ 1493 char res33[4]; 1494 uint rowar7; /* 0xd0cf0 - RapidIO Outbound Attributes Register 7 */ 1495 char res34[12]; 1496 uint rowtar8; /* 0xd0d00 - RapidIO Outbound Window Translation Address Register 8 */ 1497 char res35[4]; 1498 uint rowbar8; /* 0xd0d08 - RapidIO Outbound Window Base Address Register 8 */ 1499 char res36[4]; 1500 uint rowar8; /* 0xd0d10 - RapidIO Outbound Attributes Register 8 */ 1501 char res37[76]; 1502 uint riwtar4; /* 0xd0d60 - RapidIO Inbound Window Translation Address Register 4 */ 1503 char res38[4]; 1504 uint riwbar4; /* 0xd0d68 - RapidIO Inbound Window Base Address Register 4 */ 1505 char res39[4]; 1506 uint riwar4; /* 0xd0d70 - RapidIO Inbound Attributes Register 4 */ 1507 char res40[12]; 1508 uint riwtar3; /* 0xd0d80 - RapidIO Inbound Window Translation Address Register 3 */ 1509 char res41[4]; 1510 uint riwbar3; /* 0xd0d88 - RapidIO Inbound Window Base Address Register 3 */ 1511 char res42[4]; 1512 uint riwar3; /* 0xd0d90 - RapidIO Inbound Attributes Register 3 */ 1513 char res43[12]; 1514 uint riwtar2; /* 0xd0da0 - RapidIO Inbound Window Translation Address Register 2 */ 1515 char res44[4]; 1516 uint riwbar2; /* 0xd0da8 - RapidIO Inbound Window Base Address Register 2 */ 1517 char res45[4]; 1518 uint riwar2; /* 0xd0db0 - RapidIO Inbound Attributes Register 2 */ 1519 char res46[12]; 1520 uint riwtar1; /* 0xd0dc0 - RapidIO Inbound Window Translation Address Register 1 */ 1521 char res47[4]; 1522 uint riwbar1; /* 0xd0dc8 - RapidIO Inbound Window Base Address Register 1 */ 1523 char res48[4]; 1524 uint riwar1; /* 0xd0dd0 - RapidIO Inbound Attributes Register 1 */ 1525 char res49[12]; 1526 uint riwtar0; /* 0xd0de0 - RapidIO Inbound Window Translation Address Register 0 */ 1527 char res50[12]; 1528 uint riwar0; /* 0xd0df0 - RapidIO Inbound Attributes Register 0 */ 1529 char res51[12]; 1530 uint pnfedr; /* 0xd0e00 - Port Notification/Fatal Error Detect Register */ 1531 uint pnfedir; /* 0xd0e04 - Port Notification/Fatal Error Detect Register */ 1532 uint pnfeier; /* 0xd0e08 - Port Notification/Fatal Error Interrupt Enable Register */ 1533 uint pecr; /* 0xd0e0c - Port Error Control Register */ 1534 uint pepcsr0; /* 0xd0e10 - Port Error Packet/Control Symbol Register 0 */ 1535 uint pepr1; /* 0xd0e14 - Port Error Packet Register 1 */ 1536 uint pepr2; /* 0xd0e18 - Port Error Packet Register 2 */ 1537 char res52[4]; 1538 uint predr; /* 0xd0e20 - Port Recoverable Error Detect Register */ 1539 char res53[4]; 1540 uint pertr; /* 0xd0e28 - Port Error Recovery Threshold Register */ 1541 uint prtr; /* 0xd0e2c - Port Retry Threshold Register */ 1542 char res54[464]; 1543 uint omr; /* 0xd1000 - Outbound Mode Register */ 1544 uint osr; /* 0xd1004 - Outbound Status Register */ 1545 uint eodqtpar; /* 0xd1008 - Extended Outbound Descriptor Queue Tail Pointer Address Register */ 1546 uint odqtpar; /* 0xd100c - Outbound Descriptor Queue Tail Pointer Address Register */ 1547 uint eosar; /* 0xd1010 - Extended Outbound Unit Source Address Register */ 1548 uint osar; /* 0xd1014 - Outbound Unit Source Address Register */ 1549 uint odpr; /* 0xd1018 - Outbound Destination Port Register */ 1550 uint odatr; /* 0xd101c - Outbound Destination Attributes Register */ 1551 uint odcr; /* 0xd1020 - Outbound Doubleword Count Register */ 1552 uint eodqhpar; /* 0xd1024 - Extended Outbound Descriptor Queue Head Pointer Address Register */ 1553 uint odqhpar; /* 0xd1028 - Outbound Descriptor Queue Head Pointer Address Register */ 1554 char res55[52]; 1555 uint imr; /* 0xd1060 - Outbound Mode Register */ 1556 uint isr; /* 0xd1064 - Inbound Status Register */ 1557 uint eidqtpar; /* 0xd1068 - Extended Inbound Descriptor Queue Tail Pointer Address Register */ 1558 uint idqtpar; /* 0xd106c - Inbound Descriptor Queue Tail Pointer Address Register */ 1559 uint eifqhpar; /* 0xd1070 - Extended Inbound Frame Queue Head Pointer Address Register */ 1560 uint ifqhpar; /* 0xd1074 - Inbound Frame Queue Head Pointer Address Register */ 1561 char res56[1000]; 1562 uint dmr; /* 0xd1460 - Doorbell Mode Register */ 1563 uint dsr; /* 0xd1464 - Doorbell Status Register */ 1564 uint edqtpar; /* 0xd1468 - Extended Doorbell Queue Tail Pointer Address Register */ 1565 uint dqtpar; /* 0xd146c - Doorbell Queue Tail Pointer Address Register */ 1566 uint edqhpar; /* 0xd1470 - Extended Doorbell Queue Head Pointer Address Register */ 1567 uint dqhpar; /* 0xd1474 - Doorbell Queue Head Pointer Address Register */ 1568 char res57[104]; 1569 uint pwmr; /* 0xd14e0 - Port-Write Mode Register */ 1570 uint pwsr; /* 0xd14e4 - Port-Write Status Register */ 1571 uint epwqbar; /* 0xd14e8 - Extended Port-Write Queue Base Address Register */ 1572 uint pwqbar; /* 0xd14ec - Port-Write Queue Base Address Register */ 1573 char res58[60176]; 1574} ccsr_rio_t; 1575 1576/* Quick Engine Block Pin Muxing Registers (0xe_0100 - 0xe_01bf) */ 1577typedef struct par_io { 1578 uint cpodr; /* 0x100 */ 1579 uint cpdat; /* 0x104 */ 1580 uint cpdir1; /* 0x108 */ 1581 uint cpdir2; /* 0x10c */ 1582 uint cppar1; /* 0x110 */ 1583 uint cppar2; /* 0x114 */ 1584 char res[8]; 1585}par_io_t; 1586 1587/* 1588 * Global Utilities Register Block(0xe_0000-0xf_ffff) 1589 */ 1590typedef struct ccsr_gur { 1591 uint porpllsr; /* 0xe0000 - POR PLL ratio status register */ 1592#ifdef CONFIG_MPC8536 1593#define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 1594#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 1595#else 1596#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003e00 1597#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 9 1598#endif 1599 uint porbmsr; /* 0xe0004 - POR boot mode status register */ 1600#define MPC85xx_PORBMSR_HA 0x00070000 1601 uint porimpscr; /* 0xe0008 - POR I/O impedance status and control register */ 1602 uint pordevsr; /* 0xe000c - POR I/O device status regsiter */ 1603#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000 1604#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000 1605#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000 1606#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000 1607#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000 1608#define MPC85xx_PORDEVSR_PCI1 0x00800000 1609#define MPC85xx_PORDEVSR_IO_SEL 0x00780000 1610#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000 1611#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000 1612#define MPC85xx_PORDEVSR_PCI1_PCI32 0x00010000 1613#define MPC85xx_PORDEVSR_PCI1_SPD 0x00008000 1614#define MPC85xx_PORDEVSR_PCI2_SPD 0x00004000 1615#define MPC85xx_PORDEVSR_DRAM_RTYPE 0x00000060 1616#define MPC85xx_PORDEVSR_RIO_CTLS 0x00000008 1617#define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 1618 uint pordbgmsr; /* 0xe0010 - POR debug mode status register */ 1619 uint pordevsr2; /* 0xe0014 - POR I/O device status regsiter 2 */ 1620/* The 8544 RM says this is bit 26, but it's really bit 24 */ 1621#define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 1622 char res1[8]; 1623 uint gpporcr; /* 0xe0020 - General-purpose POR configuration register */ 1624 char res2[12]; 1625 uint gpiocr; /* 0xe0030 - GPIO control register */ 1626 char res3[12]; 1627#if defined(CONFIG_MPC8569) 1628 uint plppar1; 1629 /* 0xe0040 - Platform port pin assignment register 1 */ 1630 uint plppar2; 1631 /* 0xe0044 - Platform port pin assignment register 2 */ 1632 uint plpdir1; 1633 /* 0xe0048 - Platform port pin direction register 1 */ 1634 uint plpdir2; 1635 /* 0xe004c - Platform port pin direction register 2 */ 1636#else 1637 uint gpoutdr; /* 0xe0040 - General-purpose output data register */ 1638 char res4[12]; 1639#endif 1640 uint gpindr; /* 0xe0050 - General-purpose input data register */ 1641 char res5[12]; 1642 uint pmuxcr; /* 0xe0060 - Alternate function signal multiplex control */ 1643#define MPC85xx_PMUXCR_SD_DATA 0x80000000 1644#define MPC85xx_PMUXCR_SDHC_CD 0x40000000 1645#define MPC85xx_PMUXCR_SDHC_WP 0x20000000 1646 char res6[12]; 1647 uint devdisr; /* 0xe0070 - Device disable control */ 1648#define MPC85xx_DEVDISR_PCI1 0x80000000 1649#define MPC85xx_DEVDISR_PCI2 0x40000000 1650#define MPC85xx_DEVDISR_PCIE 0x20000000 1651#define MPC85xx_DEVDISR_LBC 0x08000000 1652#define MPC85xx_DEVDISR_PCIE2 0x04000000 1653#define MPC85xx_DEVDISR_PCIE3 0x02000000 1654#define MPC85xx_DEVDISR_SEC 0x01000000 1655#define MPC85xx_DEVDISR_SRIO 0x00080000 1656#define MPC85xx_DEVDISR_RMSG 0x00040000 1657#define MPC85xx_DEVDISR_DDR 0x00010000 1658#define MPC85xx_DEVDISR_CPU 0x00008000 1659#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU 1660#define MPC85xx_DEVDISR_TB 0x00004000 1661#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB 1662#define MPC85xx_DEVDISR_CPU1 0x00002000 1663#define MPC85xx_DEVDISR_TB1 0x00001000 1664#define MPC85xx_DEVDISR_DMA 0x00000400 1665#define MPC85xx_DEVDISR_TSEC1 0x00000080 1666#define MPC85xx_DEVDISR_TSEC2 0x00000040 1667#define MPC85xx_DEVDISR_TSEC3 0x00000020 1668#define MPC85xx_DEVDISR_TSEC4 0x00000010 1669#define MPC85xx_DEVDISR_I2C 0x00000004 1670#define MPC85xx_DEVDISR_DUART 0x00000002 1671 char res7[12]; 1672 uint powmgtcsr; /* 0xe0080 - Power management status and control register */ 1673 char res8[12]; 1674 uint mcpsumr; /* 0xe0090 - Machine check summary register */ 1675 char res9[12]; 1676 uint pvr; /* 0xe00a0 - Processor version register */ 1677 uint svr; /* 0xe00a4 - System version register */ 1678 char res10a[8]; 1679 uint rstcr; /* 0xe00b0 - Reset control register */ 1680#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569) 1681 char res10b[76]; 1682 par_io_t qe_par_io[7]; /* 0xe0100 - 0xe01bf */ 1683 char res10c[3136]; 1684#else 1685 char res10b[3404]; 1686#endif 1687 uint clkocr; /* 0xe0e00 - Clock out select register */ 1688 char res11[12]; 1689 uint ddrdllcr; /* 0xe0e10 - DDR DLL control register */ 1690 char res12[12]; 1691 uint lbcdllcr; /* 0xe0e20 - LBC DLL control register */ 1692 char res13[248]; 1693 uint lbiuiplldcr0; /* 0xe0f1c -- LBIU PLL Debug Reg 0 */ 1694 uint lbiuiplldcr1; /* 0xe0f20 -- LBIU PLL Debug Reg 1 */ 1695 uint ddrioovcr; /* 0xe0f24 - DDR IO Override Control */ 1696 uint tsec12ioovcr; /* 0xe0f28 - eTSEC 1/2 IO override control */ 1697 uint tsec34ioovcr; /* 0xe0f2c - eTSEC 3/4 IO override control */ 1698 char res15[61648]; /* 0xe0f30 to 0xefffff */ 1699} ccsr_gur_t; 1700 1701#define CONFIG_SYS_MPC85xx_GUTS_OFFSET (0xE0000) 1702#define CONFIG_SYS_MPC85xx_GUTS_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) 1703#define CONFIG_SYS_MPC85xx_ECM_OFFSET (0x0000) 1704#define CONFIG_SYS_MPC85xx_ECM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) 1705#define CONFIG_SYS_MPC85xx_DDR_OFFSET (0x2000) 1706#define CONFIG_SYS_MPC85xx_DDR_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET) 1707#define CONFIG_SYS_MPC85xx_DDR2_OFFSET (0x6000) 1708#define CONFIG_SYS_MPC85xx_DDR2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET) 1709#define CONFIG_SYS_MPC85xx_LBC_OFFSET (0x5000) 1710#define CONFIG_SYS_MPC85xx_LBC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) 1711#define CONFIG_SYS_MPC85xx_ESPI_OFFSET (0x7000) 1712#define CONFIG_SYS_MPC85xx_ESPI_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) 1713#define CONFIG_SYS_MPC85xx_PCIX_OFFSET (0x8000) 1714#define CONFIG_SYS_MPC85xx_PCIX_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) 1715#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET (0x9000) 1716#define CONFIG_SYS_MPC85xx_PCIX2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) 1717#define CONFIG_SYS_MPC85xx_SATA1_OFFSET (0x18000) 1718#define CONFIG_SYS_MPC85xx_SATA1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) 1719#define CONFIG_SYS_MPC85xx_SATA2_OFFSET (0x19000) 1720#define CONFIG_SYS_MPC85xx_SATA2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) 1721#define CONFIG_SYS_MPC85xx_L2_OFFSET (0x20000) 1722#define CONFIG_SYS_MPC85xx_L2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) 1723#define CONFIG_SYS_MPC85xx_DMA_OFFSET (0x21000) 1724#define CONFIG_SYS_MPC85xx_DMA_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) 1725#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET (0x2e000) 1726#define CONFIG_SYS_MPC85xx_ESDHC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) 1727#define CONFIG_SYS_MPC85xx_PIC_OFFSET (0x40000) 1728#define CONFIG_SYS_MPC85xx_PIC_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) 1729#define CONFIG_SYS_MPC85xx_CPM_OFFSET (0x80000) 1730#define CONFIG_SYS_MPC85xx_CPM_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET) 1731#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET (0xE3000) 1732#define CONFIG_SYS_MPC85xx_SERDES1_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) 1733#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET (0xE3100) 1734#define CONFIG_SYS_MPC85xx_SERDES2_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) 1735 1736#endif /*__IMMAP_85xx__*/ 1737