1/* 2 * (C) Copyright 2005, Psyent Corporation <www.psyent.com> 3 * Scott McNutt <smcnutt@psyent.com> 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24#ifndef __CONFIG_H 25#define __CONFIG_H 26 27/*------------------------------------------------------------------------ 28 * BOARD/CPU 29 *----------------------------------------------------------------------*/ 30#define CONFIG_EP1C20 1 /* EP1C20 board */ 31#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ 32 33#define CONFIG_SYS_RESET_ADDR 0x00000000 /* Hard-reset address */ 34#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ 35#define CONFIG_SYS_NIOS_SYSID_BASE 0x021208b8 /* System id address */ 36#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ 37 38/*------------------------------------------------------------------------ 39 * CACHE -- the following will support II/s and II/f. The II/s does not 40 * have dcache, so the cache instructions will behave as NOPs. 41 *----------------------------------------------------------------------*/ 42#define CONFIG_SYS_ICACHE_SIZE 4096 /* 4 KByte total */ 43#define CONFIG_SYS_ICACHELINE_SIZE 32 /* 32 bytes/line */ 44#define CONFIG_SYS_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ 45#define CONFIG_SYS_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ 46 47/*------------------------------------------------------------------------ 48 * MEMORY BASE ADDRESSES 49 *----------------------------------------------------------------------*/ 50#define CONFIG_SYS_FLASH_BASE 0x00000000 /* FLASH base addr */ 51#define CONFIG_SYS_FLASH_SIZE 0x00800000 /* 8 MByte */ 52#define CONFIG_SYS_SDRAM_BASE 0x01000000 /* SDRAM base addr */ 53#define CONFIG_SYS_SDRAM_SIZE 0x01000000 /* 16 MByte */ 54#define CONFIG_SYS_SRAM_BASE 0x02000000 /* SRAM base addr */ 55#define CONFIG_SYS_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/ 56 57/*------------------------------------------------------------------------ 58 * MEMORY ORGANIZATION 59 * -Monitor at top. 60 * -The heap is placed below the monitor. 61 * -Global data is placed below the heap. 62 * -The stack is placed below global data (&grows down). 63 *----------------------------------------------------------------------*/ 64#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 128k */ 65#define CONFIG_SYS_GBL_DATA_SIZE 128 /* Global data size rsvd*/ 66#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) 67 68#define CONFIG_SYS_MONITOR_BASE TEXT_BASE 69#define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN) 70#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_MALLOC_BASE - CONFIG_SYS_GBL_DATA_SIZE) 71#define CONFIG_SYS_INIT_SP CONFIG_SYS_GBL_DATA_OFFSET 72 73/*------------------------------------------------------------------------ 74 * FLASH (AM29LV065D) 75 *----------------------------------------------------------------------*/ 76#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max # sects per bank */ 77#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max # of flash banks */ 78#define CONFIG_SYS_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ 79#define CONFIG_SYS_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ 80#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size */ 81 82/*------------------------------------------------------------------------ 83 * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above 84 * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the 85 * reset address, no? This will keep the environment in user region 86 * of flash. NOTE: the monitor length must be multiple of sector size 87 * (which is common practice). 88 *----------------------------------------------------------------------*/ 89#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment in flash */ 90#define CONFIG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ 91#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ 92#define CONFIG_ENV_ADDR (CONFIG_SYS_RESET_ADDR + CONFIG_SYS_MONITOR_LEN) 93 94/*------------------------------------------------------------------------ 95 * CONSOLE 96 *----------------------------------------------------------------------*/ 97#if defined(CONFIG_CONSOLE_JTAG) 98#define CONFIG_SYS_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ 99#else 100#define CONFIG_SYS_NIOS_CONSOLE 0x02120840 /* UART base addr */ 101#endif 102 103#define CONFIG_SYS_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ 104#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ 105#define CONFIG_SYS_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ 106 107#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ 108 109/*------------------------------------------------------------------------ 110 * EPCS Device -- wne CONFIG_SYS_NIOS_EPCSBASE is defined code/commands for 111 * epcs device access is enabled. The base address is the epcs 112 * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK. 113 * The register base is currently at offset 0x600 from the memory base. 114 *----------------------------------------------------------------------*/ 115#define CONFIG_SYS_NIOS_EPCSBASE 0x02100200 /* EPCS register base */ 116 117/*------------------------------------------------------------------------ 118 * DEBUG 119 *----------------------------------------------------------------------*/ 120#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ 121 122/*------------------------------------------------------------------------ 123 * TIMEBASE -- 124 * 125 * The high res timer defaults to 1 msec. Since it includes the period 126 * registers, we can slow it down to 10 msec using TMRCNT. If the default 127 * period is acceptable, TMRCNT can be left undefined. 128 *----------------------------------------------------------------------*/ 129#define CONFIG_SYS_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ 130#define CONFIG_SYS_NIOS_TMRIRQ 3 /* Timer IRQ num */ 131#define CONFIG_SYS_NIOS_TMRMS 10 /* 10 msec per tick */ 132#define CONFIG_SYS_NIOS_TMRCNT (CONFIG_SYS_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) 133#define CONFIG_SYS_HZ (CONFIG_SYS_CLK_FREQ/(CONFIG_SYS_NIOS_TMRCNT + 1)) 134 135/*------------------------------------------------------------------------ 136 * STATUS LED -- Provides a simple blinking led. For Nios2 each board 137 * must implement its own led routines -- leds are, after all, 138 * board-specific, no? 139 *----------------------------------------------------------------------*/ 140#define CONFIG_SYS_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ 141#define CONFIG_STATUS_LED /* Enable status driver */ 142 143#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ 144#define STATUS_LED_STATE 1 /* Blinking */ 145#define STATUS_LED_PERIOD (500/CONFIG_SYS_NIOS_TMRMS) /* Every 500 msec */ 146 147/*------------------------------------------------------------------------ 148 * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... 149 * and really doesn't need any additional clutter. So I choose the lazy 150 * way out to avoid changes there -- define the base address to ensure 151 * cache bypass so there's no need to monkey with inx/outx macros. 152 *----------------------------------------------------------------------*/ 153#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ 154#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ 155#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ 156#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ 157 158#define CONFIG_ETHADDR 08:00:3e:26:0a:5b 159#define CONFIG_NETMASK 255.255.255.0 160#define CONFIG_IPADDR 192.168.2.21 161#define CONFIG_SERVERIP 192.168.2.16 162 163 164/* 165 * BOOTP options 166 */ 167#define CONFIG_BOOTP_BOOTFILESIZE 168#define CONFIG_BOOTP_BOOTPATH 169#define CONFIG_BOOTP_GATEWAY 170#define CONFIG_BOOTP_HOSTNAME 171 172 173/* 174 * Command line configuration. 175 */ 176#include <config_cmd_default.h> 177 178#define CONFIG_CMD_DHCP 179#define CONFIG_CMD_IRQ 180#define CONFIG_CMD_PING 181#define CONFIG_CMD_SAVES 182 183#undef CONFIG_CMD_BOOTD 184#undef CONFIG_CMD_CONSOLE 185#undef CONFIG_CMD_FPGA 186#undef CONFIG_CMD_IMLS 187#undef CONFIG_CMD_ITEST 188#undef CONFIG_CMD_NFS 189#undef CONFIG_CMD_SETGETDCR 190#undef CONFIG_CMD_SOURCE 191#undef CONFIG_CMD_XIMG 192 193 194/*------------------------------------------------------------------------ 195 * MISC 196 *----------------------------------------------------------------------*/ 197#define CONFIG_SYS_LONGHELP /* Provide extended help*/ 198#define CONFIG_SYS_PROMPT "==> " /* Command prompt */ 199#define CONFIG_SYS_CBSIZE 256 /* Console I/O buf size */ 200#define CONFIG_SYS_MAXARGS 16 /* Max command args */ 201#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot arg buf size */ 202#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print buf size */ 203#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE /* Default load address */ 204#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE /* Start addr for test */ 205#define CONFIG_SYS_MEMTEST_END CONFIG_SYS_INIT_SP - 0x00020000 206 207#define CONFIG_SYS_HUSH_PARSER 208#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " 209 210#endif /* __CONFIG_H */ 211